Lines Matching +full:tegra20 +full:- +full:timer

1 /*-
32 	compatible = "compal,paz00", "nvidia,tegra20";
33 	#address-cells = <1>;
34 	#size-cells = <1>;
35 	interrupt-parent = <&GIC>;
37 	SOC: tegra20@0 {
38 		#address-cells = <1>;
39 		#size-cells = <1>;
40 		compatible = "simple-bus";
42 		bus-frequency = <0>;
44 		GIC: interrupt-controller@50041000 {
48 			interrupt-controller;
49 			#interrupt-cells = <1>;
53 			compatible = "arm,mpcore-timers";
54 			clock-frequency = < 50040200 >;
55 			#address-cells = <1>;
56 			#size-cells = <0>;
57 			reg =   < 0x50040200 0x100 >, /* Global Timer Registers */
58 				< 0x50040600 0x100 >; /* Private Timer Registers */
60 			interrupt-parent = <&GIC>;
66 			reg-shift = <2>;
68 			interrupt-parent = <&GIC>;
69 			clock-frequency = < 215654400 >;