Lines Matching +full:pci +full:- +full:host +full:- +full:cam +full:- +full:generic
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that
46 * combines a tri-speed ethernet MAC and PHY, with the following
54 * o 64-bit multicast hash table filter
55 * o 64 entry CAM filter
66 * receive data buffers must be aligned on a 32-bit boundary. This is
67 * not a problem where the VT6122 is used as a LOM device in x86-based
71 * The other issue has to do with the way 64-bit addresses are handled.
74 * I/O registers. If you only have a 32-bit system, then this isn't
75 * an issue, but if you have a 64-bit system and more than 4GB of
77 * in the same 48-bit 'segment.'
117 #include <dev/pci/pcireg.h>
118 #include <dev/pci/pcivar.h>
120 MODULE_DEPEND(vge, pci, 1, 1, 1);
124 /* "device miibus" required. See GENERIC if you get errors here. */
229 DRIVER_MODULE(vge, pci, vge_driver, 0, 0);
263 device_printf(sc->vge_dev, "EEPROM read timed out\n");
317 device_printf(sc->vge_dev, "failed to idle MII autopoll\n");
337 device_printf(sc->vge_dev, "failed to idle MII autopoll\n");
354 device_printf(sc->vge_dev, "failed to start MII autopoll\n");
374 /* Wait for the read command bit to self-clear. */
382 device_printf(sc->vge_dev, "MII read timed out\n");
410 /* Wait for the write command bit to self-clear. */
418 device_printf(sc->vge_dev, "MII write timed out\n");
434 * that none of the entries in the CAM filter are valid.
454 sc->vge_camidx = 0;
462 if (sc->vge_camidx == VGE_CAM_MAXADDRS)
465 /* Select the CAM data page. */
470 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);
472 /* Write the address to the CAM registers */
487 device_printf(sc->vge_dev, "setting CAM filter failed\n");
492 /* Select the CAM mask page. */
497 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
498 1<<(sc->vge_camidx & 7));
500 sc->vge_camidx++;
503 /* Turn off access to CAM. */
519 ifp = sc->vge_ifp;
533 if (sc->vge_camidx == VGE_CAM_MAXADDRS)
550 hashes[1] |= (1 << (h - 32));
556 * Program the multicast filter. We use the 64-entry CAM filter
578 * this host.
582 ifp = sc->vge_ifp;
601 if (sc->vge_camidx == VGE_CAM_MAXADDRS) {
628 device_printf(sc->vge_dev, "soft reset timed out\n");
637 * Probe for a VIA gigabit chip. Check the PCI vendor and device
647 while (t->vge_name != NULL) {
648 if ((pci_get_vendor(dev) == t->vge_vid) &&
649 (pci_get_device(dev) == t->vge_did)) {
650 device_set_desc(dev, t->vge_name);
678 ctx->vge_busaddr = segs[0].ds_addr;
691 * It seems old PCI controllers do not support DAC. DAC
698 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0)
705 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */
715 &sc->vge_cdata.vge_ring_tag);
717 device_printf(sc->vge_dev,
723 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */
733 &sc->vge_cdata.vge_tx_ring_tag);
735 device_printf(sc->vge_dev,
741 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */
751 &sc->vge_cdata.vge_rx_ring_tag);
753 device_printf(sc->vge_dev,
759 error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag,
760 (void **)&sc->vge_rdata.vge_tx_ring,
762 &sc->vge_cdata.vge_tx_ring_map);
764 device_printf(sc->vge_dev,
770 error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag,
771 sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring,
774 device_printf(sc->vge_dev,
778 sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr;
781 error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag,
782 (void **)&sc->vge_rdata.vge_rx_ring,
784 &sc->vge_cdata.vge_rx_ring_map);
786 device_printf(sc->vge_dev,
792 error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag,
793 sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring,
796 device_printf(sc->vge_dev,
800 sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr;
803 tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ;
804 rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ;
806 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) ||
808 VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) ||
810 device_printf(sc->vge_dev, "4GB boundary crossed, "
818 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0)
823 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */
833 &sc->vge_cdata.vge_buffer_tag);
835 device_printf(sc->vge_dev,
841 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */
851 &sc->vge_cdata.vge_tx_tag);
853 device_printf(sc->vge_dev, "could not create Tx DMA tag.\n");
858 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */
868 &sc->vge_cdata.vge_rx_tag);
870 device_printf(sc->vge_dev, "could not create Rx DMA tag.\n");
876 txd = &sc->vge_cdata.vge_txdesc[i];
877 txd->tx_m = NULL;
878 txd->tx_dmamap = NULL;
879 error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0,
880 &txd->tx_dmamap);
882 device_printf(sc->vge_dev,
888 if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0,
889 &sc->vge_cdata.vge_rx_sparemap)) != 0) {
890 device_printf(sc->vge_dev,
895 rxd = &sc->vge_cdata.vge_rxdesc[i];
896 rxd->rx_m = NULL;
897 rxd->rx_dmamap = NULL;
898 error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0,
899 &rxd->rx_dmamap);
901 device_printf(sc->vge_dev,
919 if (sc->vge_cdata.vge_tx_ring_tag != NULL) {
920 if (sc->vge_rdata.vge_tx_ring_paddr)
921 bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag,
922 sc->vge_cdata.vge_tx_ring_map);
923 if (sc->vge_rdata.vge_tx_ring)
924 bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag,
925 sc->vge_rdata.vge_tx_ring,
926 sc->vge_cdata.vge_tx_ring_map);
927 sc->vge_rdata.vge_tx_ring = NULL;
928 sc->vge_rdata.vge_tx_ring_paddr = 0;
929 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag);
930 sc->vge_cdata.vge_tx_ring_tag = NULL;
933 if (sc->vge_cdata.vge_rx_ring_tag != NULL) {
934 if (sc->vge_rdata.vge_rx_ring_paddr)
935 bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag,
936 sc->vge_cdata.vge_rx_ring_map);
937 if (sc->vge_rdata.vge_rx_ring)
938 bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag,
939 sc->vge_rdata.vge_rx_ring,
940 sc->vge_cdata.vge_rx_ring_map);
941 sc->vge_rdata.vge_rx_ring = NULL;
942 sc->vge_rdata.vge_rx_ring_paddr = 0;
943 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag);
944 sc->vge_cdata.vge_rx_ring_tag = NULL;
947 if (sc->vge_cdata.vge_tx_tag != NULL) {
949 txd = &sc->vge_cdata.vge_txdesc[i];
950 if (txd->tx_dmamap != NULL) {
951 bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag,
952 txd->tx_dmamap);
953 txd->tx_dmamap = NULL;
956 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag);
957 sc->vge_cdata.vge_tx_tag = NULL;
960 if (sc->vge_cdata.vge_rx_tag != NULL) {
962 rxd = &sc->vge_cdata.vge_rxdesc[i];
963 if (rxd->rx_dmamap != NULL) {
964 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag,
965 rxd->rx_dmamap);
966 rxd->rx_dmamap = NULL;
969 if (sc->vge_cdata.vge_rx_sparemap != NULL) {
970 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag,
971 sc->vge_cdata.vge_rx_sparemap);
972 sc->vge_cdata.vge_rx_sparemap = NULL;
974 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag);
975 sc->vge_cdata.vge_rx_tag = NULL;
978 if (sc->vge_cdata.vge_buffer_tag != NULL) {
979 bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag);
980 sc->vge_cdata.vge_buffer_tag = NULL;
982 if (sc->vge_cdata.vge_ring_tag != NULL) {
983 bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag);
984 sc->vge_cdata.vge_ring_tag = NULL;
1001 sc->vge_dev = dev;
1003 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1005 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0);
1013 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1016 if (sc->vge_res == NULL) {
1023 sc->vge_flags |= VGE_FLAG_PCIE;
1024 sc->vge_expcap = cap;
1026 sc->vge_flags |= VGE_FLAG_JUMBO;
1028 sc->vge_flags |= VGE_FLAG_PMCAP;
1029 sc->vge_pmcap = cap;
1037 sc->vge_flags |= VGE_FLAG_MSI;
1047 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1048 ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE);
1049 if (sc->vge_irq == NULL) {
1083 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0)
1084 sc->vge_phyaddr = 1;
1086 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) &
1095 ifp = sc->vge_ifp = if_alloc(IFT_ETHER);
1098 error = mii_attach(dev, &sc->vge_miibus, ifp, vge_ifmedia_upd,
1099 vge_ifmedia_sts, BMSR_DEFCAPMASK, sc->vge_phyaddr, MII_OFFSET_ANY,
1115 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0)
1122 if_setsendqlen(ifp, VGE_TX_DESC_CNT - 1);
1134 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE,
1135 NULL, vge_intr, sc, &sc->vge_intrhand);
1164 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized"));
1165 ifp = sc->vge_ifp;
1178 callout_drain(&sc->vge_watchdog);
1182 if (sc->vge_intrhand)
1183 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand);
1184 if (sc->vge_irq)
1186 sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq);
1187 if (sc->vge_flags & VGE_FLAG_MSI)
1189 if (sc->vge_res)
1191 PCIR_BAR(1), sc->vge_res);
1196 mtx_destroy(&sc->vge_mtx);
1207 rxd = &sc->vge_cdata.vge_rxdesc[prod];
1208 rxd->rx_desc->vge_sts = 0;
1209 rxd->rx_desc->vge_ctl = 0;
1219 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) {
1220 for (i = VGE_RXCHUNK; i > 0; i--) {
1221 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN);
1222 rxd = rxd->rxd_prev;
1224 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK;
1241 * This is part of an evil trick to deal with strict-alignment
1243 * on 32-bit boundaries, but that will hose strict-alignment
1245 * at the start of each buffer and for non-strict-alignment hosts,
1250 m->m_len = m->m_pkthdr.len = MCLBYTES;
1253 if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag,
1254 sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1260 rxd = &sc->vge_cdata.vge_rxdesc[prod];
1261 if (rxd->rx_m != NULL) {
1262 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap,
1264 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap);
1266 map = rxd->rx_dmamap;
1267 rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap;
1268 sc->vge_cdata.vge_rx_sparemap = map;
1269 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap,
1271 rxd->rx_m = m;
1273 rxd->rx_desc->vge_sts = 0;
1274 rxd->rx_desc->vge_ctl = 0;
1275 rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr));
1276 rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) |
1287 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) {
1288 for (i = VGE_RXCHUNK; i > 0; i--) {
1289 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN);
1290 rxd = rxd->rxd_prev;
1292 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK;
1307 sc->vge_cdata.vge_tx_prodidx = 0;
1308 sc->vge_cdata.vge_tx_considx = 0;
1309 sc->vge_cdata.vge_tx_cnt = 0;
1311 rd = &sc->vge_rdata;
1312 bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ);
1314 txd = &sc->vge_cdata.vge_txdesc[i];
1315 txd->tx_m = NULL;
1316 txd->tx_desc = &rd->vge_tx_ring[i];
1319 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1320 sc->vge_cdata.vge_tx_ring_map,
1335 sc->vge_cdata.vge_rx_prodidx = 0;
1336 sc->vge_cdata.vge_head = NULL;
1337 sc->vge_cdata.vge_tail = NULL;
1338 sc->vge_cdata.vge_rx_commit = 0;
1340 rd = &sc->vge_rdata;
1341 bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ);
1343 rxd = &sc->vge_cdata.vge_rxdesc[i];
1344 rxd->rx_m = NULL;
1345 rxd->rx_desc = &rd->vge_rx_ring[i];
1347 rxd->rxd_prev =
1348 &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1];
1350 rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1];
1355 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag,
1356 sc->vge_cdata.vge_rx_ring_map,
1359 sc->vge_cdata.vge_rx_commit = 0;
1374 ifp = sc->vge_ifp;
1379 rxd = &sc->vge_cdata.vge_rxdesc[i];
1380 if (rxd->rx_m != NULL) {
1381 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag,
1382 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
1383 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag,
1384 rxd->rx_dmamap);
1385 m_freem(rxd->rx_m);
1386 rxd->rx_m = NULL;
1391 txd = &sc->vge_cdata.vge_txdesc[i];
1392 if (txd->tx_m != NULL) {
1393 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag,
1394 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
1395 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag,
1396 txd->tx_dmamap);
1397 m_freem(txd->tx_m);
1398 txd->tx_m = NULL;
1412 dst = src - 1;
1414 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1417 m->m_data -= ETHER_ALIGN;
1437 ifp = sc->vge_ifp;
1439 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag,
1440 sc->vge_cdata.vge_rx_ring_map,
1443 prod = sc->vge_cdata.vge_rx_prodidx;
1447 cur_rx = &sc->vge_rdata.vge_rx_ring[prod];
1448 rxstat = le32toh(cur_rx->vge_sts);
1451 count--;
1453 rxctl = le32toh(cur_rx->vge_ctl);
1455 rxd = &sc->vge_cdata.vge_rxdesc[prod];
1456 m = rxd->rx_m;
1460 * either the first fragment in a multi-fragment receive,
1471 m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN;
1472 if (sc->vge_cdata.vge_head == NULL) {
1473 sc->vge_cdata.vge_head = m;
1474 sc->vge_cdata.vge_tail = m;
1476 m->m_flags &= ~M_PKTHDR;
1477 sc->vge_cdata.vge_tail->m_next = m;
1478 sc->vge_cdata.vge_tail = m;
1487 * match it against the CAM filter, it considers this
1488 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit.
1491 * We also want to receive bad-checksummed frames and
1492 * and frames with bad-length.
1499 * If this is part of a multi-fragment packet,
1515 if (sc->vge_cdata.vge_head != NULL) {
1516 m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN);
1523 if (m->m_len <= ETHER_CRC_LEN) {
1524 sc->vge_cdata.vge_tail->m_len -=
1525 (ETHER_CRC_LEN - m->m_len);
1528 m->m_len -= ETHER_CRC_LEN;
1529 m->m_flags &= ~M_PKTHDR;
1530 sc->vge_cdata.vge_tail->m_next = m;
1532 m = sc->vge_cdata.vge_head;
1533 m->m_flags |= M_PKTHDR;
1534 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1536 m->m_flags |= M_PKTHDR;
1537 m->m_pkthdr.len = m->m_len =
1538 (total_len - ETHER_CRC_LEN);
1544 m->m_pkthdr.rcvif = ifp;
1551 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1553 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1558 m->m_pkthdr.csum_flags |=
1560 m->m_pkthdr.csum_data = 0xffff;
1566 * The 32-bit rxctl register is stored in little-endian.
1567 * However, the 16-bit vlan tag is stored in big-endian,
1570 m->m_pkthdr.ether_vtag =
1572 m->m_flags |= M_VLANTAG;
1578 sc->vge_cdata.vge_head = NULL;
1579 sc->vge_cdata.vge_tail = NULL;
1583 sc->vge_cdata.vge_rx_prodidx = prod;
1584 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag,
1585 sc->vge_cdata.vge_rx_ring_map,
1588 if (sc->vge_cdata.vge_rx_commit != 0) {
1590 sc->vge_cdata.vge_rx_commit);
1591 sc->vge_cdata.vge_rx_commit = 0;
1608 ifp = sc->vge_ifp;
1610 if (sc->vge_cdata.vge_tx_cnt == 0)
1613 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1614 sc->vge_cdata.vge_tx_ring_map,
1621 cons = sc->vge_cdata.vge_tx_considx;
1622 prod = sc->vge_cdata.vge_tx_prodidx;
1624 cur_tx = &sc->vge_rdata.vge_tx_ring[cons];
1625 txstat = le32toh(cur_tx->vge_sts);
1628 sc->vge_cdata.vge_tx_cnt--;
1631 txd = &sc->vge_cdata.vge_txdesc[cons];
1632 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap,
1634 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap);
1636 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n",
1638 m_freem(txd->tx_m);
1639 txd->tx_m = NULL;
1640 txd->tx_desc->vge_frag[0].vge_addrhi = 0;
1642 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1643 sc->vge_cdata.vge_tx_ring_map,
1645 sc->vge_cdata.vge_tx_considx = cons;
1646 if (sc->vge_cdata.vge_tx_cnt == 0)
1647 sc->vge_timer = 0;
1658 ifp = sc->vge_ifp;
1664 sc->vge_flags &= ~VGE_FLAG_LINK;
1665 if_link_state_change(sc->vge_ifp,
1668 sc->vge_flags |= VGE_FLAG_LINK;
1669 if_link_state_change(sc->vge_ifp,
1686 * Restart MII auto-polling because link state change interrupt
1749 ifp = sc->vge_ifp;
1750 if ((sc->vge_flags & VGE_FLAG_SUSPENDED) != 0 ||
1796 /* Re-enable interrupts */
1820 if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) {
1822 padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len;
1845 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1846 m->m_pkthdr.len += padlen;
1847 m->m_len = m->m_pkthdr.len;
1851 txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx];
1853 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag,
1854 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1863 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag,
1864 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1872 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap,
1879 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1881 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1883 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1887 if ((m->m_flags & M_VLANTAG) != 0)
1888 cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG;
1889 txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16);
1905 txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) |
1908 frag = &txd->tx_desc->vge_frag[i];
1909 frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr));
1910 frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) |
1914 sc->vge_cdata.vge_tx_cnt++;
1915 VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx);
1921 txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC);
1922 txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN);
1923 txd->tx_m = m;
1955 if ((sc->vge_flags & VGE_FLAG_LINK) == 0 ||
1960 idx = sc->vge_cdata.vge_tx_prodidx;
1963 sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) {
1980 txd = &sc->vge_cdata.vge_txdesc[idx];
1981 txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q);
1993 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag,
1994 sc->vge_cdata.vge_tx_ring_map,
2001 sc->vge_timer = 5;
2018 if_t ifp = sc->vge_ifp;
2039 device_printf(sc->vge_dev, "no memory for Rx buffers.\n");
2047 CSR_WRITE_1(sc, VGE_PAR0 + i, if_getlladdr(sc->vge_ifp)[i]);
2076 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr));
2078 VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr));
2079 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);
2082 VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr));
2083 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);
2096 /* Init the cam filter. */
2109 * Disable hald-duplex flow control
2139 sc->vge_flags &= ~VGE_FLAG_LINK;
2144 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc);
2171 mii = device_get_softc(sc->vge_miibus);
2172 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2190 mii = device_get_softc(sc->vge_miibus);
2198 ifmr->ifm_active = mii->mii_media_active;
2199 ifmr->ifm_status = mii->mii_media_status;
2209 mii = device_get_softc(sc->vge_miibus);
2210 ife = mii->mii_media.ifm_cur;
2223 switch (IFM_SUBTYPE(ife->ifm_media)) {
2235 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
2242 device_printf(sc->vge_dev, "unknown media type: %x\n",
2243 IFM_SUBTYPE(ife->ifm_media));
2259 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > VGE_JUMBO_MTU)
2261 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
2262 if (ifr->ifr_mtu > ETHERMTU &&
2263 (sc->vge_flags & VGE_FLAG_JUMBO) == 0)
2266 if_setmtu(ifp, ifr->ifr_mtu);
2274 ((if_getflags(ifp) ^ sc->vge_if_flags) &
2281 sc->vge_if_flags = if_getflags(ifp);
2293 mii = device_get_softc(sc->vge_miibus);
2294 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2297 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
2300 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2372 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc);
2373 if (sc->vge_timer == 0 || --sc->vge_timer > 0)
2376 ifp = sc->vge_ifp;
2397 ifp = sc->vge_ifp;
2398 sc->vge_timer = 0;
2399 callout_stop(&sc->vge_watchdog);
2417 * Device suspend routine. Stop the interface and save some PCI
2431 sc->vge_flags |= VGE_FLAG_SUSPENDED;
2438 * Device resume routine. Restore some PCI settings in case the BIOS
2439 * doesn't, re-enable busmastering, and restart the interface if
2451 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) {
2453 pmstat = pci_read_config(sc->vge_dev,
2454 sc->vge_pmcap + PCIR_POWER_STATUS, 2);
2457 pci_write_config(sc->vge_dev,
2458 sc->vge_pmcap + PCIR_POWER_STATUS, pmstat, 2);
2462 /* Restart MII auto-polling. */
2464 ifp = sc->vge_ifp;
2470 sc->vge_flags &= ~VGE_FLAG_SUSPENDED;
2498 stats = &sc->vge_stats;
2499 ctx = device_get_sysctl_ctx(sc->vge_dev);
2500 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev));
2503 CTLFLAG_RW, &sc->vge_int_holdoff, 0, "interrupt holdoff");
2505 CTLFLAG_RW, &sc->vge_rx_coal_pkt, 0, "rx coalescing packet");
2507 CTLFLAG_RW, &sc->vge_tx_coal_pkt, 0, "tx coalescing packet");
2510 sc->vge_int_holdoff = VGE_INT_HOLDOFF_DEFAULT;
2511 resource_int_value(device_get_name(sc->vge_dev),
2512 device_get_unit(sc->vge_dev), "int_holdoff", &sc->vge_int_holdoff);
2513 sc->vge_rx_coal_pkt = VGE_RX_COAL_PKT_DEFAULT;
2514 resource_int_value(device_get_name(sc->vge_dev),
2515 device_get_unit(sc->vge_dev), "rx_coal_pkt", &sc->vge_rx_coal_pkt);
2516 sc->vge_tx_coal_pkt = VGE_TX_COAL_PKT_DEFAULT;
2517 resource_int_value(device_get_name(sc->vge_dev),
2518 device_get_unit(sc->vge_dev), "tx_coal_pkt", &sc->vge_tx_coal_pkt);
2529 &stats->rx_frames, "frames");
2531 &stats->rx_good_frames, "Good frames");
2533 &stats->rx_fifo_oflows, "FIFO overflows");
2535 &stats->rx_runts, "Too short frames");
2537 &stats->rx_runts_errs, "Too short frames with errors");
2539 &stats->rx_pkts_64, "64 bytes frames");
2541 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
2543 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
2545 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
2547 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
2549 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
2551 &stats->rx_pkts_1519_max, "1519 to max frames");
2553 &stats->rx_pkts_1519_max_errs, "1519 to max frames with error");
2555 &stats->rx_jumbos, "Jumbo frames");
2557 &stats->rx_crcerrs, "CRC errors");
2559 &stats->rx_pause_frames, "Pause frames");
2561 &stats->rx_alignerrs, "Alignment errors");
2563 &stats->rx_nobufs, "Frames with no buffer event");
2565 &stats->rx_symerrs, "Frames with symbol errors");
2567 &stats->rx_lenerrs, "Frames with length mismatched");
2574 &stats->tx_good_frames, "Good frames");
2576 &stats->tx_pkts_64, "64 bytes frames");
2578 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
2580 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
2582 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
2584 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
2586 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
2588 &stats->tx_jumbos, "Jumbo frames");
2590 &stats->tx_colls, "Collisions");
2592 &stats->tx_latecolls, "Late collisions");
2594 &stats->tx_pause, "Pause frames");
2597 &stats->tx_sqeerrs, "SQE errors");
2614 for (i = VGE_TIMEOUT; i > 0; i--) {
2620 device_printf(sc->vge_dev, "MIB clear timed out!\n");
2635 stats = &sc->vge_stats;
2636 ifp = sc->vge_ifp;
2640 for (i = VGE_TIMEOUT; i > 0; i--) {
2646 device_printf(sc->vge_dev, "MIB counter dump timed out!\n");
2666 stats->rx_frames += mib[VGE_MIB_RX_FRAMES];
2667 stats->rx_good_frames += mib[VGE_MIB_RX_GOOD_FRAMES];
2668 stats->rx_fifo_oflows += mib[VGE_MIB_RX_FIFO_OVERRUNS];
2669 stats->rx_runts += mib[VGE_MIB_RX_RUNTS];
2670 stats->rx_runts_errs += mib[VGE_MIB_RX_RUNTS_ERRS];
2671 stats->rx_pkts_64 += mib[VGE_MIB_RX_PKTS_64];
2672 stats->rx_pkts_65_127 += mib[VGE_MIB_RX_PKTS_65_127];
2673 stats->rx_pkts_128_255 += mib[VGE_MIB_RX_PKTS_128_255];
2674 stats->rx_pkts_256_511 += mib[VGE_MIB_RX_PKTS_256_511];
2675 stats->rx_pkts_512_1023 += mib[VGE_MIB_RX_PKTS_512_1023];
2676 stats->rx_pkts_1024_1518 += mib[VGE_MIB_RX_PKTS_1024_1518];
2677 stats->rx_pkts_1519_max += mib[VGE_MIB_RX_PKTS_1519_MAX];
2678 stats->rx_pkts_1519_max_errs += mib[VGE_MIB_RX_PKTS_1519_MAX_ERRS];
2679 stats->rx_jumbos += mib[VGE_MIB_RX_JUMBOS];
2680 stats->rx_crcerrs += mib[VGE_MIB_RX_CRCERRS];
2681 stats->rx_pause_frames += mib[VGE_MIB_RX_PAUSE];
2682 stats->rx_alignerrs += mib[VGE_MIB_RX_ALIGNERRS];
2683 stats->rx_nobufs += mib[VGE_MIB_RX_NOBUFS];
2684 stats->rx_symerrs += mib[VGE_MIB_RX_SYMERRS];
2685 stats->rx_lenerrs += mib[VGE_MIB_RX_LENERRS];
2688 stats->tx_good_frames += mib[VGE_MIB_TX_GOOD_FRAMES];
2689 stats->tx_pkts_64 += mib[VGE_MIB_TX_PKTS_64];
2690 stats->tx_pkts_65_127 += mib[VGE_MIB_TX_PKTS_65_127];
2691 stats->tx_pkts_128_255 += mib[VGE_MIB_TX_PKTS_128_255];
2692 stats->tx_pkts_256_511 += mib[VGE_MIB_TX_PKTS_256_511];
2693 stats->tx_pkts_512_1023 += mib[VGE_MIB_TX_PKTS_512_1023];
2694 stats->tx_pkts_1024_1518 += mib[VGE_MIB_TX_PKTS_1024_1518];
2695 stats->tx_jumbos += mib[VGE_MIB_TX_JUMBOS];
2696 stats->tx_colls += mib[VGE_MIB_TX_COLLS];
2697 stats->tx_pause += mib[VGE_MIB_TX_PAUSE];
2699 stats->tx_sqeerrs += mib[VGE_MIB_TX_SQEERRS];
2701 stats->tx_latecolls += mib[VGE_MIB_TX_LATECOLLS];
2734 * It's possible to use single-shot timer in VGE_CRS1 register
2739 * what single-shot timer value should be used in advance so
2744 CSR_WRITE_1(sc, VGE_TXSUPPTHR, sc->vge_tx_coal_pkt);
2748 CSR_WRITE_1(sc, VGE_RXSUPPTHR, sc->vge_rx_coal_pkt);
2753 if (sc->vge_tx_coal_pkt <= 0)
2757 if (sc->vge_rx_coal_pkt <= 0)
2763 if (sc->vge_int_holdoff > 0) {
2767 VGE_INT_HOLDOFF_USEC(sc->vge_int_holdoff));
2781 mii = device_get_softc(sc->vge_miibus);
2784 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2786 switch IFM_SUBTYPE(mii->mii_media_active) {
2799 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_100T2CR, 0);
2800 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_ANAR,
2802 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR,
2809 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
2811 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2824 device_printf(sc->vge_dev, "establishing link failed, "
2828 * No link, force MAC to have 100Mbps, full-duplex link.
2831 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
2832 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
2844 if ((sc->vge_flags & VGE_FLAG_PMCAP) == 0) {
2846 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR,
2852 ifp = sc->vge_ifp;
2872 /* Disable MII auto-polling. */
2891 pmstat = pci_read_config(sc->vge_dev, sc->vge_pmcap +
2896 pci_write_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS,