Lines Matching +full:write +full:- +full:1 +full:- +full:bps
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
33 #define UMCS7840_READ_LENGTH 1 /* bytes */
47 #define MCS7840_DEV_REG_SP1 0x00 /* Options for UART 1, R/W */
48 #define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1,
50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong
52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong
67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
73 #define MCS7840_DEV_REG_CLOCK_SELECT12 0x13 /* Clock source for ports 1 &
78 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */
94 * configuration for Port 1,
105 #define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 &
109 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port
110 * 1, contains number of
112 #define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port
113 * 1, contains number of
115 #define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port
118 #define MCS7840_DEV_REG_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port
121 #define MCS7840_DEV_REG_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port
124 #define MCS7840_DEV_REG_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port
127 #define MCS7840_DEV_REG_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port
130 #define MCS7840_DEV_REG_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port
134 * frames for Port 1, R/W */
136 * frames for Port 1, R/W */
138 * frames for Port 1, R/W */
140 * frames for Port 1, R/W */
144 * value for Bulk-Out for Port
145 * 1, R/W */
146 #define MCS7840_DEV_REG_THR_VAL_HIGH1 0x40 /* High 1 bit of threshold
147 * value for Bulk-Out and
148 * enable flag for Port 1, R/W */
150 * value for Bulk-Out for Port
152 #define MCS7840_DEV_REG_THR_VAL_HIGH2 0x42 /* High 1 bit of threshold
153 * value for Bulk-Out and
156 * value for Bulk-Out for Port
158 #define MCS7840_DEV_REG_THR_VAL_HIGH3 0x44 /* High 1 bit of threshold
159 * value for Bulk-Out and
162 * value for Bulk-Out for Port
164 #define MCS7840_DEV_REG_THR_VAL_HIGH4 0x46 /* High 1 bit of threshold
165 * value for Bulk-Out and
169 #define MCS7840_DEV_SPx_LOOP_PIPES 0x01 /* Loop Bulk-Out FIFO to the
170 * Bulk-In FIFO, default = 0 */
174 #define MCS7840_DEV_SPx_RESET_OUT_FIFO 0x04 /* Reset Bulk-Out FIFO */
175 #define MCS7840_DEV_SPx_RESET_IN_FIFO 0x08 /* Reset Bulk-In FIFO */
179 * = 115200 bps, default */
181 * = 230400 bps */
183 * = 403200 bps */
185 * = 460800 bps */
187 * = 806400 bps */
189 * = 921600 bps */
219 * RS-232/RS-485 mode,
230 * for Bulk-In FIFOs are swapped. One of buffers is used
240 * THIS ONE IS UNDOCUMENTED IN FULL DATASHEET, but e-mail from tech support
243 * authors as "number of port" indicator, grounded (0) for two-port
244 * devices and pulled-up to 1 for 4-port devices.
255 * Default PLL input frequency Fin is 12Mhz (on-chip).
260 #define MCS7840_DEV_PLL_DIV_M_MIN 1 /* Minimum value for M, 0 is
262 #define MCS7840_DEV_PLL_DIV_M_DEF 1 /* Default value for M */
267 #define MCS7840_DEV_PLL_DIV_N_MIN 1 /* Minimum value for N, 0 is
276 #define MCS7840_DEV_CLOCK_MUX_INEXTRN 0x01 /* External (device-depended)
281 * 20MHz-100MHz (default), 1 =
282 * 100MHz-300MHz range */
293 #define MCS7840_DEV_CLOCK_SELECT1_MASK 0x07 /* Bits for port 1 in
295 #define MCS7840_DEV_CLOCK_SELECT1_SHIFT 0 /* Shift for port 1in
318 * (device-dependend) */
325 * (default), 1: Reserved (?) */
326 #define MCS7840_DEV_MODE_SER_PRSNT 0x04 /* 0: Reserved, 1: Do not use
329 #define MCS7840_DEV_MODE_PLLBYPASS 0x08 /* 1: PLL output is bypassed,
331 #define MCS7840_DEV_MODE_PORBYPASS 0x10 /* 1: Power-On Reset is
334 * active, 1: 2 Serial Ports /
336 #define MCS7840_DEV_MODE_EEPROMWR 0x40 /* EEPROM write is enabled,
353 #define MCS7840_DEV_RX_SAMPLING1_MASK 0x0f /* Bits for port 1 in
355 #define MCS7840_DEV_RX_SAMPLING1_SHIFT 0 /* Shift for port 1in
375 #define MCS7840_DEV_ZERO_PERIODx_DEF 20 /* Number of Bulk-in requests
376 * befor sending zero-sized
381 * zero-sized replies for port
382 * 1, default */
384 * zero-sized replies for port
387 * zero-sized replies for port
390 * zero-sized replies for port
401 * 1, R/W */
402 #define MCS7840_DEV_REG_DCR1_1 0x05 /* Device contol register 1 for Port
403 * 1, R/W */
405 * 1, R/W */
408 #define MCS7840_DEV_REG_DCR1_2 0x17 /* Device contol register 1 for Port
414 #define MCS7840_DEV_REG_DCR1_3 0x1a /* Device contol register 1 for Port
420 #define MCS7840_DEV_REG_DCR1_4 0x1d /* Device contol register 1 for Port
428 * engaged, default = 1 */
431 * ONLY FOR PORT 1 */
432 #define MCS7840_DEV_DCR0_GPIO_MODE_IN 0x00 /* GPIO Mode - Input
434 * FOR PORT 1 */
435 #define MCS7840_DEV_DCR0_GPIO_MODE_OUT 0x08 /* GPIO Mode - Input
437 * FOR PORT 1 */
450 * ONLY FOR PORT 1 */
453 * PORT 1 */
456 * ONLY FOR PORT 1 */
459 * PORT 1 */
462 * PORT 1 */
477 * WORKS ONLY FOR PORT 1 */
481 * WORKS ONLY FOR PORT 1 */
486 * Wakeup will work only if DCR0_IRDA = 0 (RS-xxx mode) and
494 * default = 1 */
501 * otherwise, default = 1 */
503 #define MCS7840_DEV_DCR2_SHDN_POLARITY 0x80 /* 0: Pin 12 Active Low, 1:
510 * Thesse can be calculated as "1 << portnumber" for Bulk-out and
511 * "1 << (portnumber+1)" for Bulk-in
527 #define MCS7840_UART_REG_IER 0x01 /* Interrupt enable register -
529 #define MCS7840_UART_REG_FCR 0x02 /* FIFO Control register -
557 #define MCS7840_UART_FCR_RTL_1_1 0x00 /* L1 = 1, L2 = 1 */
558 #define MCS7840_UART_FCR_RTL_1_4 0x40 /* L1 = 1, L2 = 4 */
559 #define MCS7840_UART_FCR_RTL_1_8 0x80 /* L1 = 1, L2 = 8 */
560 #define MCS7840_UART_FCR_RTL_1_14 0xa0 /* L1 = 1, L2 = 14 */
580 #define MCS7840_UART_LCR_STOPB1 0x00 /* 1 stop bit in any case */
581 #define MCS7840_UART_LCR_STOPB2 0x04 /* 1.5-2 stop bits depends on
585 #define MCS7840_UART_LCR_PARITYON 0x08 /* Parity ON/OFF - ON */
636 #define MCS7840_UART_SCRATCHPAD_RS232 0x00 /* RS-485 disabled */
637 #define MCS7840_UART_SCRATCHPAD_RS485_DTRRX 0x80 /* RS-485 mode, DTR High
639 #define MCS7840_UART_SCRATCHPAD_RS485_DTRTX 0xc0 /* RS-485 mode, DTR High