61 	if (baudrate == 0)  in quicc_divisor()
67 	else if (divisor >= 0)  in quicc_divisor()
69 	if (divisor < 0 || divisor >= 8192)  in quicc_divisor()
90 	if (baudrate > 0) {  in quicc_param()
95 		    divisor | 0x10000);  in quicc_param()
98 	psmr = 0;  in quicc_param()
100 	case 5:		psmr |= 0x0000; break;  in quicc_param()
101 	case 6:		psmr |= 0x1000; break;  in quicc_param()
102 	case 7:		psmr |= 0x2000; break;  in quicc_param()
103 	case 8:		psmr |= 0x3000; break;  in quicc_param()
107 	case 1:		psmr |= 0x0000; break;  in quicc_param()
108 	case 2:		psmr |= 0x4000; break;  in quicc_param()
112 	case UART_PARITY_EVEN:	psmr |= 0x1a; break;  in quicc_param()
113 	case UART_PARITY_MARK:	psmr |= 0x1f; break;  in quicc_param()
114 	case UART_PARITY_NONE:	psmr |= 0x00; break;  in quicc_param()
115 	case UART_PARITY_ODD:	psmr |= 0x10; break;  in quicc_param()
116 	case UART_PARITY_SPACE:	psmr |= 0x15; break;  in quicc_param()
120 	return (0);  in quicc_param()
128 	if (bas->rclk == 0)  in quicc_setup()
132 	 * GSMR_L = 0x00028034  in quicc_setup()
133 	 * GSMR_H = 0x00000020  in quicc_setup()
137 	quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);  in quicc_setup()
138 	quicc_write2(bas, QUICC_REG_SCC_SCCM(bas->chan - 1), 0x0027);  in quicc_setup()
164 	return (0);  in quicc_probe()
187 	while (quicc_read2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit)) & 0x2000)  in quicc_putc()
190 	toseq = 0x2000 | (c & 0xff);  in quicc_putc()
200 	return ((quicc_read2(bas, rb) & 0x8000) ? 0 : 1);  in quicc_rxready()
214 	while ((sc = quicc_read2(bas, rb)) & 0x8000) {  in quicc_getc()
222 	quicc_write2(bas, rb, sc | 0x8000);  in quicc_getc()
264 	{ 0, 0 }
274 	.uc_rshift = 0
304 	quicc_write2(bas, rb, st | 0x9000);  in quicc_bus_attach()
308 	return (0);  in quicc_bus_attach()
315 	return (0);  in quicc_bus_detach()
322 	return (0);  in quicc_bus_flush()
336 		dummy = 0;  in quicc_bus_getsig()
354 	error = 0;  in quicc_bus_ioctl()
360 		brg = quicc_read4(bas, QUICC_REG_BRG(bas->chan - 1)) & 0x1fff;  in quicc_bus_ioctl()
381 	ipend = 0;  in quicc_bus_ipend()
385 	quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0);  in quicc_bus_ipend()
387 	if (scce & 0x0001)  in quicc_bus_ipend()
389 	if (scce & 0x0002)  in quicc_bus_ipend()
391 	if (scce & 0x0004)  in quicc_bus_ipend()
393 	if (scce & 0x0020)  in quicc_bus_ipend()
425 	return (0);  in quicc_bus_probe()
441 	quicc_write2(bas, rb, st | 0x9000);  in quicc_bus_receive()
443 	return (0);  in quicc_bus_receive()
467 	return (0);  in quicc_bus_setsig()
482 	*buf = sc->sc_txbuf[0];  in quicc_bus_transmit()
484 	quicc_write2(bas, tb, st | 0x9000);  in quicc_bus_transmit()
487 	return (0);  in quicc_bus_transmit()
501 	quicc_write2(bas, rb, st & ~0x9000);  in quicc_bus_grab()
516 	quicc_write2(bas, rb, st | 0x9000);  in quicc_bus_ungrab()