Lines Matching full:receive
62 /* TSEC Receive Control and Status Registers */
63 #define TSEC_REG_RCTRL 0x300 /* Receive control register */
64 #define TSEC_REG_RSTAT 0x304 /* Receive status register */
66 #define TSEC_REG_RXIC 0x310 /* Receive interrupt coalescing
69 #define TSEC_REG_MRBLR 0x340 /* Maximum receive buffer length register */
91 /* TSEC Transmit and Receive Counters */
92 #define TSEC_REG_MON_TR64 0x680 /* Transmit and receive 64-byte
94 #define TSEC_REG_MON_TR127 0x684 /* Transmit and receive 65-127 byte
96 #define TSEC_REG_MON_TR255 0x688 /* Transmit and receive 128-255 byte
98 #define TSEC_REG_MON_TR511 0x68c /* Transmit and receive 256-511 byte
100 #define TSEC_REG_MON_TR1K 0x690 /* Transmit and receive 512-1023 byte
102 #define TSEC_REG_MON_TRMAX 0x694 /* Transmit and receive 1024-1518 byte
104 #define TSEC_REG_MON_TRMGV 0x698 /* Transmit and receive 1519-1522 byte
107 /* TSEC Receive Counters */
108 #define TSEC_REG_MON_RBYT 0x69c /* Receive byte counter register */
109 #define TSEC_REG_MON_RPKT 0x6a0 /* Receive packet counter register */
110 #define TSEC_REG_MON_RFCS 0x6a4 /* Receive FCS error counter register */
111 #define TSEC_REG_MON_RMCA 0x6a8 /* Receive multicast packet counter
113 #define TSEC_REG_MON_RBCA 0x6ac /* Receive broadcast packet counter
115 #define TSEC_REG_MON_RXCF 0x6b0 /* Receive control frame packet counter
117 #define TSEC_REG_MON_RXPF 0x6b4 /* Receive pause frame packet counter
119 #define TSEC_REG_MON_RXUO 0x6b8 /* Receive unknown OP code counter
121 #define TSEC_REG_MON_RALN 0x6bc /* Receive alignment error counter
123 #define TSEC_REG_MON_RFLR 0x6c0 /* Receive frame length error counter
125 #define TSEC_REG_MON_RCDE 0x6c4 /* Receive code error counter register */
126 #define TSEC_REG_MON_RCSE 0x6c8 /* Receive carrier sense error counter
128 #define TSEC_REG_MON_RUND 0x6cc /* Receive undersize packet counter
130 #define TSEC_REG_MON_ROVR 0x6d0 /* Receive oversize packet counter
132 #define TSEC_REG_MON_RFRG 0x6d4 /* Receive fragments counter register */
133 #define TSEC_REG_MON_RJBR 0x6d8 /* Receive jabber counter register */
134 #define TSEC_REG_MON_RDRP 0x6dc /* Receive drop counter register */
208 #define TSEC_DMACTRL_GRS 0x00000010 /* Graceful receive stop */
222 #define TSEC_RCTRL_RSF 0x00000004 /* Receive short frame mode */
235 #define TSEC_IEVENT_BABR 0x80000000 /* Babbling receive error */
236 #define TSEC_IEVENT_RXC 0x40000000 /* Receive control interrupt */
250 #define TSEC_IEVENT_RXB 0x00008000 /* Receive buffer */
253 #define TSEC_IEVENT_GRSC 0x00000100 /* Graceful receive stop complete */
254 #define TSEC_IEVENT_RXF 0x00000080 /* Receive frame interrupt */
257 #define TSEC_IMASK_RXCEN 0x40000000 /* Receive control interrupt */
270 #define TSEC_IMASK_RXBEN 0x00008000 /* Receive buffer interrupt */
273 #define TSEC_IMASK_GRSCEN 0x00000100 /* Graceful receive stop complete interrupt */
274 #define TSEC_IMASK_RXFEN 0x00000080 /* Receive frame interrupt */
282 #define TSEC_MACCFG1_RESET_RX_MC 0x00080000 /* Reset receive MAC control block */
284 #define TSEC_MACCFG1_RESET_RX_FUN 0x00020000 /* Reset receive function block */
287 #define TSEC_MACCFG1_RX_FLOW 0x00000020 /* Receive flow */
289 #define TSEC_MACCFG1_SYNCD_RX_EN 0x00000008 /* Receive enable synchronized
290 * to the receive stream (Read-only) */
291 #define TSEC_MACCFG1_RX_EN 0x00000004 /* Receive enable */
347 /* Receive Data Buffer Descriptor (RxBD) Field Descriptions */
349 #define TSEC_RXBD_RO1 0x4000 /* Receive software ownership bit */
382 /* Receive Path Off-Load Frame Control Block flags */