Lines Matching +full:spi +full:- +full:lsb +full:- +full:first

1 /*-
40 #include <dev/spibus/spi.h>
58 #define	 AW_SPI_TCR_FBS		(1 << 12)	/* First Transmit Bit Select (1 == LSB) */
126 	{ "allwinner,sun8i-h3-spi",		1 },
133 	{ -1, 0 }
156 #define	AW_SPI_LOCK(sc)			mtx_lock(&(sc)->mtx)
157 #define	AW_SPI_UNLOCK(sc)		mtx_unlock(&(sc)->mtx)
158 #define	AW_SPI_ASSERT_LOCKED(sc)	mtx_assert(&(sc)->mtx, MA_OWNED)
159 #define	AW_SPI_READ_1(sc, reg)		bus_read_1((sc)->res[0], (reg))
160 #define	AW_SPI_WRITE_1(sc, reg, val)	bus_write_1((sc)->res[0], (reg), (val))
161 #define	AW_SPI_READ_4(sc, reg)		bus_read_4((sc)->res[0], (reg))
162 #define	AW_SPI_WRITE_4(sc, reg, val)	bus_write_4((sc)->res[0], (reg), (val))
175 	if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
178 	device_set_desc(dev, "Allwinner SPI");
189 	sc->dev = dev;
191 	mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
193 	if (bus_alloc_resources(dev, aw_spi_spec, sc->res) != 0) {
199 	if (bus_setup_intr(dev, sc->res[1],
201 	    &sc->intrhand)) {
202 		bus_release_resources(dev, aw_spi_spec, sc->res);
207 	/* De-assert reset */
208 	if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst_ahb) == 0) {
209 		error = hwreset_deassert(sc->rst_ahb);
211 			device_printf(dev, "cannot de-assert reset\n");
217 	error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->clk_ahb);
222 	error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_mod);
227 	error = clk_enable(sc->clk_ahb);
232 	error = clk_enable(sc->clk_mod);
238 	sc->spibus = device_add_child(dev, "spibus", DEVICE_UNIT_ANY);
255 	bus_generic_detach(sc->dev);
257 	if (sc->clk_mod != NULL)
258 		clk_release(sc->clk_mod);
259 	if (sc->clk_ahb)
260 		clk_release(sc->clk_ahb);
261 	if (sc->rst_ahb)
262 		hwreset_assert(sc->rst_ahb);
264 	if (sc->intrhand != NULL)
265 		bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
267 	bus_release_resources(dev, aw_spi_spec, sc->res);
268 	mtx_destroy(&sc->mtx);
326 		cur = sc->mod_freq / (1 << i);
327 		if ((clock - cur) < (clock - best)) {
345 		cur = sc->mod_freq / (2 * i + 1);
346 		if ((clock - cur) < (clock - best)) {
370 		if ((clock - best_ccr1) < (clock - best_ccr2))
385 	if (sc->txcnt == sc->txlen)
392 	for (i = 0; i < (AW_SPI_FIFO_SIZE - txcnt); i++) {
393 		AW_SPI_WRITE_1(sc, AW_SPI_TXD, sc->txbuf[sc->txcnt++]);
394 		if (sc->txcnt == sc->txlen)
408 	if (sc->rxcnt == sc->rxlen)
416 		if (sc->rxcnt < sc->rxlen)
417 			sc->rxbuf[sc->rxcnt++] = val;
441 		if (sc->txcnt == sc->txlen)
452 		sc->transfer = 0;
467 	sc->rxbuf = rxbuf;
468 	sc->rxcnt = 0;
469 	sc->txbuf = txbuf;
470 	sc->txcnt = 0;
471 	sc->txlen = txlen;
472 	sc->rxlen = rxlen;
477 	for (timeout = 1000; timeout > 0; timeout--) {
483 		device_printf(sc->dev, "Cannot reset the FIFOs\n");
488 	 * Set the TX FIFO threshold to 3/4-th the size and
489 	 * the RX FIFO one to 1/4-th.
500 	/* First fill */
517 	sc->transfer = 1;
519 	while (error == 0 && sc->transfer != 0)
520 		error = msleep(sc, &sc->mtx, 0, "aw_spi", 10 * hz);
539 	clk_set_freq(sc->clk_mod, 2 * clock, CLK_SET_ROUND_DOWN);
540 	clk_get_freq(sc->clk_mod, &sc->mod_freq);
546 	mtx_lock(&sc->mtx);
563 	if (cmd->tx_cmd_sz > 0)
564 		err = aw_spi_xfer(sc, cmd->rx_cmd, cmd->tx_cmd,
565 		    cmd->tx_cmd_sz, cmd->rx_cmd_sz);
566 	if (cmd->tx_data_sz > 0 && err == 0)
567 		err = aw_spi_xfer(sc, cmd->rx_data, cmd->tx_data,
568 		    cmd->tx_data_sz, cmd->rx_data_sz);
580 	mtx_unlock(&sc->mtx);