Lines Matching +full:0 +full:xff0000
48 #define AW_SPI_GCR 0x04 /* Global Control Register */
49 #define AW_SPI_GCR_EN (1 << 0) /* ENable */
50 #define AW_SPI_GCR_MODE_MASTER (1 << 1) /* 1 = Master, 0 = Slave */
54 #define AW_SPI_TCR 0x08 /* Transfer Control register */
62 #define AW_SPI_TCR_SSSEL_MASK 0x30 /* Chip select */
68 #define AW_SPI_TCR_CPHA (1 << 0) /* 1 == Phase 1 */
70 #define AW_SPI_IER 0x10 /* Interrupt Control Register */
82 #define AW_SPI_IER_RF_RDY (1 << 0) /* RXFIFO Ready Request */
84 #define AW_SPI_ISR 0x14 /* Interrupt Status Register */
86 #define AW_SPI_FCR 0x18 /* FIFO Control Register */
88 #define AW_SPI_FCR_TX_TRIG_MASK 0xFF0000 /* TX FIFO Trigger level */
91 #define AW_SPI_FCR_RX_TRIG_MASK 0xFF /* RX FIFO Trigger level */
92 #define AW_SPI_FCR_RX_TRIG_SHIFT 0
94 #define AW_SPI_FSR 0x1C /* FIFO Status Register */
96 #define AW_SPI_FSR_TB_CNT_MASK 0x70000000
98 #define AW_SPI_FSR_TF_CNT_MASK 0xFF0000
101 #define AW_SPI_FSR_RB_CNT_MASK 0x7000
103 #define AW_SPI_FSR_RF_CNT_MASK 0xFF
104 #define AW_SPI_FSR_RF_CNT_SHIFT 0
106 #define AW_SPI_WCR 0x20 /* Wait Clock Counter Register */
108 #define AW_SPI_CCR 0x24 /* Clock Rate Control Register */
110 #define AW_SPI_CCR_CDR1_MASK 0xF00
112 #define AW_SPI_CCR_CDR2_MASK 0xFF
113 #define AW_SPI_CCR_CDR2_SHIFT 0
115 #define AW_SPI_MBC 0x30 /* Burst Counter Register */
116 #define AW_SPI_MTC 0x34 /* Transmit Counter Register */
117 #define AW_SPI_BCC 0x38 /* Burst Control Register */
118 #define AW_SPI_MDMA_CTL 0x88 /* Normal DMA Control Register */
119 #define AW_SPI_TXD 0x200 /* TX Data Register */
120 #define AW_SPI_RDX 0x300 /* RX Data Register */
127 { NULL, 0 }
131 { SYS_RES_MEMORY, 0, RF_ACTIVE },
132 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
133 { -1, 0 }
159 #define AW_SPI_READ_1(sc, reg) bus_read_1((sc)->res[0], (reg))
160 #define AW_SPI_WRITE_1(sc, reg, val) bus_write_1((sc)->res[0], (reg), (val))
161 #define AW_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))
162 #define AW_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
193 if (bus_alloc_resources(dev, aw_spi_spec, sc->res) != 0) {
208 if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst_ahb) == 0) {
210 if (error != 0) {
217 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->clk_ahb);
218 if (error != 0) {
222 error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_mod);
223 if (error != 0) {
228 if (error != 0) {
233 if (error != 0) {
241 return (0);
270 return (0);
321 uint64_t cur, best = 0;
325 for (i = 0; i < max; i++) {
340 uint64_t cur, best = 0;
344 for (i = 0; i < max; i++) {
392 for (i = 0; i < (AW_SPI_FIFO_SIZE - txcnt); i++) {
414 for (i = 0; i < reg; i++) {
451 AW_SPI_WRITE_4(sc, AW_SPI_IER, 0);
452 sc->transfer = 0;
458 return (intr != 0 ? FILTER_HANDLED : FILTER_STRAY);
465 int error = 0, timeout;
468 sc->rxcnt = 0;
470 sc->txcnt = 0;
477 for (timeout = 1000; timeout > 0; timeout--) {
479 if (reg == 0)
482 if (timeout == 0) {
519 while (error == 0 && sc->transfer != 0)
520 error = msleep(sc, &sc->mtx, 0, "aw_spi", 10 * hz);
522 return (0);
530 int err = 0;
562 err = 0;
563 if (cmd->tx_cmd_sz > 0)
566 if (cmd->tx_data_sz > 0 && err == 0)
606 DRIVER_MODULE(aw_spi, simplebus, aw_spi_driver, 0, 0);
607 DRIVER_MODULE(ofw_spibus, aw_spi, ofw_spibus_driver, 0, 0);