Lines Matching +full:dsp +full:- +full:config +full:- +full:name
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * Maestro-3/Allegro FreeBSD pcm sound driver
34 * (+) /dev/dsp multiple concurrent play channels.
35 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit).
37 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel
39 * (-) hardware volme controls don't work =-(
40 * (-) setblocksize() does nothing.
50 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference.
51 * <taku@cent.saitama-u.ac.jp>
72 /* -------------------------------------------------------------------- */
74 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1};
80 /* -------------------------------------------------------------------- */
87 u_int32_t pci_id; int which; int delay1; int delay2; char *name;
89 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" },
98 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */
100 #define M3_MAXADDR ((1 << 27) - 1)
162 #define M3_LOCK(_sc) snd_mtxlock((_sc)->sc_lock)
163 #define M3_UNLOCK(_sc) snd_mtxunlock((_sc)->sc_lock)
164 #define M3_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->sc_lock)
166 /* -------------------------------------------------------------------- */
194 /* talk to the codec - called from ac97.c */
210 /* -------------------------------------------------------------------- */
220 /* -------------------------------------------------------------------- */
267 /* -------------------------------------------------------------------- */
270 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno)
271 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno)
272 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno)
273 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data)
274 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data)
275 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data)
313 return -1;
316 /* -------------------------------------------------------------------- */
327 /* init ac-link */
340 device_printf(sc->dev, "m3_rdcd timed out.\n");
341 return -1;
346 device_printf(sc->dev, "m3_rdcd timed out.\n");
347 return -1;
358 device_printf(sc->dev, "m3_wrcd timed out.\n");
359 return -1;
367 /* -------------------------------------------------------------------- */
402 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1},
408 idx = sc->pch_cnt; /* dac instance number, no active reuse! */
413 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n");
422 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
423 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
427 ch = &sc->pch[idx];
428 ch->dac_idx = idx;
429 ch->dac_data = dac_data;
430 if (ch->dac_data + data_bytes/2 >= 0x1c00) {
432 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n");
436 ch->buffer = b;
437 ch->parent = sc;
438 ch->channel = c;
439 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
440 ch->spd = DSP_DEFAULT_SPEED;
442 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
443 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n");
447 ch->bufsize = sndbuf_getsize(ch->buffer);
450 bus_addr = sndbuf_getbufaddr(ch->buffer);
452 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n");
455 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
456 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
457 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L,
458 LO(bus_addr + ch->bufsize));
459 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H,
460 HI(bus_addr + ch->bufsize));
461 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL,
463 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH,
466 /* dsp buffers */
467 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
468 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1,
470 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
471 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
472 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
473 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1,
475 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
476 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
479 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12,
480 ch->dac_data + 40 + 8);
481 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19,
484 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0);
486 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL,
492 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val);
497 (sc->pch_cnt + sc->rch_cnt),
498 ch->dac_data >> DP_SHIFT_COUNT);
499 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
500 ch->dac_data >> DP_SHIFT_COUNT);
501 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt,
502 ch->dac_data >> DP_SHIFT_COUNT);
509 sc->pch_cnt++;
519 struct sc_info *sc = ch->parent;
522 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx));
529 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
531 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
532 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0);
533 sc->pch_cnt--;
543 struct sc_info *sc = ch->parent;
548 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
549 ch->dac_idx, format,
555 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data);
559 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data);
561 ch->fmt = format;
571 struct sc_info *sc = ch->parent;
576 ch->dac_idx, speed));
579 freq--;
582 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq);
583 ch->spd = speed;
596 ch->dac_idx, blocksize));
598 return (sndbuf_getblksz(ch->buffer));
605 struct sc_info *sc = ch->parent;
625 for (i = 0; i < sc->pch_cnt; i++)
626 ret += sc->pch[i].active;
628 for (i = 0; i < sc->rch_cnt; i++)
629 ret += sc->rch[i].active;
638 struct sc_info *sc = ch->parent;
646 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go,
653 if (ch->active) {
656 ch->active = 1;
657 ch->ptr = 0;
658 ch->prevptr = 0;
659 sc->pch_active_cnt++;
669 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1);
671 sc->pch_active_cnt);
676 if (ch->active == 0) {
679 ch->active = 0;
680 sc->pch_active_cnt--;
691 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0);
693 sc->pch_active_cnt);
697 /* got play irq, transfer next buffer - ignore if using dma */
699 /* got rec irq, transfer next buffer - ignore if using dma */
709 struct sc_info *sc = ch->parent;
712 bus_base = sndbuf_getbufaddr(ch->buffer);
713 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH);
714 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL);
718 ch->dac_idx, bus_crnt - bus_base));
720 return (bus_crnt - bus_base); /* current byte offset of channel */
727 struct sc_info *sc = ch->parent;
731 ptr = ch->ptr;
742 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx));
747 /* -------------------------------------------------------------------- */
788 idx = sc->rch_cnt; /* adc instance number, no active reuse! */
793 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n");
802 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
806 ch = &sc->rch[idx];
807 ch->adc_idx = idx;
808 ch->adc_data = adc_data;
809 if (ch->adc_data + data_bytes/2 >= 0x1c00) {
811 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n");
815 ch->buffer = b;
816 ch->parent = sc;
817 ch->channel = c;
818 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
819 ch->spd = DSP_DEFAULT_SPEED;
821 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
822 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n");
826 ch->bufsize = sndbuf_getsize(ch->buffer);
829 bus_addr = sndbuf_getbufaddr(ch->buffer);
831 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n");
834 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
835 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
836 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L,
837 LO(bus_addr + ch->bufsize));
838 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H,
839 HI(bus_addr + ch->bufsize));
840 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL,
842 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH,
845 /* dsp buffers */
846 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
847 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1,
849 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
850 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
851 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
852 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1,
854 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
855 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
858 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12,
859 ch->adc_data + 40 + 8);
860 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL,
866 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val);
871 (sc->pch_cnt + sc->rch_cnt),
872 ch->adc_data >> DP_SHIFT_COUNT);
873 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
874 ch->adc_data >> DP_SHIFT_COUNT);
875 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt,
876 ch->adc_data >> DP_SHIFT_COUNT);
883 sc->rch_cnt++;
893 struct sc_info *sc = ch->parent;
896 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx));
903 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
905 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
906 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0);
907 sc->rch_cnt--;
917 struct sc_info *sc = ch->parent;
922 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
923 ch->adc_idx, format,
929 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data);
933 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data);
934 ch->fmt = format;
944 struct sc_info *sc = ch->parent;
949 ch->adc_idx, speed));
952 freq--;
955 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq);
956 ch->spd = speed;
969 ch->adc_idx, blocksize));
971 return (sndbuf_getblksz(ch->buffer));
978 struct sc_info *sc = ch->parent;
995 struct sc_info *sc = ch->parent;
1003 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go,
1010 if (ch->active) {
1013 ch->active = 1;
1014 ch->ptr = 0;
1015 ch->prevptr = 0;
1026 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1);
1031 if (ch->active == 0) {
1034 ch->active = 0;
1044 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0);
1049 /* got play irq, transfer next buffer - ignore if using dma */
1051 /* got rec irq, transfer next buffer - ignore if using dma */
1061 struct sc_info *sc = ch->parent;
1064 bus_base = sndbuf_getbufaddr(ch->buffer);
1065 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH);
1066 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL);
1070 ch->adc_idx, bus_crnt - bus_base));
1072 return (bus_crnt - bus_base); /* current byte offset of channel */
1079 struct sc_info *sc = ch->parent;
1083 ptr = ch->ptr;
1094 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx));
1099 /* -------------------------------------------------------------------- */
1127 mixer_hwvol_mute(sc->dev);
1130 mixer_hwvol_step(sc->dev, 1, 1);
1133 mixer_hwvol_step(sc->dev, -1, -1);
1138 device_printf(sc->dev, "Unknown HWVOL event\n");
1159 for (i=0 ; i<sc->pch_cnt ; i++) {
1160 pch = &sc->pch[i];
1161 if (pch->active) {
1162 pch->ptr = m3_pchan_getptr_internal(pch);
1163 delta = pch->bufsize + pch->ptr - pch->prevptr;
1164 delta %= pch->bufsize;
1165 if (delta < sndbuf_getblksz(pch->buffer))
1167 pch->prevptr = pch->ptr;
1169 chn_intr(pch->channel);
1173 for (i=0 ; i<sc->rch_cnt ; i++) {
1174 rch = &sc->rch[i];
1175 if (rch->active) {
1176 rch->ptr = m3_rchan_getptr_internal(rch);
1177 delta = rch->bufsize + rch->ptr - rch->prevptr;
1178 delta %= rch->bufsize;
1179 if (delta < sndbuf_getblksz(rch->buffer))
1181 rch->prevptr = rch->ptr;
1183 chn_intr(rch->channel);
1192 /* -------------------------------------------------------------------- */
1203 data = pci_read_config(sc->dev, 0x34, 1);
1204 if (pci_read_config(sc->dev, data, 1) == 1) {
1205 pci_write_config(sc->dev, data + 4, state, 1);
1221 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2);
1223 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2);
1295 /* -------------------------------------------------------------------- */
1305 for (card = m3_card_types ; card->pci_id ; card++) {
1306 if (pci_get_devid(dev) == card->pci_id) {
1307 device_set_desc(dev, card->name);
1326 sc->dev = dev;
1327 sc->type = pci_get_devid(dev);
1328 sc->sc_lock = snd_mtxcreate(device_get_nameunit(dev),
1330 for (card = m3_card_types ; card->pci_id ; card++) {
1331 if (sc->type == card->pci_id) {
1332 sc->which = card->which;
1333 sc->delay1 = card->delay1;
1334 sc->delay2 = card->delay2;
1354 sc->regid = PCIR_BAR(0);
1355 sc->regtype = SYS_RES_MEMORY;
1356 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1358 if (!sc->reg) {
1359 sc->regtype = SYS_RES_IOPORT;
1360 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1363 if (!sc->reg) {
1367 sc->st = rman_get_bustag(sc->reg);
1368 sc->sh = rman_get_bushandle(sc->reg);
1370 sc->irqid = 0;
1371 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1373 if (!sc->irq) {
1378 if (snd_setup_intr(dev, sc->irq, INTR_MPSAFE, m3_intr, sc, &sc->ih)) {
1383 sc->bufsz = pcm_getbuffersize(dev, M3_BUFSIZE_MIN, M3_BUFSIZE_DEFAULT,
1392 sc->bufsz, /* maxsize */
1398 &sc->parent_dmat) != 0) {
1408 if (i == -1) {
1440 (sc->regtype == SYS_RES_IOPORT)? "port" : "mem",
1441 rman_get_start(sc->reg), rman_get_start(sc->irq),
1453 sc->savemem = malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1460 if (sc->ih)
1461 bus_teardown_intr(dev, sc->irq, sc->ih);
1462 if (sc->irq)
1463 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1464 if (sc->reg)
1465 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1466 if (sc->parent_dmat)
1467 bus_dma_tag_destroy(sc->parent_dmat);
1468 if (sc->sc_lock)
1469 snd_mtxfree(sc->sc_lock);
1491 bus_teardown_intr(dev, sc->irq, sc->ih);
1492 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1493 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1494 bus_dma_tag_destroy(sc->parent_dmat);
1496 free(sc->savemem, M_DEVBUF);
1497 snd_mtxfree(sc->sc_lock);
1511 for (i=0 ; i<sc->pch_cnt ; i++) {
1512 if (sc->pch[i].active) {
1513 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1517 for (i=0 ; i<sc->rch_cnt ; i++) {
1518 if (sc->rch[i].active) {
1519 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1533 sc->savemem[index++] = m3_rd_assp_code(sc, i);
1535 sc->savemem[index++] = m3_rd_assp_data(sc, i);
1565 m3_wr_assp_code(sc, i, sc->savemem[index++]);
1567 m3_wr_assp_data(sc, i, sc->savemem[index++]);
1580 if (mixer_reinit(dev) == -1) {
1587 for (i=0 ; i<sc->pch_cnt ; i++) {
1588 if (sc->pch[i].active) {
1589 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1593 for (i=0 ; i<sc->rch_cnt ; i++) {
1594 if (sc->rch[i].active) {
1595 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1649 if (resource_int_value(device_get_name(sc->dev),
1650 device_get_unit(sc->dev),
1657 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1661 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1664 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1666 if (sc->which == ESS_MAESTRO3) {
1671 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1673 if (sc->which == ESS_ALLEGRO_1) {
1674 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4);
1676 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4);
1681 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/
1706 switch (sc->which) {
1714 panic("bad sc->which");
1755 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/
1761 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/
1768 device_printf(sc->dev, "Codec reset failed\n");
1771 device_printf(sc->dev, "Codec reset retry\n");