Lines Matching +full:pcm +full:- +full:clock +full:- +full:mode
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2012-2016 Ruslan Bukin <br@bsdpad.com>
5 * Copyright (c) 2023-2024 Florian Walpen <dev@submerge.ch>
38 #include <dev/sound/pcm/sound.h>
52 &hdsp_unified_pcm, 0, "Combine physical ports in one unified pcm device");
112 snd_mtxlock(sc->lock);
116 if ((err = device_get_children(sc->dev, &devlist, &devcount)) != 0)
121 if (scp->ih != NULL)
122 scp->ih(scp);
129 snd_mtxunlock(sc->lock);
136 device_printf(sc->dev, "hdsp_dmapsetmap()\n");
145 sc->csid = PCIR_BAR(0);
146 sc->cs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
147 &sc->csid, RF_ACTIVE);
149 if (!sc->cs) {
150 device_printf(sc->dev, "Unable to map SYS_RES_MEMORY.\n");
154 sc->cst = rman_get_bustag(sc->cs);
155 sc->csh = rman_get_bushandle(sc->cs);
158 sc->irqid = 0;
159 sc->irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irqid,
162 if (!sc->irq ||
163 bus_setup_intr(sc->dev, sc->irq, INTR_MPSAFE | INTR_TYPE_AV,
164 NULL, hdsp_intr, sc, &sc->ih)) {
165 device_printf(sc->dev, "Unable to alloc interrupt resource.\n");
170 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(sc->dev),
183 /*dmatag*/&sc->dmat) != 0) {
184 device_printf(sc->dev, "Unable to create dma tag.\n");
188 sc->bufsize = HDSP_DMASEGSIZE;
191 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->pbuf, BUS_DMA_WAITOK,
192 &sc->pmap)) {
193 device_printf(sc->dev, "Can't alloc pbuf.\n");
197 if (bus_dmamap_load(sc->dmat, sc->pmap, sc->pbuf, sc->bufsize,
199 device_printf(sc->dev, "Can't load pbuf.\n");
204 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->rbuf, BUS_DMA_WAITOK,
205 &sc->rmap)) {
206 device_printf(sc->dev, "Can't alloc rbuf.\n");
210 if (bus_dmamap_load(sc->dmat, sc->rmap, sc->rbuf, sc->bufsize,
212 device_printf(sc->dev, "Can't load rbuf.\n");
216 bzero(sc->pbuf, sc->bufsize);
217 bzero(sc->rbuf, sc->bufsize);
227 paddr = vtophys(sc->pbuf);
228 raddr = vtophys(sc->rbuf);
243 return ("-10dBV");
258 sc = oidp->oid_arg1;
261 if (sc->type != HDSP_9632)
265 control = sc->ctrl_register & HDSP_INPUT_LEVEL_MASK;
272 if (error != 0 || req->newptr == NULL)
288 if (control != (sc->ctrl_register & HDSP_INPUT_LEVEL_MASK)) {
289 snd_mtxlock(sc->lock);
290 sc->ctrl_register &= ~HDSP_INPUT_LEVEL_MASK;
291 sc->ctrl_register |= control;
292 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register);
293 snd_mtxunlock(sc->lock);
303 return ("-10dBV");
322 sc = oidp->oid_arg1;
325 if (sc->type != HDSP_9632)
329 control = sc->ctrl_register & HDSP_OUTPUT_LEVEL_MASK;
336 if (error != 0 || req->newptr == NULL)
352 if (control != (sc->ctrl_register & HDSP_OUTPUT_LEVEL_MASK)) {
353 snd_mtxlock(sc->lock);
354 sc->ctrl_register &= ~HDSP_OUTPUT_LEVEL_MASK;
355 sc->ctrl_register |= control;
356 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register);
357 snd_mtxunlock(sc->lock);
367 return ("-12dB");
369 return ("-6dB");
386 sc = oidp->oid_arg1;
389 if (sc->type != HDSP_9632)
393 control = sc->ctrl_register & HDSP_PHONES_LEVEL_MASK;
400 if (error != 0 || req->newptr == NULL)
416 if (control != (sc->ctrl_register & HDSP_PHONES_LEVEL_MASK)) {
417 snd_mtxlock(sc->lock);
418 sc->ctrl_register &= ~HDSP_PHONES_LEVEL_MASK;
419 sc->ctrl_register |= control;
420 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register);
421 snd_mtxunlock(sc->lock);
429 struct sc_info *sc = oidp->oid_arg1;
433 speed = sc->force_speed;
437 if (error != 0 || req->newptr == NULL)
440 /* Speed from 32000 to 192000, 0 falls back to pcm speed setting. */
441 sc->force_speed = 0;
444 if ((speed > (96000 + 128000) / 2) && sc->type == HDSP_9632)
450 sc->force_speed = 32000 * multiplier;
452 sc->force_speed = 44100 * multiplier;
454 sc->force_speed = 48000 * multiplier;
464 struct sc_info *sc = oidp->oid_arg1;
468 period = sc->force_period;
472 if (error != 0 || req->newptr == NULL)
475 /* Period is from 2^5 to 2^14, 0 falls back to pcm latency settings. */
476 sc->force_period = 0;
478 sc->force_period = 32;
479 while (sc->force_period < period && sc->force_period < 4096)
480 sc->force_period <<= 1;
513 struct hdsp_clock_source *clock_table, *clock;
518 sc = oidp->oid_arg1;
521 if (sc->type == HDSP_9632)
523 else if (sc->type == HDSP_9652)
528 /* Extract preferred clock source from control register. */
529 control = sc->ctrl_register & HDSP_CONTROL_CLOCK_MASK;
530 for (clock = clock_table; clock->name != NULL; ++clock) {
531 if (hdsp_control_clock_preference(clock->type) == control)
534 if (clock->name != NULL)
535 strlcpy(buf, clock->name, sizeof(buf));
539 if (error != 0 || req->newptr == NULL)
542 /* Find clock source matching the sysctl string. */
543 for (clock = clock_table; clock->name != NULL; ++clock) {
544 if (strncasecmp(buf, clock->name, sizeof(buf)) == 0)
548 /* Set preferred clock source in control register. */
549 if (clock->name != NULL) {
550 control = hdsp_control_clock_preference(clock->type);
552 snd_mtxlock(sc->lock);
553 sc->ctrl_register &= ~HDSP_CONTROL_CLOCK_MASK;
554 sc->ctrl_register |= control;
555 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register);
556 snd_mtxunlock(sc->lock);
588 struct hdsp_clock_source *clock_table, *clock;
592 sc = oidp->oid_arg1;
595 if (sc->type == HDSP_9632)
597 else if (sc->type == HDSP_9652)
602 /* Read current (autosync) clock source from status2 register. */
603 snd_mtxlock(sc->lock);
606 snd_mtxunlock(sc->lock);
608 /* Translate status2 register value to clock source. */
609 for (clock = clock_table; clock->name != NULL; ++clock) {
610 /* In clock master mode, override with internal clock source. */
611 if (sc->ctrl_register & HDSP_CONTROL_MASTER) {
612 if (clock->type == HDSP_CLOCK_INTERNAL)
614 } else if (hdsp_status2_clock_source(clock->type) == status2)
619 if (clock->name != NULL)
620 strlcpy(buf, clock->name, sizeof(buf));
628 struct hdsp_clock_source *clock_table, *clock;
632 sc = oidp->oid_arg1;
635 /* Select clock source table for device type. */
636 if (sc->type == HDSP_9632)
638 else if (sc->type == HDSP_9652)
643 /* List available clock sources. */
645 for (clock = clock_table; clock->name != NULL; ++clock) {
647 n += strlcpy(buf + n, ",", sizeof(buf) - n);
648 n += strlcpy(buf + n, clock->name, sizeof(buf) - n);
705 struct hdsp_clock_source *clock_table, *clock;
711 sc = oidp->oid_arg1;
715 if (sc->type == HDSP_9632)
717 else if (sc->type == HDSP_9652)
723 snd_mtxlock(sc->lock);
726 snd_mtxunlock(sc->lock);
728 /* List clock sources with lock and sync state. */
729 for (clock = clock_table; clock->name != NULL; ++clock) {
730 if (clock->type == HDSP_CLOCK_INTERNAL)
733 n += strlcpy(buf + n, ",", sizeof(buf) - n);
735 if (hdsp_clock_source_locked(clock->type, status, status2)) {
736 if (hdsp_clock_source_synced(clock->type, status,
742 n += snprintf(buf + n, sizeof(buf) - n, "%s(%s)",
743 clock->name, state);
775 sc->period = 256;
777 * The pcm channel latency settings propagate unreliable blocksizes,
782 sc->force_period = 256;
783 sc->ctrl_register = hdsp_encode_latency(2);
786 sc->speed = HDSP_SPEED_DEFAULT;
787 sc->force_speed = 0;
788 sc->ctrl_register &= ~HDSP_FREQ_MASK;
789 sc->ctrl_register |= HDSP_FREQ_MASK_DEFAULT;
791 /* Set internal clock source (master). */
792 sc->ctrl_register &= ~HDSP_CONTROL_CLOCK_MASK;
793 sc->ctrl_register |= HDSP_CONTROL_MASTER;
796 sc->ctrl_register &= ~HDSP_CONTROL_SPDIF_COAX;
797 sc->ctrl_register |= HDSP_CONTROL_SPDIF_COAX;
798 sc->ctrl_register &= ~HDSP_CONTROL_LINE_OUT;
799 sc->ctrl_register |= HDSP_CONTROL_LINE_OUT;
802 sc->ctrl_register &= ~HDSP_INPUT_LEVEL_MASK;
803 sc->ctrl_register |= HDSP_INPUT_LEVEL_LOWGAIN;
804 sc->ctrl_register &= ~HDSP_OUTPUT_LEVEL_MASK;
805 sc->ctrl_register |= HDSP_OUTPUT_LEVEL_MINUS10DBV;
806 sc->ctrl_register &= ~HDSP_PHONES_LEVEL_MASK;
807 sc->ctrl_register |= HDSP_PHONES_LEVEL_MINUS12DB;
809 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register);
811 if (sc->type == HDSP_9652)
816 switch (sc->type) {
838 if (sc->type == HDSP_9632) {
840 hdsp_write_4(sc, HDSP_FREQ_REG, hdsp_freq_reg_value(sc->speed));
860 sc->lock = snd_mtxcreate(device_get_nameunit(dev),
862 sc->dev = dev;
868 sc->type = HDSP_9632;
872 sc->type = HDSP_9652;
891 scp->hc = &chan_map[i];
892 scp->sc = sc;
893 scp->dev = device_add_child(dev, "pcm", -1);
894 device_set_ivars(scp->dev, scp);
903 "List clock source signal lock and sync status");
909 "Currently effective clock source");
915 "Set 'internal' (master) or preferred autosync clock source");
921 "List of supported clock sources");
935 if (sc->type == HDSP_9632) {
940 "Phones output level ('0dB', '-6dB', '-12dB')");
946 "Analog output level ('HighGain', '+4dBU', '-10dBV')");
952 "Analog input level ('LowGain', '+4dBU', '-10dBV')");
969 bus_dmamap_unload(sc->dmat, sc->rmap);
970 bus_dmamap_unload(sc->dmat, sc->pmap);
971 bus_dmamem_free(sc->dmat, sc->rbuf, sc->rmap);
972 bus_dmamem_free(sc->dmat, sc->pbuf, sc->pmap);
973 sc->rbuf = sc->pbuf = NULL;
994 if (sc->ih)
995 bus_teardown_intr(dev, sc->irq, sc->ih);
996 if (sc->dmat)
997 bus_dma_tag_destroy(sc->dmat);
998 if (sc->irq)
999 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
1000 if (sc->cs)
1001 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->cs);
1002 if (sc->lock)
1003 snd_mtxfree(sc->lock);