Lines Matching +full:sdi +full:- +full:enabled
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
54 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
55 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
56 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
80 { HDA_INTEL_CMLKLP, "Intel Comet Lake-LP", 0, 0 },
81 { HDA_INTEL_CMLKH, "Intel Comet Lake-H", 0, 0 },
88 { HDA_INTEL_BXTNT, "Intel Broxton-T", 0, 0 },
98 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 },
99 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 },
100 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 },
101 { HDA_INTEL_KBLKLP, "Intel Kaby Lake-LP", 0, 0 },
104 { HDA_INTEL_KBLKH, "Intel Kaby Lake-H", 0, 0 },
106 { HDA_INTEL_CMLKS, "Intel Comet Lake-S", 0, 0 },
110 { HDA_INTEL_TGLKH, "Intel Tiger Lake-H", 0, 0 },
113 { HDA_INTEL_ALLKM, "Intel Alder Lake-M", 0, 0 },
114 { HDA_INTEL_ALLKN, "Intel Alder Lake-N", 0, 0 },
115 { HDA_INTEL_ALLKP1, "Intel Alder Lake-P", 0, 0 },
116 { HDA_INTEL_ALLKP2, "Intel Alder Lake-P", 0, 0 },
117 { HDA_INTEL_ALLKPS, "Intel Alder Lake-PS", 0, 0 },
118 { HDA_INTEL_RPTLK1, "Intel Raptor Lake-P", 0, 0 },
119 { HDA_INTEL_RPTLK2, "Intel Raptor Lake-P", 0, 0 },
120 { HDA_INTEL_MTL, "Intel Meteor Lake-P", 0, 0 },
121 { HDA_INTEL_ARLS, "Intel Arrow Lake-S", 0, 0 },
123 { HDA_INTEL_LNLP, "Intel Lunar Lake-P", 0, 0 },
136 { HDA_INTEL_BXTNP, "Intel Broxton-P", 0, 0 },
202 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 },
272 if (resource_string_value(device_get_name(sc->dev),
273 device_get_unit(sc->dev), "config", &res) != 0)
278 device_printf(sc->dev, "Config options:");
294 len = j - i;
301 hdac_quirks_tab[k].key, len - inv) != 0)
303 if (len - inv != strlen(hdac_quirks_tab[k].key))
335 * a reset or a wake-up event.
351 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
353 HDAC_WRITE_1(&sc->mem,
356 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
358 if (sc->unsolq_rp != sc->unsolq_wp)
359 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
363 for (i = 0; i < sc->num_ss; i++) {
366 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
368 if ((dev = sc->streams[i].dev) != NULL) {
370 sc->streams[i].dir, sc->streams[i].stream);
392 * from zero to one. GIS is formed by OR-ing multiple hardware
396 * re-examine GIS then we can leave it set and never get an interrupt
400 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
403 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
417 if (sc->polling == 0) {
421 callout_reset(&sc->poll_callout, sc->poll_ival, hdac_poll_callback, sc);
441 for (i = 0; i < sc->num_iss; i++)
442 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
443 for (i = 0; i < sc->num_oss; i++)
444 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
445 for (i = 0; i < sc->num_bss; i++)
446 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
451 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
452 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
457 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
458 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
464 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
465 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
468 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
472 } while (--count);
474 device_printf(sc->dev, "Unable to put hdac in reset\n");
478 /* If wakeup is not requested - leave the controller in reset state. */
483 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
484 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
487 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
491 } while (--count);
493 device_printf(sc->dev, "Device stuck in reset\n");
522 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
523 sc->num_iss = HDAC_GCAP_ISS(gcap);
524 sc->num_oss = HDAC_GCAP_OSS(gcap);
525 sc->num_bss = HDAC_GCAP_BSS(gcap);
526 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss;
527 sc->num_sdo = HDAC_GCAP_NSDO(gcap);
528 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0;
529 if (sc->quirks_on & HDAC_QUIRK_64BIT)
530 sc->support_64bit = 1;
531 else if (sc->quirks_off & HDAC_QUIRK_64BIT)
532 sc->support_64bit = 0;
534 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
537 sc->corb_size = 256;
540 sc->corb_size = 16;
543 sc->corb_size = 2;
545 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
550 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
553 sc->rirb_size = 256;
556 sc->rirb_size = 16;
559 sc->rirb_size = 2;
561 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
567 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
569 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
570 sc->support_64bit ? ", 64bit" : "",
571 sc->corb_size, sc->rirb_size);
591 dma->dma_paddr = segs[0].ds_addr;
614 bus_get_dma_tag(sc->dev), /* parent */
617 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
628 &dma->dma_tag); /* dmat */
630 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%d)\n",
638 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
640 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE :
642 &dma->dma_map);
644 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%d)\n",
649 dma->dma_size = roundsz;
654 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
655 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
656 if (result != 0 || dma->dma_paddr == 0) {
659 device_printf(sc->dev, "%s: bus_dmamem_load failed (%d)\n",
665 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
686 if (dma->dma_paddr != 0) {
688 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
690 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
691 dma->dma_paddr = 0;
693 if (dma->dma_vaddr != NULL) {
694 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
695 dma->dma_vaddr = NULL;
697 if (dma->dma_tag != NULL) {
698 bus_dma_tag_destroy(dma->dma_tag);
699 dma->dma_tag = NULL;
701 dma->dma_size = 0;
715 mem = &sc->mem;
716 mem->mem_rid = PCIR_BAR(0);
717 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
718 &mem->mem_rid, RF_ACTIVE);
719 if (mem->mem_res == NULL) {
720 device_printf(sc->dev,
724 mem->mem_tag = rman_get_bustag(mem->mem_res);
725 mem->mem_handle = rman_get_bushandle(mem->mem_res);
740 mem = &sc->mem;
741 if (mem->mem_res != NULL)
742 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
743 mem->mem_res);
744 mem->mem_res = NULL;
758 irq = &sc->irq;
759 irq->irq_rid = 0x0;
761 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 &&
762 (result = pci_msi_count(sc->dev)) == 1 &&
763 pci_alloc_msi(sc->dev, &result) == 0)
764 irq->irq_rid = 0x1;
766 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
767 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
768 if (irq->irq_res == NULL) {
769 device_printf(sc->dev, "%s: Unable to allocate irq\n",
773 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
774 NULL, hdac_intr_handler, sc, &irq->irq_handle);
776 device_printf(sc->dev,
800 irq = &sc->irq;
801 if (irq->irq_res != NULL && irq->irq_handle != NULL)
802 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
803 if (irq->irq_res != NULL)
804 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
805 irq->irq_res);
806 if (irq->irq_rid == 0x1)
807 pci_release_msi(sc->dev);
808 irq->irq_handle = NULL;
809 irq->irq_res = NULL;
810 irq->irq_rid = 0x0;
826 switch (sc->corb_size) {
837 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
839 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
842 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
843 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
844 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
847 sc->corb_wp = 0;
848 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
849 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
856 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
860 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
877 switch (sc->rirb_size) {
888 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
890 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
893 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
894 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
895 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
898 sc->rirb_rp = 0;
899 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
902 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
906 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
909 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
916 * read-only from now on.
918 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
932 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
934 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
947 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
949 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
961 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
962 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
963 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
967 while (sc->rirb_rp != rirbwp) {
968 sc->rirb_rp++;
969 sc->rirb_rp %= sc->rirb_size;
970 rirb = &rirb_base[sc->rirb_rp];
971 resp = le32toh(rirb->response);
972 resp_ex = le32toh(rirb->response_ex);
975 sc->unsolq[sc->unsolq_wp++] = resp;
976 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
977 sc->unsolq[sc->unsolq_wp++] = cad;
978 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
979 } else if (sc->codecs[cad].pending <= 0) {
980 device_printf(sc->dev, "Unexpected unsolicited "
983 sc->codecs[cad].response = resp;
984 sc->codecs[cad].pending--;
989 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1002 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
1003 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
1004 while (sc->unsolq_rp != sc->unsolq_wp) {
1005 resp = sc->unsolq[sc->unsolq_rp++];
1006 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
1007 cad = sc->unsolq[sc->unsolq_rp++];
1008 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
1009 if ((child = sc->codecs[cad].dev) != NULL &&
1014 sc->unsolq_st = HDAC_UNSOLQ_READY;
1034 sc->codecs[cad].response = HDA_INVALID;
1036 sc->codecs[cad].pending++;
1037 sc->corb_wp++;
1038 sc->corb_wp %= sc->corb_size;
1039 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
1040 bus_dmamap_sync(sc->corb_dma.dma_tag,
1041 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
1042 corb[sc->corb_wp] = htole32(verb);
1043 bus_dmamap_sync(sc->corb_dma.dma_tag,
1044 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
1045 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1051 } while (sc->codecs[cad].pending != 0 && --timeout);
1053 if (sc->codecs[cad].pending != 0) {
1054 device_printf(sc->dev, "Command 0x%08x timeout on address %d\n",
1056 sc->codecs[cad].pending = 0;
1059 if (sc->unsolq_rp != sc->unsolq_wp)
1060 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
1061 return (sc->codecs[cad].response);
1130 * Attach the device into the kernel. Interrupts usually won't be enabled
1132 * interrupts and defer probing of codecs until interrupts are enabled.
1139 int i, devid = -1;
1171 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex");
1172 sc->dev = dev;
1173 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
1174 callout_init(&sc->poll_callout, 1);
1176 sc->codecs[i].dev = NULL;
1178 sc->quirks_on = hdac_devices[devid].quirks_on;
1179 sc->quirks_off = hdac_devices[devid].quirks_off;
1181 sc->quirks_on = 0;
1182 sc->quirks_off = 0;
1187 sc->quirks_off |= HDAC_QUIRK_MSI;
1189 sc->quirks_on |= HDAC_QUIRK_MSI;
1190 sc->quirks_off |= ~HDAC_QUIRK_MSI;
1193 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off);
1195 device_printf(sc->dev,
1197 sc->quirks_on, sc->quirks_off);
1199 sc->poll_ival = hz;
1202 sc->polling = 1;
1204 sc->polling = 0;
1210 /* TCSEL -> TC0 */
1214 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
1220 sc->flags |= HDAC_F_DMA_NOCACHE;
1225 sc->flags &= ~HDAC_F_DMA_NOCACHE;
1235 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
1240 sc->flags &= ~HDAC_F_DMA_NOCACHE;
1259 sc->flags |= HDAC_F_DMA_NOCACHE;
1270 (sc->flags & HDAC_F_DMA_NOCACHE) ?
1285 result = hdac_dma_alloc(sc, &sc->corb_dma,
1286 sc->corb_size * sizeof(uint32_t));
1289 result = hdac_dma_alloc(sc, &sc->rirb_dma,
1290 sc->rirb_size * sizeof(struct hdac_rirb));
1293 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss,
1295 for (i = 0; i < sc->num_ss; i++) {
1296 result = hdac_dma_alloc(sc, &sc->streams[i].bdl,
1301 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) {
1302 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) {
1306 "(non-fatal)\n");
1309 uint64_t addr = sc->pos_dma.dma_paddr;
1311 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32);
1312 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
1319 bus_get_dma_tag(sc->dev), /* parent */
1322 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1333 &sc->chan_dmat); /* dmat */
1354 /* Defer remaining of initialization until interrupts are enabled */
1355 sc->intrhook.ich_func = hdac_attach2;
1356 sc->intrhook.ich_arg = (void *)sc;
1357 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
1358 sc->intrhook.ich_func = NULL;
1366 if (sc->streams != NULL)
1367 for (i = 0; i < sc->num_ss; i++)
1368 hdac_dma_free(sc, &sc->streams[i].bdl);
1369 free(sc->streams, M_HDAC);
1370 hdac_dma_free(sc, &sc->rirb_dma);
1371 hdac_dma_free(sc, &sc->corb_dma);
1373 snd_mtxfree(sc->lock);
1386 dev = oidp->oid_arg1;
1392 if (err != 0 || req->newptr == NULL || val == 0)
1460 if (sc->polling == 0)
1462 if (sc->unsol_registered > 0)
1464 for (i = 0; i < sc->num_ss; i++) {
1465 s = &sc->streams[i];
1466 if (s->running == 0)
1468 pollticks = ((uint64_t)hz * s->blksz) /
1469 (hdac_mdata_rate(s->format) / 8);
1478 sc->poll_ival = min;
1480 callout_stop(&sc->poll_callout);
1482 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc);
1493 dev = oidp->oid_arg1;
1498 val = sc->polling;
1502 if (err != 0 || req->newptr == NULL)
1508 if (val != sc->polling) {
1510 callout_stop(&sc->poll_callout);
1512 callout_drain(&sc->poll_callout);
1514 sc->polling = 0;
1515 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1517 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1519 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1521 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1522 sc->polling = 1;
1545 if (sc->intrhook.ich_func != NULL) {
1546 config_intrhook_disestablish(&sc->intrhook);
1547 sc->intrhook.ich_func = NULL;
1551 device_printf(sc->dev, "Starting CORB Engine...\n");
1555 device_printf(sc->dev, "Starting RIRB Engine...\n");
1560 * Clear HDAC_WAKEEN as at present we have no use for SDI wake
1564 * NB: this needs to be done before the interrupt is enabled as
1567 HDAC_WRITE_2(&sc->mem, HDAC_WAKEEN, 0);
1570 * Read and clear post-reset SDI wake status.
1573 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1574 HDAC_WRITE_2(&sc->mem, HDAC_STATESTS, statests);
1577 device_printf(sc->dev,
1580 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1582 if (sc->polling == 0) {
1583 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
1589 device_printf(sc->dev, "Scanning HDA codecs ...\n");
1595 device_printf(sc->dev,
1606 device_printf(sc->dev,
1610 sc->codecs[i].vendor_id =
1612 sc->codecs[i].device_id =
1614 sc->codecs[i].revision_id =
1616 sc->codecs[i].stepping_id =
1618 child = device_add_child(sc->dev, "hdacc", DEVICE_UNIT_ANY);
1620 device_printf(sc->dev,
1625 sc->codecs[i].dev = child;
1628 bus_attach_children(sc->dev);
1630 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1631 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1632 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
1633 sizeof(sc->dev), sysctl_hdac_pindump, "I", "Dump pin states/data");
1634 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1635 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1636 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
1637 sizeof(sc->dev), sysctl_hdac_polling, "I", "Enable polling mode");
1659 callout_stop(&sc->poll_callout);
1662 callout_drain(&sc->poll_callout);
1663 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1706 * Clear HDAC_WAKEEN as at present we have no use for SDI wake
1711 * NB: this needs to be done before the interrupt is enabled as
1714 HDAC_WRITE_2(&sc->mem, HDAC_WAKEEN, 0);
1715 HDAC_WRITE_2(&sc->mem, HDAC_STATESTS, HDAC_STATESTS_SDIWAKE_MASK);
1720 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1722 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1752 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1755 for (i = 0; i < sc->num_ss; i++)
1756 hdac_dma_free(sc, &sc->streams[i].bdl);
1757 free(sc->streams, M_HDAC);
1758 hdac_dma_free(sc, &sc->pos_dma);
1759 hdac_dma_free(sc, &sc->rirb_dma);
1760 hdac_dma_free(sc, &sc->corb_dma);
1761 if (sc->chan_dmat != NULL) {
1762 bus_dma_tag_destroy(sc->chan_dmat);
1763 sc->chan_dmat = NULL;
1766 snd_mtxfree(sc->lock);
1775 return (sc->chan_dmat);
1806 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id,
1807 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id);
1822 *result = sc->codecs[cad].vendor_id;
1825 *result = sc->codecs[cad].device_id;
1828 *result = sc->codecs[cad].revision_id;
1831 *result = sc->codecs[cad].stepping_id;
1840 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0;
1843 *result = (1 << (1 << sc->num_sdo)) - 1;
1856 return (sc->lock);
1872 ss = -1;
1875 for (i = 0; i < sc->num_iss; i++) {
1876 if (sc->streams[i].stream == stream) {
1882 for (i = 0; i < sc->num_oss; i++) {
1883 if (sc->streams[i + sc->num_iss].stream == stream) {
1884 ss = i + sc->num_iss;
1890 if (ss == -1) {
1891 for (i = 0; i < sc->num_bss; i++) {
1892 if (sc->streams[i + sc->num_iss + sc->num_oss].stream
1894 ss = i + sc->num_iss + sc->num_oss;
1920 bw *= 1 << (sc->num_sdo - stripe);
1921 prevbw = sc->sdo_bw_used;
1922 maxbw = 48000 * 960 * (1 << sc->num_sdo);
1924 prevbw = sc->codecs[cad].sdi_bw_used;
1930 bw + prevbw > maxbw ? " -- OVERFLOW!" : "");
1935 sc->sdo_bw_used += bw;
1937 sc->codecs[cad].sdi_bw_used += bw;
1940 if (ss >= sc->num_iss + sc->num_oss)
1941 stream = 15 - (ss - sc->num_iss - sc->num_oss);
1942 else if (ss >= sc->num_iss)
1943 stream = ss - sc->num_iss + 1;
1947 sc->streams[ss].dev = child;
1948 sc->streams[ss].dir = dir;
1949 sc->streams[ss].stream = stream;
1950 sc->streams[ss].bw = bw;
1951 sc->streams[ss].format = format;
1952 sc->streams[ss].stripe = stripe;
1954 if (sc->pos_dma.dma_vaddr != NULL)
1955 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8);
1973 sc->sdo_bw_used -= sc->streams[ss].bw;
1975 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw;
1976 sc->streams[ss].stream = 0;
1977 sc->streams[ss].dev = NULL;
1995 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr;
1997 bdle->addrl = htole32((uint32_t)addr);
1998 bdle->addrh = htole32((uint32_t)(addr >> 32));
1999 bdle->len = htole32(blksz);
2000 bdle->ioc = htole32(1);
2004 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag,
2005 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_PREWRITE);
2008 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt);
2009 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1);
2010 addr = sc->streams[ss].bdl.dma_paddr;
2011 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr);
2012 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
2014 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2);
2022 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT;
2023 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl);
2025 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format);
2027 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2029 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2031 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS,
2033 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2036 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2038 sc->streams[ss].blksz = blksz;
2039 sc->streams[ss].running = 1;
2055 bus_dmamap_sync(sc->streams[ss].bdl.dma_tag,
2056 sc->streams[ss].bdl.dma_map, BUS_DMASYNC_POSTWRITE);
2059 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2062 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2064 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2066 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2068 sc->streams[ss].running = 0;
2086 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2088 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2090 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2094 } while (--to);
2098 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2101 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2105 } while (--to);
2121 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB));
2129 sc->unsol_registered++;
2139 sc->unsol_registered--;