Lines Matching +full:system +full:- +full:clock +full:- +full:direction +full:- +full:out
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
29 /* -------------------------------------------------------------------- */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
60 #define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */
63 #define PCIR_SCFG 0x60 /* System Configuration Register */
64 #define PCIM_SCFG_XIN2 0xc0 /* XIN2 Clock Source Configuration */
67 /* 10: from external clock synthesizer chip */
68 #define PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */
71 #define PCIM_SCFG_ADC 0x0c /* 1-4 stereo ADC connected */
72 #define PCIM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
74 #define PCIR_ACL 0x61 /* AC-Link Configuration Register */
75 #define PCIM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */
92 #define PCIM_SPDIF_OUT 0x01 /* S/PDIF Stereo Out is present */
100 #define ENVY24_CCS_CTL_DMAINT 0x40 /* DS DMA Channel-C interrupt */
102 #define ENVY24_CCS_CTL_EDGE 0x08 /* SERR# edge (only one PCI clock width) */
110 #define ENVY24_CCS_IMASK_PMT 0x10 /* Professional Multi-track */
120 #define ENVY24_CCS_ISTAT_PMT 0x10 /* Professional Multi-track */
230 #define ENVY24_CCI_GPIOCTL 0x22 /* GPIO Direction Control Register */
235 #define ENVY24_CCI_CPDWN_XTAL 0x80 /* Crystal clock generation power down for XTAL_1 */
237 #define ENVY24_CCI_CPDWN_I2C 0x10 /* I2C port clock */
238 #define ENVY24_CCI_CPDWN_MIDI 0x08 /* MIDI clock */
239 #define ENVY24_CCI_CPDWN_AC97 0x04 /* AC'97 clock */
240 #define ENVY24_CCI_CPDWN_DS 0x02 /* DS Block clock */
241 #define ENVY24_CCI_CPDWN_PCI 0x01 /* PCI clock for SB, DMA controller */
243 #define ENVY24_CCI_MTPDWN 0x31 /* Multi-Track Section Power Down Register */
244 #define ENVY24_CCI_MTPDWN_XTAL 0x80 /* Crystal clock generation power down for XTAL_2 */
245 #define ENVY24_CCI_MTPDWN_SPDIF 0x04 /* S/PDIF clock */
246 #define ENVY24_CCI_MTPDWN_MIX 0x02 /* Professional digital mixer clock */
247 #define ENVY24_CCI_MTPDWN_I2S 0x01 /* Multi-track I2S serial interface clock */
251 #define ENVY24_DDMA_ADDR0 0x00 /* DMA Base and Current Address bit 0-7 */
252 #define ENVY24_DDMA_ADDR8 0x01 /* DMA Base and Current Address bit 8-15 */
253 #define ENVY24_DDMA_ADDR16 0x02 /* DMA Base and Current Address bit 16-23 */
254 #define ENVY24_DDMA_ADDR24 0x03 /* DMA Base and Current Address bit 24-31 */
255 #define ENVY24_DDMA_CNT0 0x04 /* DMA Base and Current Count 0-7 */
256 #define ENVY24_DDMA_CNT8 0x05 /* DMA Base and Current Count 8-15 */
284 #define ENVY24_CS_CTL_U8 0x04 /* 8-bit unsigned(or 16-bit signed) */
291 /* Professional Multi-Track Control Registers */
294 #define ENVY24_MT_INT_RMASK 0x80 /* Multi-track record interrupt mask */
295 #define ENVY24_MT_INT_PMASK 0x40 /* Multi-track playback interrupt mask */
296 #define ENVY24_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */
297 #define ENVY24_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */
300 #define ENVY24_MT_RATE_SPDIF 0x10 /* S/PDIF input clock as the master */
329 #define ENVY24_MT_AC97CMD_ID 0x03 /* ID(0-3) for external AC 97 registers */
364 /* -------------------------------------------------------------------- */
369 able to use for this. If system has consumer AC'97 output, AC'97 line is
391 #define ENVY24_VOL_MIN 96 /* -144db(negate) */
394 /* -------------------------------------------------------------------- */
398 ENVY24 has input->output data routing matrix switch. But original ENVY24
406 (NOTICE: this class is able to set only DAC-1 and S/PDIF output)
437 /* -------------------------------------------------------------------- */
462 /* GPIO connect map of M-Audio Delta series */
472 /* M-Audio Delta series S/PDIF(CS84[01]4) control pin values */
478 /* M-Audio Delta series parameter */