Lines Matching defs:sc
83 #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx)
84 #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx)
85 #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED)
147 smc_select_bank(struct smc_softc *sc, uint16_t bank)
150 bus_barrier(sc->smc_reg, BSR, 2,
152 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK);
153 bus_barrier(sc->smc_reg, BSR, 2,
159 smc_mmu_wait(struct smc_softc *sc)
162 KASSERT((bus_read_2(sc->smc_reg, BSR) &
164 device_get_nameunit(sc->smc_dev)));
165 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY)
170 smc_read_1(struct smc_softc *sc, bus_size_t offset)
173 return (bus_read_1(sc->smc_reg, offset));
177 smc_write_1(struct smc_softc *sc, bus_size_t offset, uint8_t val)
180 bus_write_1(sc->smc_reg, offset, val);
184 smc_read_2(struct smc_softc *sc, bus_size_t offset)
187 return (bus_read_2(sc->smc_reg, offset));
191 smc_write_2(struct smc_softc *sc, bus_size_t offset, uint16_t val)
194 bus_write_2(sc->smc_reg, offset, val);
198 smc_read_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
202 bus_read_multi_2(sc->smc_reg, offset, datap, count);
206 smc_write_multi_2(struct smc_softc *sc, bus_size_t offset, uint16_t *datap,
210 bus_write_multi_2(sc->smc_reg, offset, datap, count);
214 smc_barrier(struct smc_softc *sc, bus_size_t offset, bus_size_t length,
218 bus_barrier(sc->smc_reg, offset, length, flags);
226 struct smc_softc *sc;
229 sc = device_get_softc(dev);
234 if (sc->smc_usemem)
307 struct smc_softc *sc;
310 sc = device_get_softc(dev);
313 sc->smc_dev = dev;
315 ifp = sc->smc_ifp = if_alloc(IFT_ETHER);
317 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
320 callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0);
323 if (sc->smc_usemem)
326 sc->smc_reg_rid = 0;
327 sc->smc_reg = bus_alloc_resource_anywhere(dev, type, &sc->smc_reg_rid,
329 if (sc->smc_reg == NULL) {
334 sc->smc_irq = bus_alloc_resource_anywhere(dev, SYS_RES_IRQ,
335 &sc->smc_irq_rid, 1, RF_ACTIVE | RF_SHAREABLE);
336 if (sc->smc_irq == NULL) {
341 SMC_LOCK(sc);
342 smc_reset(sc);
343 SMC_UNLOCK(sc);
345 smc_select_bank(sc, 3);
346 val = smc_read_2(sc, REV);
347 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
348 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
350 device_printf(dev, "revision %x\n", sc->smc_rev);
352 callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx,
354 if (sc->smc_chip >= REV_CHIP_91110FD) {
355 (void)mii_attach(dev, &sc->smc_miibus, ifp,
358 if (sc->smc_miibus != NULL) {
359 sc->smc_mii_tick = smc_mii_tick;
360 sc->smc_mii_mediachg = smc_mii_mediachg;
361 sc->smc_mii_mediaioctl = smc_mii_mediaioctl;
365 smc_select_bank(sc, 1);
366 eaddr[0] = smc_read_1(sc, IAR0);
367 eaddr[1] = smc_read_1(sc, IAR1);
368 eaddr[2] = smc_read_1(sc, IAR2);
369 eaddr[3] = smc_read_1(sc, IAR3);
370 eaddr[4] = smc_read_1(sc, IAR4);
371 eaddr[5] = smc_read_1(sc, IAR5);
374 if_setsoftc(ifp, sc);
391 TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp);
392 NET_TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp);
393 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp);
394 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT,
395 taskqueue_thread_enqueue, &sc->smc_tq);
396 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq",
397 device_get_nameunit(sc->smc_dev));
400 sc->smc_mask = 0;
401 smc_write_1(sc, MSK, 0);
404 error = bus_setup_intr(dev, sc->smc_irq,
405 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih);
419 struct smc_softc *sc;
421 sc = device_get_softc(dev);
422 SMC_LOCK(sc);
423 smc_stop(sc);
424 SMC_UNLOCK(sc);
426 if (sc->smc_ifp != NULL) {
427 ether_ifdetach(sc->smc_ifp);
430 callout_drain(&sc->smc_watchdog);
431 callout_drain(&sc->smc_mii_tick_ch);
434 if (sc->smc_if_getcapenable(ifp) & IFCAP_POLLING)
435 ether_poll_deregister(sc->smc_ifp);
438 if (sc->smc_ih != NULL)
439 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih);
441 if (sc->smc_tq != NULL) {
442 taskqueue_drain(sc->smc_tq, &sc->smc_intr);
443 taskqueue_drain(sc->smc_tq, &sc->smc_rx);
444 taskqueue_drain(sc->smc_tq, &sc->smc_tx);
445 taskqueue_free(sc->smc_tq);
446 sc->smc_tq = NULL;
449 if (sc->smc_ifp != NULL) {
450 if_free(sc->smc_ifp);
453 bus_generic_detach(sc->smc_dev);
455 if (sc->smc_reg != NULL) {
457 if (sc->smc_usemem)
460 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid,
461 sc->smc_reg);
464 if (sc->smc_irq != NULL)
465 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid,
466 sc->smc_irq);
468 if (mtx_initialized(&sc->smc_mtx))
469 mtx_destroy(&sc->smc_mtx);
497 struct smc_softc *sc;
499 sc = if_getsoftc(ifp);
500 SMC_LOCK(sc);
502 SMC_UNLOCK(sc);
508 struct smc_softc *sc;
512 sc = if_getsoftc(ifp);
513 SMC_ASSERT_LOCKED(sc);
537 sc->smc_pending = m;
550 smc_select_bank(sc, 2);
551 smc_mmu_wait(sc);
552 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages);
559 if (smc_read_1(sc, IST) & ALLOC_INT) {
560 smc_write_1(sc, ACK, ALLOC_INT);
570 sc->smc_mask |= ALLOC_INT;
572 smc_write_1(sc, MSK, sc->smc_mask);
576 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
583 struct smc_softc *sc;
591 sc = if_getsoftc(ifp);
593 SMC_LOCK(sc);
595 if (sc->smc_pending == NULL) {
596 SMC_UNLOCK(sc);
600 m = m0 = sc->smc_pending;
601 sc->smc_pending = NULL;
602 smc_select_bank(sc, 2);
607 packet = smc_read_1(sc, ARR);
617 SMC_UNLOCK(sc);
624 smc_write_1(sc, PNR, packet);
625 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR);
632 smc_write_2(sc, DATA0, 0);
633 smc_write_2(sc, DATA0, len);
642 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2);
650 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]);
652 smc_write_2(sc, DATA0, 0);
657 sc->smc_mask |= TX_EMPTY_INT;
659 smc_write_1(sc, MSK, sc->smc_mask);
664 smc_mmu_wait(sc);
665 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE);
666 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc);
673 SMC_UNLOCK(sc);
690 struct smc_softc *sc;
695 sc = if_getsoftc(ifp);
698 SMC_LOCK(sc);
700 packet = smc_read_1(sc, FIFO_RX);
717 smc_select_bank(sc, 2);
718 smc_write_1(sc, PNR, packet);
719 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
724 status = smc_read_2(sc, DATA0);
725 len = smc_read_2(sc, DATA0) & RX_LEN_MASK;
734 smc_mmu_wait(sc);
735 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
753 smc_select_bank(sc, 2);
754 smc_write_1(sc, PNR, packet);
755 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
757 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1);
760 *data = smc_read_1(sc, DATA0);
766 smc_mmu_wait(sc);
767 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
779 packet = smc_read_1(sc, FIFO_RX);
782 sc->smc_mask |= RCV_INT;
784 smc_write_1(sc, MSK, sc->smc_mask);
786 SMC_UNLOCK(sc);
801 struct smc_softc *sc;
803 sc = if_getsoftc(ifp);
805 SMC_LOCK(sc);
807 SMC_UNLOCK(sc);
810 SMC_UNLOCK(sc);
813 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
821 struct smc_softc *sc;
824 sc = (struct smc_softc *)context;
829 curbank = (smc_read_2(sc, BSR) & BSR_BANK_MASK);
834 smc_select_bank(sc, 2);
835 smc_write_1(sc, MSK, 0);
838 smc_select_bank(sc, curbank);
840 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
847 struct smc_softc *sc;
853 sc = if_getsoftc(ifp);
855 SMC_LOCK(sc);
857 smc_select_bank(sc, 2);
862 status = smc_read_1(sc, IST) & sc->smc_mask;
871 packet = smc_read_1(sc, FIFO_TX);
873 callout_stop(&sc->smc_watchdog);
874 smc_select_bank(sc, 2);
875 smc_write_1(sc, PNR, packet);
876 smc_write_2(sc, PTR, 0 | PTR_READ |
878 smc_select_bank(sc, 0);
879 tcr = smc_read_2(sc, EPHSR);
882 device_printf(sc->smc_dev,
885 smc_select_bank(sc, 2);
886 smc_mmu_wait(sc);
887 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT);
889 smc_select_bank(sc, 0);
890 tcr = smc_read_2(sc, TCR);
892 smc_write_2(sc, TCR, tcr);
893 smc_select_bank(sc, 2);
894 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
900 smc_write_1(sc, ACK, TX_INT);
907 smc_write_1(sc, ACK, RCV_INT);
908 sc->smc_mask &= ~RCV_INT;
909 taskqueue_enqueue(sc->smc_tq, &sc->smc_rx);
916 smc_write_1(sc, ACK, ALLOC_INT);
917 sc->smc_mask &= ~ALLOC_INT;
918 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
925 smc_write_1(sc, ACK, RX_OVRN_INT);
933 smc_write_1(sc, ACK, TX_EMPTY_INT);
934 sc->smc_mask &= ~TX_EMPTY_INT;
935 callout_stop(&sc->smc_watchdog);
940 smc_select_bank(sc, 0);
941 counter = smc_read_2(sc, ECR);
942 smc_select_bank(sc, 2);
950 taskqueue_enqueue(sc->smc_tq, &sc->smc_tx);
956 smc_select_bank(sc, 2);
958 smc_write_1(sc, MSK, sc->smc_mask);
960 SMC_UNLOCK(sc);
966 struct smc_softc *sc;
969 sc = device_get_softc(dev);
971 SMC_ASSERT_LOCKED(sc);
972 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
974 device_get_nameunit(sc->smc_dev),
975 smc_read_2(sc, BSR) & BSR_BANK_MASK));
977 val = smc_read_2(sc, MGMT);
978 smc_barrier(sc, MGMT, 2,
987 struct smc_softc *sc;
989 sc = device_get_softc(dev);
991 SMC_ASSERT_LOCKED(sc);
992 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
994 device_get_nameunit(sc->smc_dev),
995 smc_read_2(sc, BSR) & BSR_BANK_MASK));
997 smc_write_2(sc, MGMT, val);
998 smc_barrier(sc, MGMT, 2,
1005 struct smc_softc *sc;
1008 sc = device_get_softc(dev);
1010 SMC_LOCK(sc);
1012 smc_select_bank(sc, 3);
1016 SMC_UNLOCK(sc);
1023 struct smc_softc *sc;
1025 sc = device_get_softc(dev);
1027 SMC_LOCK(sc);
1029 smc_select_bank(sc, 3);
1033 SMC_UNLOCK(sc);
1040 struct smc_softc *sc;
1044 sc = device_get_softc(dev);
1045 mii = device_get_softc(sc->smc_miibus);
1047 SMC_LOCK(sc);
1049 smc_select_bank(sc, 0);
1050 tcr = smc_read_2(sc, TCR);
1057 smc_write_2(sc, TCR, tcr);
1059 SMC_UNLOCK(sc);
1065 struct smc_softc *sc;
1068 sc = if_getsoftc(ifp);
1069 if (sc->smc_miibus == NULL)
1072 mii = device_get_softc(sc->smc_miibus);
1079 struct smc_softc *sc;
1082 sc = if_getsoftc(ifp);
1083 if (sc->smc_miibus == NULL)
1086 mii = device_get_softc(sc->smc_miibus);
1095 struct smc_softc *sc;
1097 sc = (struct smc_softc *)context;
1099 if (sc->smc_miibus == NULL)
1102 SMC_UNLOCK(sc);
1104 mii_tick(device_get_softc(sc->smc_miibus));
1105 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc);
1109 smc_mii_mediachg(struct smc_softc *sc)
1112 if (sc->smc_miibus == NULL)
1114 mii_mediachg(device_get_softc(sc->smc_miibus));
1118 smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command)
1122 if (sc->smc_miibus == NULL)
1125 mii = device_get_softc(sc->smc_miibus);
1126 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command));
1130 smc_reset(struct smc_softc *sc)
1134 SMC_ASSERT_LOCKED(sc);
1136 smc_select_bank(sc, 2);
1141 smc_write_1(sc, MSK, 0);
1146 smc_select_bank(sc, 0);
1147 smc_write_2(sc, RCR, RCR_SOFT_RST);
1152 smc_select_bank(sc, 1);
1153 smc_write_2(sc, CR, CR_EPH_POWER_EN);
1159 smc_select_bank(sc, 0);
1160 smc_write_2(sc, TCR, 0);
1161 smc_write_2(sc, RCR, 0);
1166 smc_select_bank(sc, 1);
1167 ctr = smc_read_2(sc, CTRL);
1169 smc_write_2(sc, CTRL, ctr);
1174 smc_select_bank(sc, 2);
1175 smc_mmu_wait(sc);
1176 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET);
1180 smc_enable(struct smc_softc *sc)
1184 SMC_ASSERT_LOCKED(sc);
1185 ifp = sc->smc_ifp;
1190 smc_select_bank(sc, 0);
1191 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT)
1197 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN);
1198 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC);
1203 smc_select_bank(sc, 2);
1204 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT;
1206 smc_write_1(sc, MSK, sc->smc_mask);
1210 smc_stop(struct smc_softc *sc)
1213 SMC_ASSERT_LOCKED(sc);
1218 callout_stop(&sc->smc_watchdog);
1219 callout_stop(&sc->smc_mii_tick_ch);
1224 smc_select_bank(sc, 2);
1225 sc->smc_mask = 0;
1226 smc_write_1(sc, MSK, 0);
1228 ether_poll_deregister(sc->smc_ifp);
1235 smc_select_bank(sc, 0);
1236 smc_write_2(sc, TCR, 0);
1237 smc_write_2(sc, RCR, 0);
1239 if_setdrvflagbits(sc->smc_ifp, 0, IFF_DRV_RUNNING);
1245 struct smc_softc *sc;
1247 sc = (struct smc_softc *)arg;
1248 device_printf(sc->smc_dev, "watchdog timeout\n");
1249 taskqueue_enqueue(sc->smc_tq, &sc->smc_intr);
1255 struct smc_softc *sc;
1257 sc = (struct smc_softc *)context;
1258 SMC_LOCK(sc);
1259 smc_init_locked(sc);
1260 SMC_UNLOCK(sc);
1264 smc_init_locked(struct smc_softc *sc)
1268 SMC_ASSERT_LOCKED(sc);
1269 ifp = sc->smc_ifp;
1273 smc_reset(sc);
1274 smc_enable(sc);
1281 if (sc->smc_mii_tick != NULL)
1282 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc);
1285 SMC_UNLOCK(sc);
1287 SMC_LOCK(sc);
1295 struct smc_softc *sc;
1298 sc = if_getsoftc(ifp);
1305 SMC_LOCK(sc);
1306 smc_stop(sc);
1307 SMC_UNLOCK(sc);
1309 smc_init(sc);
1310 if (sc->smc_mii_mediachg != NULL)
1311 sc->smc_mii_mediachg(sc);
1318 SMC_LOCK(sc);
1319 smc_setmcast(sc);
1320 SMC_UNLOCK(sc);
1327 if (sc->smc_mii_mediaioctl == NULL) {
1331 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd);