Lines Matching +full:32 +full:- +full:bit
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2016 Solarflare Communications Inc.
48 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
54 * FR_AB_EE_VPD_CFG0_REG(128bit):
76 #define FRF_AB_EE_VPD_BASE_LBN 32
94 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
100 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
130 #define FRF_AB_PCIE_PARLPBK_LBN 32
162 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
168 * FR_AB_PCIE_SD_CTL45_REG(128bit):
188 #define FRF_AB_PCIE_DTX0_LBN 32
208 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit):
214 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit):
226 #define FRF_AB_PCIE_PRBSERRH0_LBN 32
248 * FR_AB_HW_INIT_REG_SF(128bit):
254 * FR_AZ_HW_INIT_REG(128bit):
282 #define FRF_AZ_TLP_ATTR_LBN 32
302 * FR_AB_NIC_STAT_REG_SF(128bit):
308 * FR_AB_NIC_STAT_REG(128bit):
334 * FR_AB_GLB_CTL_REG_SF(128bit):
340 * FR_AB_GLB_CTL_REG(128bit):
432 * FR_AZ_IOM_IND_ADR_REG(32bit):
433 * IO-mapped indirect access address register
444 * FR_AZ_IOM_IND_DAT_REG(32bit):
445 * IO-mapped indirect access data register
451 #define FRF_AZ_IOM_IND_DAT_WIDTH 32
454 * FR_AZ_ADR_REGION_REG(128bit):
464 #define FRF_AZ_ADR_REGION1_LBN 32
470 * FR_AZ_INT_EN_REG_KER(128bit):
486 * FR_AZ_INT_EN_REG_CHAR(128bit):
502 * FR_AZ_INT_ADR_REG_KER(128bit):
513 #define FRF_AZ_INT_ADR_KER_DW0_WIDTH 32
514 #define FRF_AZ_INT_ADR_KER_DW1_LBN 32
515 #define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32
518 * FR_AZ_INT_ADR_REG_CHAR(128bit):
529 #define FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32
530 #define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32
531 #define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32
534 * FR_AA_INT_ACK_KER(32bit):
541 #define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32
544 * FR_BZ_INT_ISR0_REG(128bit):
553 #define FRF_BZ_INT_ISR_REG_DW0_WIDTH 32
554 #define FRF_BZ_INT_ISR_REG_DW1_LBN 32
555 #define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32
558 * FR_AB_EE_SPI_HCMD_REG(128bit):
582 * FR_CZ_USR_EV_CFG(32bit):
594 * FR_AB_EE_SPI_HADR_REG(128bit):
606 * FR_AB_EE_SPI_HDATA_REG(128bit):
613 #define FRF_AB_EE_SPI_HDATA3_WIDTH 32
615 #define FRF_AB_EE_SPI_HDATA2_WIDTH 32
616 #define FRF_AB_EE_SPI_HDATA1_LBN 32
617 #define FRF_AB_EE_SPI_HDATA1_WIDTH 32
619 #define FRF_AB_EE_SPI_HDATA0_WIDTH 32
622 * FR_AB_EE_BASE_PAGE_REG(128bit):
634 * FR_AB_EE_VPD_SW_CNTL_REG(128bit):
648 * FR_AB_EE_VPD_SW_DATA_REG(128bit):
655 #define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32
658 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit):
664 #define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32
665 #define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32
672 * FR_AB_GPIO_CTL_REG(128bit):
740 #define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32
796 * FR_AZ_FATAL_INTR_REG_KER(128bit):
828 #define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32
860 * FR_AZ_FATAL_INTR_REG_CHAR(128bit):
892 #define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32
924 * FR_AZ_DP_CTRL_REG(128bit):
934 * FR_AZ_MEM_STAT_REG(128bit):
943 #define FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32
951 #define FRF_AB_MBIST_ERR_DW0_WIDTH 32
952 #define FRF_AB_MBIST_ERR_DW1_LBN 32
957 #define FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32
958 #define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32
962 * FR_PORT0_CS_DEBUG_REG(128bit):
986 #define FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32
1007 * FR_AZ_DRIVER_REG(128bit):
1008 * Driver scratch register [0-7]
1016 #define FRF_AZ_DRIVER_DW0_WIDTH 32
1019 * FR_AZ_ALTERA_BUILD_REG(128bit):
1026 #define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32
1029 * FR_AZ_CSR_SPARE_REG(128bit):
1040 #define FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32
1044 #define FRF_AZ_CSR_SPARE_BITS_WIDTH 32
1047 * FR_BZ_DEBUG_DATA_OUT_REG(128bit):
1059 * FR_BZ_EVQ_RPTR_REGP0(32bit):
1067 * FR_AA_EVQ_RPTR_REG_KER(32bit):
1075 * FR_AZ_EVQ_RPTR_REG(32bit):
1084 * FR_BB_EVQ_RPTR_REGP123(32bit):
1098 * FR_BZ_TIMER_COMMAND_REGP0(128bit):
1106 * FR_AA_TIMER_COMMAND_REG_KER(128bit):
1114 * FR_AB_TIMER_COMMAND_REGP123(128bit):
1122 * FR_AA_TIMER_COMMAND_REGP0(128bit):
1140 * FR_AZ_DRV_EV_REG(128bit):
1151 #define FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32
1152 #define FRF_AZ_DRV_EV_DATA_DW1_LBN 32
1153 #define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32
1156 * FR_AZ_EVQ_CTL_REG(128bit):
1174 * FR_AZ_EVQ_CNT1_REG(128bit):
1196 * FR_AZ_EVQ_CNT2_REG(128bit):
1218 * FR_CZ_USR_EV_REG(32bit):
1227 #define FRF_CZ_USR_EV_DATA_WIDTH 32
1230 * FR_AZ_BUF_TBL_CFG_REG(128bit):
1240 * FR_AZ_SRM_RX_DC_CFG_REG(128bit):
1252 * FR_AZ_SRM_TX_DC_CFG_REG(128bit):
1262 * FR_AZ_SRM_CFG_REG(128bit):
1268 * FR_AZ_SRM_CFG_REG(128bit):
1286 * FR_AZ_BUF_TBL_UPD_REG(128bit):
1296 #define FRF_AZ_BUF_CLR_END_ID_LBN 32
1302 * FR_AZ_SRM_UPD_EVQ_REG(128bit):
1312 * FR_AZ_SRAM_PARITY_REG(128bit):
1330 * FR_AZ_RX_CFG_REG(128bit):
1394 * FR_AZ_RX_FILTER_CTL_REG(128bit):
1422 #define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32
1434 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit):
1446 * FR_BZ_RX_DESC_UPD_REGP0(128bit):
1454 * FR_AA_RX_DESC_UPD_REG_KER(128bit):
1462 * FR_AB_RX_DESC_UPD_REGP123(128bit):
1470 * FR_AA_RX_DESC_UPD_REGP0(128bit):
1485 #define FRF_AZ_RX_DESC_DW0_WIDTH 32
1486 #define FRF_AZ_RX_DESC_DW1_LBN 32
1487 #define FRF_AZ_RX_DESC_DW1_WIDTH 32
1490 * FR_AZ_RX_DC_CFG_REG(128bit):
1506 * FR_AZ_RX_DC_PF_WM_REG(128bit):
1507 * Receive descriptor cache pre-fetch watermark register
1518 * FR_BZ_RX_RSS_TKEY_REG(128bit):
1525 #define FRF_BZ_RX_RSS_TKEY_WIDTH 32
1527 #define FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32
1529 #define FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32
1530 #define FRF_BZ_RX_RSS_TKEY_DW1_LBN 32
1531 #define FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32
1533 #define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32
1536 * FR_AZ_RX_NODESC_DROP_REG(128bit):
1546 * FR_AZ_RX_SELF_RST_REG(128bit):
1564 * FR_AZ_RX_DEBUG_REG(128bit):
1573 #define FRF_AZ_RX_DEBUG_DW0_WIDTH 32
1574 #define FRF_AZ_RX_DEBUG_DW1_LBN 32
1575 #define FRF_AZ_RX_DEBUG_DW1_WIDTH 32
1578 * FR_AZ_RX_PUSH_DROP_REG(128bit):
1585 #define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32
1588 * FR_CZ_RX_RSS_IPV6_REG1(128bit):
1597 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32
1598 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32
1599 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32
1601 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32
1603 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32
1606 * FR_CZ_RX_RSS_IPV6_REG2(128bit):
1615 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32
1616 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32
1617 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32
1619 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32
1621 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32
1624 * FR_CZ_RX_RSS_IPV6_REG3(128bit):
1639 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32
1640 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32
1641 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32
1644 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit):
1656 * FR_BZ_TX_DESC_UPD_REGP0(128bit):
1664 * FR_AA_TX_DESC_UPD_REG_KER(128bit):
1672 * FR_AB_TX_DESC_UPD_REGP123(128bit):
1680 * FR_AA_TX_DESC_UPD_REGP0(128bit):
1695 #define FRF_AZ_TX_DESC_DW0_WIDTH 32
1696 #define FRF_AZ_TX_DESC_DW1_LBN 32
1697 #define FRF_AZ_TX_DESC_DW1_WIDTH 32
1702 * FR_AZ_TX_DC_CFG_REG(128bit):
1715 * FR_AA_TX_CHKSM_CFG_REG(128bit):
1722 #define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32
1724 #define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32
1725 #define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32
1726 #define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32
1728 #define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32
1731 * FR_AZ_TX_CFG_REG(128bit):
1773 * FR_AZ_TX_PUSH_DROP_REG(128bit):
1780 #define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32
1783 * FR_AZ_TX_RESERVED_REG(128bit):
1853 * FR_BZ_TX_PACE_REG(128bit):
1859 * FR_AA_TX_PACE_REG(128bit):
1875 * FR_AZ_TX_PACE_DROP_QID_REG(128bit):
1885 * FR_AB_TX_VLAN_REG(128bit):
1927 #define FRF_AB_TX_VLAN2_LBN 32
1943 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit):
1981 #define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32
2017 * FR_AB_TX_IPFIL_TBL(128bit):
2026 #define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32
2028 #define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32
2029 #define FRF_AB_TX_IPFIL_MASK_0_LBN 32
2030 #define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32
2032 #define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32
2035 * FR_AB_MD_TXD_REG(128bit):
2045 * FR_AB_MD_RXD_REG(128bit):
2055 * FR_AB_MD_CS_REG(128bit):
2085 * FR_AB_MD_PHY_ADR_REG(128bit):
2095 * FR_AB_MD_ID_REG(128bit):
2107 * FR_AB_MD_STAT_REG(128bit):
2125 * FR_AB_MAC_STAT_DMA_REG(128bit):
2136 #define FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32
2137 #define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32
2141 * FR_AB_MAC_CTRL_REG(128bit):
2167 * FR_BB_GEN_MODE_REG(128bit):
2183 * FR_AB_MAC_MC_HASH_REG0(128bit):
2192 #define FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32
2193 #define FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32
2194 #define FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32
2196 #define FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32
2198 #define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32
2201 * FR_AB_MAC_MC_HASH_REG1(128bit):
2210 #define FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32
2211 #define FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32
2212 #define FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32
2214 #define FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32
2216 #define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32
2219 * FR_AB_GM_CFG1_REG(32bit):
2253 * FR_AB_GM_CFG2_REG(32bit):
2277 * FR_AB_GM_IPG_REG(32bit):
2293 * FR_AB_GM_HD_REG(32bit):
2315 * FR_AB_GM_MAX_FLEN_REG(32bit):
2325 * FR_AB_GM_TEST_REG(32bit):
2341 * FR_AB_GM_ADR1_REG(32bit):
2357 * FR_AB_GM_ADR2_REG(32bit):
2369 * FR_AB_GMF_CFG0_REG(32bit):
2407 * FR_AB_GMF_CFG1_REG(32bit):
2419 * FR_AB_GMF_CFG2_REG(32bit):
2431 * FR_AB_GMF_CFG3_REG(32bit):
2443 * FR_AB_GMF_CFG4_REG(32bit):
2453 * FR_AB_GMF_CFG5_REG(32bit):
2473 * FR_BB_TX_SRC_MAC_TBL(128bit):
2484 #define FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32
2490 #define FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32
2491 #define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32
2495 * FR_BB_TX_SRC_MAC_CTL_REG(128bit):
2511 * FR_AB_XM_ADR_LO_REG(128bit):
2518 #define FRF_AB_XM_ADR_LO_WIDTH 32
2521 * FR_AB_XM_ADR_HI_REG(128bit):
2531 * FR_AB_XM_GLB_CFG_REG(128bit):
2555 * FR_AB_XM_TX_CFG_REG(128bit):
2581 * FR_AB_XM_RX_CFG_REG(128bit):
2611 * FR_AB_XM_MGT_INT_MASK(128bit):
2631 * FR_AB_XM_FC_REG(128bit):
2657 * FR_AB_XM_PAUSE_TIME_REG(128bit):
2669 * FR_AB_XM_TX_PARAM_REG(128bit):
2685 * FR_AB_XM_RX_PARAM_REG(128bit):
2697 * FR_AB_XM_MGT_INT_MSK_REG(128bit):
2715 * FR_AB_XX_PWR_RST_REG(128bit):
2777 * FR_AB_XX_SD_CTL_REG(128bit):
2813 * FR_AB_XX_TXDRV_CTL_REG(128bit):
2837 * FR_AB_XX_PRBS_CTL_REG(128bit):
2893 * FR_AB_XX_PRBS_CHK_REG(128bit):
2935 * FR_AB_XX_PRBS_ERR_REG(128bit):
2951 * FR_AB_XX_CORE_STAT_REG(128bit):
3023 * FR_AA_RX_DESC_PTR_TBL_KER(128bit):
3031 * FR_AZ_RX_DESC_PTR_TBL(128bit):
3078 * FR_AA_TX_DESC_PTR_TBL_KER(128bit):
3086 * FR_AZ_TX_DESC_PTR_TBL(128bit):
3139 * FR_AA_EVQ_PTR_TBL_KER(128bit):
3147 * FR_AZ_EVQ_PTR_TBL(128bit):
3177 * FR_AA_BUF_HALF_TBL_KER(64bit):
3185 * FR_AZ_BUF_HALF_TBL(64bit):
3196 #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32
3204 * FR_AA_BUF_FULL_TBL_KER(64bit):
3212 * FR_AZ_BUF_FULL_TBL(64bit):
3235 #define FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32
3242 * FR_AZ_RX_FILTER_TBL0(128bit):
3247 #define FR_AZ_RX_FILTER_TBL0_STEP 32
3250 * FR_AB_RX_FILTER_TBL1(128bit):
3255 #define FR_AB_RX_FILTER_TBL1_STEP 32
3267 #define FRF_AZ_DEST_IP_WIDTH 32
3271 #define FRF_AZ_SRC_IP_WIDTH 32
3276 * FR_CZ_RX_MAC_FILTER_TBL0(128bit):
3281 #define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32
3297 #define FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32
3304 * FR_AZ_TIMER_TBL(128bit):
3315 #define FRF_CZ_INT_ARMD_LBN 32
3341 * FR_BZ_TX_PACE_TBL(128bit):
3350 * FR_AA_TX_PACE_TBL(128bit):
3362 * FR_BZ_RX_INDIRECTION_TBL(7bit):
3374 * FR_CZ_TX_FILTER_TBL0(128bit):
3387 #define FRF_CZ_TIFT_DEST_IP_WIDTH 32
3391 #define FRF_CZ_TIFT_SRC_IP_WIDTH 32
3396 * FR_CZ_TX_MAC_FILTER_TBL0(128bit):
3411 #define FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32
3418 * FR_CZ_MC_TREG_SMEM(32bit):
3427 #define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32
3430 * FR_BB_MSIX_VECTOR_TABLE(128bit):
3438 * FR_CZ_MSIX_VECTOR_TABLE(128bit):
3451 #define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32
3452 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32
3453 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32
3455 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32
3458 * FR_BB_MSIX_PBA_TABLE(32bit):
3459 * MSIX Pending Bit Array
3466 * FR_CZ_MSIX_PBA_TABLE(32bit):
3467 * MSIX Pending Bit Array
3472 #define FR_CZ_MSIX_PBA_TABLE_ROWS 32
3475 #define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32
3478 * FR_AZ_SRM_DBG_REG(64bit):
3491 #define FRF_AZ_SRM_DBG_DW0_WIDTH 32
3492 #define FRF_AZ_SRM_DBG_DW1_LBN 32
3493 #define FRF_AZ_SRM_DBG_DW1_WIDTH 32
3496 * FR_AA_INT_ACK_CHAR(32bit):
3503 #define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32
3534 #define FSF_AZ_EV_DATA_DW0_WIDTH 32
3535 #define FSF_AZ_EV_DATA_DW1_LBN 32
3598 #define FSF_AZ_RX_EV_Q_LABEL_LBN 32
3625 #define FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32
3626 #define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32
3640 #define FSF_AZ_TX_EV_Q_LABEL_LBN 32
3663 #define FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32
3664 #define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32
3680 #define FSF_CZ_USER_QID_LBN 32
3683 #define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32
3690 #define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32
3698 /* Sub-fields of an RX flush completion event */
3706 * Falcon non-volatile configuration