Lines Matching +full:wp +full:- +full:inverted
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
112 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
116 { "marvell,armada-380-sdhci", SDHCI_FDT_ARMADA38X },
117 { "qcom,sdhci-msm-v4", SDHCI_FDT_QUALCOMM },
118 { "rockchip,rk3399-sdhci-5.1", SDHCI_FDT_RK3399 },
120 { "rockchip,rk3568-dwcmshc", SDHCI_FDT_RK3568 },
121 { "xlnx,zynqmp-8.9a", SDHCI_FDT_XLNX_ZMP },
138 bool wp_inverted; /* WP pin is inverted */
139 bool wp_disabled; /* WP pin is not supported */
199 node = ofw_bus_get_node(sc->dev);
202 device_printf(sc->dev, "cannot parse 'reg' property\n");
207 "#clock-cells", &ncells);
209 device_printf(sc->dev, "couldn't find parent clocks\n");
213 nclocks = ofw_bus_string_list_to_array(node, "clock-output-names",
219 clkdom = clkdom_create(sc->dev);
227 def.parent_names[0] = clk_get_name(sc->clk_xin);
232 device_printf(sc->dev, "cannot create clknode\n");
237 clksc->clkdev = device_get_parent(sc->dev);
243 device_printf(sc->dev, "cannot finalize clkdom initialization\n");
258 error = clk_get_by_ofw_name(dev, 0, "clk_xin", &sc->clk_xin);
263 error = clk_enable(sc->clk_xin);
268 error = clk_get_by_ofw_name(dev, 0, "clk_ahb", &sc->clk_ahb);
273 error = clk_enable(sc->clk_ahb);
288 error = phy_get_by_ofw_name(sc->dev, 0, "phy_arasan", &sc->phy);
292 device_printf(sc->dev, "Could not get phy\n");
295 error = phy_enable(sc->phy);
297 device_printf(sc->dev, "Could not enable phy\n");
310 node = ofw_bus_get_node(sc->dev);
311 if (OF_hasprop(node, "arasan,soc-ctl-syscon") &&
312 syscon_get_by_ofw_property(sc->dev, node,
313 "arasan,soc-ctl-syscon", &sc->syscon) != 0) {
314 device_printf(sc->dev, "cannot get syscon handle\n");
329 error = clk_get_freq(sc->clk_xin, &freq);
338 SYSCON_WRITE_4(sc->syscon, RK3399_GRF_EMMCCORE_CON11, (mask << 16) | val);
344 SYSCON_WRITE_4(sc->syscon, RK3399_GRF_EMMCCORE_CON0, (mask << 16) | val);
354 return (bus_read_1(sc->mem_res[slot->num], off));
363 bus_write_1(sc->mem_res[slot->num], off, val);
371 return (bus_read_2(sc->mem_res[slot->num], off));
380 bus_write_2(sc->mem_res[slot->num], off, val);
389 val32 = bus_read_4(sc->mem_res[slot->num], off);
390 if (off == SDHCI_CAPABILITIES && sc->no_18v)
402 bus_write_4(sc->mem_res[slot->num], off, val);
411 bus_read_multi_4(sc->mem_res[slot->num], off, data, count);
420 bus_write_multi_4(sc->mem_res[slot->num], off, data, count);
429 for (i = 0; i < sc->num_slots; i++)
430 sdhci_generic_intr(&sc->slots[i]);
438 if (sc->wp_disabled)
440 return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted);
450 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data ==
456 clk_set_freq(sc->clk_core, clock, 0);
459 bus_write_4(sc->mem_res[slot->num],
461 bus_write_4(sc->mem_res[slot->num],
463 bus_write_4(sc->mem_res[slot->num],
465 bus_write_4(sc->mem_res[slot->num],
470 bus_write_4(sc->mem_res[slot->num],
473 bus_write_4(sc->mem_res[slot->num],
475 bus_write_4(sc->mem_res[slot->num],
479 val = bus_read_4(sc->mem_res[slot->num],
486 bus_write_4(sc->mem_res[slot->num], RK3568_EMMC_ATCTRL,
488 bus_write_4(sc->mem_res[slot->num],
491 bus_write_4(sc->mem_res[slot->num],
494 bus_write_4(sc->mem_res[slot->num],
510 sc->quirks = 0;
511 sc->num_slots = 1;
512 sc->max_clk = 0;
517 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
519 sc->quirks = SDHCI_QUIRK_BROKEN_AUTO_STOP;
523 sc->quirks = SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
525 sc->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
532 sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
533 device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller");
547 /* Allow dts to patch quirks, slots, and max-frequency. */
549 sc->quirks = cid;
550 if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0)
551 sc->num_slots = cid;
552 if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0)
553 sc->max_clk = cid;
554 if (OF_hasprop(node, "no-1-8-v"))
555 sc->no_18v = true;
556 if (OF_hasprop(node, "wp-inverted"))
557 sc->wp_inverted = true;
558 if (OF_hasprop(node, "disable-wp"))
559 sc->wp_disabled = true;
571 sc->dev = dev;
575 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
577 if (sc->irq_res == NULL) {
582 compat = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
610 if (clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core)) {
614 clk_enable(sc->clk_core);
621 slots = sc->num_slots; /* number of slots determined in probe(). */
622 sc->num_slots = 0;
624 slot = &sc->slots[sc->num_slots];
628 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
630 if (sc->mem_res[i] == NULL) {
636 slot->quirks = sc->quirks;
637 slot->caps = sc->caps;
638 slot->max_clk = sc->max_clk;
639 slot->sdma_boundary = sc->sdma_boundary;
644 sc->num_slots++;
646 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
649 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
650 NULL, sdhci_fdt_intr, sc, &sc->intrhand);
657 for (i = 0; i < sc->num_slots; i++)
658 sdhci_start_slot(&sc->slots[i]);
670 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
671 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
672 sc->irq_res);
674 for (i = 0; i < sc->num_slots; i++) {
675 sdhci_cleanup_slot(&sc->slots[i]);
677 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);