Lines Matching +full:controller +full:- +full:data
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 /* Controller doesn't honor resets unless we touch the clock register */
38 /* Controller really supports DMA */
40 /* Controller has unusable DMA engine */
42 /* Controller doesn't like to be reset when there is no card inserted. */
44 /* Controller has flaky internal state so reset it on each ios change */
46 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
48 /* Controller needs to be reset after each request to stay stable */
50 /* Controller has an off-by-one issue with timeout value */
52 /* Controller has broken read timings */
54 /* Controller needs lowered frequency */
56 /* Data timeout is invalid, should use SD clock */
62 /* Hardware shifts the 136-bit response, don't do it in software. */
64 /* Wait to see reset bit asserted before waiting for de-asserted */
66 /* Leave controller in standard mode when putting card in HS mode. */
72 /* All controller slots are non-removable. */
74 /* Issue custom Intel controller reset sequence after power-up. */
76 /* Data timeout is invalid, use 1 MHz clock instead. */
78 /* Controller doesn't allow access boot partitions. */
80 /* Controller waits for busy responses. */
82 /* Controller supports eMMC DDR52 mode. */
84 /* Controller support for UHS DDR50 mode is broken. */
86 /* Controller support for eMMC HS200 mode is broken. */
88 /* Controller reports support for eMMC HS400 mode as SDHCI_CAN_MMC_HS400. */
90 /* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */
92 /* Controller does not support or the support for ACMD12 is broken. */
94 /* Controller supports eMMC HS400 mode if SDHCI_CAN_SDR104 is set. */
96 /* SDMA boundary in SDHCI_BLOCK_SIZE broken - use front-end supplied value. */
100 * Controller registers
271 #define SDHCI_CTRL2_MMC_HS400 0x0005 /* non-standard */
311 #define SDHCI_CAN_MMC_HS400 0x80000000 /* non-standard */
379 struct callout timeout_callout;/* Card command/data response timeout */
380 struct callout retune_callout; /* Re-tuning mode 1 callout */
387 struct mmc_data *tune_data; /* Tuning data of tuning command */
388 uint32_t retune_ticks; /* Re-tuning callout ticks [hz] */
391 size_t offset; /* Data buffer offset */
393 uint8_t retune_count; /* Controller re-tuning count [s] */
394 uint8_t retune_mode; /* Controller re-tuning mode */
398 uint8_t retune_req; /* Re-tuning request status */
399 #define SDHCI_RETUNE_REQ_NEEDED 0x01 /* Re-tuning w/o circuit reset needed */
400 #define SDHCI_RETUNE_REQ_RESET 0x02 /* Re-tuning w/ circuit reset needed */
409 #define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */
427 /* performs generic clean-up for platform transfers */