Lines Matching +full:int +full:- +full:clock +full:- +full:stable +full:- +full:broken
1 /*-
105 * Freescale-specific registers, or in some cases the layout of bits within the
106 * sdhci-defined register is different on Freescale. These names all begin with
112 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */
161 * The clock enable bits exist in different registers for ESDHC vs USDHC, but
163 * standard sdhci clock register, but in different bit positions and meanings
177 {"fsl,imx6q-usdhc", HWTYPE_USDHC},
178 {"fsl,imx6sl-usdhc", HWTYPE_USDHC},
179 {"fsl,imx53-esdhc", HWTYPE_ESDHC},
180 {"fsl,imx51-esdhc", HWTYPE_ESDHC},
193 return (bus_read_4(sc->mem_res, off));
200 bus_write_4(sc->mem_res, off, val);
263 if (sc->hwtype == HWTYPE_USDHC) {
278 } else if (sc->hwtype == HWTYPE_ESDHC) {
280 * The ESDHC hardware has the typical 32-bit combined "command
286 return (sc->cmd_and_mode & 0x0000ffff);
288 return (sc->cmd_and_mode >> 16);
304 * Clock bits are scattered into various registers which differ by
323 * The hardware leaves the base clock frequency out of the capabilities
324 * register, but we filled it in by setting slot->max_clk at attach time
326 * in an sdhci 2.0 capabliities register. The timeout clock is the same
344 * masks out some Freescale-specific bits in locations defined as
361 return (val32 | sc->r1bfix_intmask);
373 bus_read_multi_4(sc->mem_res, off, data, count);
426 * The clock control stuff is complex enough to have its own function
438 * - R1B response with no data transfer should generate a DATA_END (aka
442 * - R1B response after Auto-CMD12 appears to not work, even though
453 sc->r1bfix_type = R1BFIX_AC12;
456 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
457 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
458 sc->r1bfix_type = R1BFIX_NODATA;
466 * typical combined cmd-and-mode register that allows only 32-bit
470 if (sc->hwtype == HWTYPE_USDHC) {
479 } else if (sc->hwtype == HWTYPE_ESDHC) {
481 sc->cmd_and_mode =
482 (sc->cmd_and_mode & 0xffff0000) | val;
485 sc->cmd_and_mode =
486 (sc->cmd_and_mode & 0xffff) | (val << 16);
487 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
505 sc->r1bfix_intmask &= ~val;
517 bus_write_multi_4(sc->mem_res, off, data, count);
526 * Whenever the sdhci driver writes the clock register we save a
530 * those bits, and mix in the clock status and enable bits that come
533 val = sc->sdclockreg_freq_bits;
536 * The internal clock is always enabled (actually, the hardware manages
537 * it). Whether the internal clock is stable yet after a frequency
538 * change comes from the present-state register on both hardware types.
545 * On i.MX ESDHC hardware the card bus clock enable is in the usual
548 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but
549 * no force-off for the card bus clock (the hardware runs the clock when
550 * transfers are active no matter what), so we always say the clock is
555 if (sc->hwtype == HWTYPE_ESDHC) {
575 * Save the frequency-setting bits in SDHCI format so that we can play
579 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK;
580 if (sc->hwtype == HWTYPE_ESDHC) {
583 * start and stop the sd bus clock. If the enable bit is not
584 * set, turn off the clock in hardware and we're done, otherwise
586 * the sdhci driver will use the original 8-bit divisor field
597 freq = sc->baseclk_hz >> ffs(divisor);
601 * over the sd bus clock, but no way to turn it off. (If a cmd
602 * or data transfer is in progress the clock is on, otherwise it
603 * is off.) If the clock is being disabled, we can just return
605 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit
614 freq = sc->baseclk_hz;
616 freq = sc->baseclk_hz / (2 * divisor);
622 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);)
625 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);)
629 device_printf(sc->dev,
631 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz,
636 * Adjust to zero-based values, and store them to the hardware.
639 divisor -= 1;
653 mtx_assert(&sc->slot.mtx, MA_OWNED);
664 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) {
665 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0,
674 * of fix needed was on a command-without-data we also now add in the
678 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT;
680 sc->r1bfix_intmask |= SDHCI_INT_DATA_END;
681 if (sc->r1bfix_type == R1BFIX_NODATA)
682 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE;
685 sc->r1bfix_type = R1BFIX_NONE;
695 mtx_lock(&sc->slot.mtx);
697 mtx_unlock(&sc->slot.mtx);
699 sdhci_generic_intr(&sc->slot);
708 mtx_lock(&sc->slot.mtx);
717 * not, then the wait_done routine will schedule a callout to re-check
725 * cards tend to take 10-20ms for a long-running command such as a write
728 switch (sc->r1bfix_type) {
740 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS;
743 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4,
748 mtx_unlock(&sc->slot.mtx);
749 sdhci_generic_intr(&sc->slot);
752 static int
757 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
765 return (sdhci_fdt_gpio_get_present(sc->gpio));
773 uint32_t clock;
778 if((OF_getprop(node, "clock-frequency", (void *)&clock,
779 sizeof(clock)) <= 0) || (clock == 0)) {
780 clock = mpc85xx_get_system_clock();
782 if (clock == 0) {
791 device_printf(dev, "Acquired clock: %d from DTS\n", clock);
793 return (clock);
797 static int
802 if (sc->gpio != NULL)
803 sdhci_fdt_gpio_teardown(sc->gpio);
805 callout_drain(&sc->r1bfix_callout);
807 if (sc->slot_init_done)
808 sdhci_cleanup_slot(&sc->slot);
810 if (sc->intr_cookie != NULL)
811 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
812 if (sc->irq_res != NULL)
814 rman_get_rid(sc->irq_res), sc->irq_res);
816 if (sc->mem_res != NULL) {
818 rman_get_rid(sc->mem_res), sc->mem_res);
824 static int
828 int rid, err;
834 sc->dev = dev;
836 callout_init(&sc->r1bfix_callout, 1);
838 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
839 if (sc->hwtype == HWTYPE_NONE)
843 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
845 if (!sc->mem_res) {
852 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
854 if (!sc->irq_res) {
860 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
861 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) {
867 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
870 * DMA is not really broken, I just haven't implemented it yet.
872 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
879 * re-check the status and potentially wait for more data. The main
891 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc"))
901 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev);
903 sc->baseclk_hz = imx_ccm_sdhci_hz();
905 sc->slot.max_clk = sc->baseclk_hz;
911 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
915 /* Default to big-endian on powerpc */
918 if (OF_hasprop(node, "little-endian"))
925 sdhci_init_slot(dev, &sc->slot, 0);
926 sc->slot_init_done = true;
931 sdhci_start_slot(&sc->slot);
940 static int
947 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {