Lines Matching +full:0 +full:xc00
69 SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_HT_MCS(0)]) |
99 /* 1SS, MCS 0..3 */
101 SM(R12A_TXAGC_NSS1_MCS0, power[RTWN_RIDX_VHT_MCS(0, 0)]) |
102 SM(R12A_TXAGC_NSS1_MCS1, power[RTWN_RIDX_VHT_MCS(0, 1)]) |
103 SM(R12A_TXAGC_NSS1_MCS2, power[RTWN_RIDX_VHT_MCS(0, 2)]) |
104 SM(R12A_TXAGC_NSS1_MCS3, power[RTWN_RIDX_VHT_MCS(0, 3)]));
108 SM(R12A_TXAGC_NSS1_MCS4, power[RTWN_RIDX_VHT_MCS(0, 4)]) |
109 SM(R12A_TXAGC_NSS1_MCS5, power[RTWN_RIDX_VHT_MCS(0, 5)]) |
110 SM(R12A_TXAGC_NSS1_MCS6, power[RTWN_RIDX_VHT_MCS(0, 6)]) |
111 SM(R12A_TXAGC_NSS1_MCS7, power[RTWN_RIDX_VHT_MCS(0, 7)]));
116 SM(R12A_TXAGC_NSS1_MCS8, power[RTWN_RIDX_VHT_MCS(0, 8)]) |
117 SM(R12A_TXAGC_NSS1_MCS9, power[RTWN_RIDX_VHT_MCS(0, 9)]) |
118 SM(R12A_TXAGC_NSS2_MCS0, 0) |
119 SM(R12A_TXAGC_NSS2_MCS1, 0));
122 SM(R12A_TXAGC_NSS1_MCS8, power[RTWN_RIDX_VHT_MCS(0, 8)]) |
123 SM(R12A_TXAGC_NSS1_MCS9, power[RTWN_RIDX_VHT_MCS(0, 9)]) |
124 SM(R12A_TXAGC_NSS2_MCS0, power[RTWN_RIDX_VHT_MCS(1, 0)]) |
191 write_data = 0;
194 for (i = 0; i < 3; i++) {
195 if (i == 0)
206 write_data |= ((power_level & 0xff) << (i * 8));
210 0x00ffffff, write_data);
234 if (chan <= 2) group = 0;
240 KASSERT(0, ("wrong 2GHz channel %d!\n", chan));
247 if (chan <= 42) group = 0;
262 KASSERT(0, ("wrong 5GHz channel %d!\n", chan));
266 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags));
300 power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0];
302 for (i = 0; i < sc->ntxchains; i++) {
329 power[ridx] += rs->ofdm_tx_pwr_diff_5g[chain][0];
331 for (i = 0; i < sc->ntxchains; i++) {
350 for (ridx = RTWN_RIDX_VHT_MCS(i, 0);
363 for (ridx = RTWN_RIDX_VHT_MCS(0, 0);
376 /* TODO: dump VHT 0..9 for each spatial stream */
387 for (i = 0; i < sc->ntxchains; i++) {
388 memset(power, 0, sizeof(power));
404 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00);
405 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000);
407 rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800);
413 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);
415 0, 0x40000000);
420 0, 0x40000000);
423 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);
425 0x40000000, 0);
434 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);
436 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);
465 KASSERT(0, ("wrong channel flags %08X\n", c->ic_flags));
470 for (i = 0; i < 2; i++) {
471 uint16_t val = 0;
473 switch ((swing >> i * 2) & 0x3) {
474 case 0:
475 val = 0x200; /* 0 dB */
478 val = 0x16a; /* -3 dB */
481 val = 0x101; /* -6 dB */
484 val = 0xb6; /* -9 dB */
504 val = 0x09280000;
506 val = 0x08a60000;
508 val = 0x08a40000;
510 val = 0x08240000;
512 val = 0x12d40000;
514 rtwn_bb_setbits(sc, R12A_FC_AREA, 0x1ffe0000, val);
516 for (i = 0; i < sc->nrxchains; i++) {
518 val = 0x10100;
520 val = 0x30100;
522 val = 0x50100;
524 val = 0x00000;
526 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0x70300, val);
531 KASSERT(chan <= 0xff, ("%s: chan %d\n", __func__, chan));
532 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xff, chan);
536 uint8_t ext20 = 0, ext40 = 0;
560 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0x100);
566 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300202);
569 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000);
583 if (rtwn_read_1(sc, 0x837) & 0x04)
584 val = 0x01400000;
586 val = 0x01800000;
588 val = 0x01c00000;
590 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
592 val = 0x0;
603 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80);
606 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300201);
607 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);
618 if (rtwn_read_1(sc, 0x837) & 0x04)
619 val = 0x01800000;
621 val = 0x01c00000;
623 val = 0x02000000;
625 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
628 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 0);
630 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0, 0x10);
632 val = 0x400;
634 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0);
637 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300200);
638 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);
641 val = 0x01c00000;
643 val = 0x02000000;
645 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
647 val = 0xc00;
653 for (i = 0; i < sc->nrxchains; i++)
654 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xc00, val);
667 0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM);
669 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x02, 0x01);
670 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2e000);
673 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0);
676 case 0:
679 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);
680 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
681 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);
682 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
685 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337770);
686 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337770);
687 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
688 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
689 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);
692 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);
693 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
694 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x00100000);
695 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x00100000);
698 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x77);
699 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
700 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0x01, 0);
701 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
707 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10);
708 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000);
713 rtwn_write_1(sc, R12A_CCK_CHECK, 0);
724 for (ntries = 0; ntries < 100; ntries++) {
725 if ((rtwn_read_2(sc, R12A_TXPKT_EMPTY) & 0x30) == 0x30)
740 rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x01, 0x02);
741 rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2a000);
744 rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0x01);
747 case 0:
748 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);
749 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);
750 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
751 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
754 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);
755 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);
756 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);
757 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
761 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337777);
762 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);
763 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
764 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
767 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337717);
768 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337717);
769 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
770 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
771 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);
774 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x33);
775 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);
776 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0, 0x01);
777 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
783 rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0);
784 rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000);