Lines Matching full:power
58 uint8_t power[RTWN_RIDX_COUNT])
69 power[RTWN_RIDX_CCK1],
70 power[RTWN_RIDX_CCK2],
71 power[RTWN_RIDX_CCK55],
72 power[RTWN_RIDX_CCK11]);
78 power[RTWN_RIDX_OFDM6],
79 power[RTWN_RIDX_OFDM9],
80 power[RTWN_RIDX_OFDM12],
81 power[RTWN_RIDX_OFDM18],
82 power[RTWN_RIDX_OFDM24],
83 power[RTWN_RIDX_OFDM36],
84 power[RTWN_RIDX_OFDM48],
85 power[RTWN_RIDX_OFDM54]);
93 power[RTWN_RIDX_HT_MCS(i * 8 + 0)],
94 power[RTWN_RIDX_HT_MCS(i * 8 + 1)],
95 power[RTWN_RIDX_HT_MCS(i * 8 + 2)],
96 power[RTWN_RIDX_HT_MCS(i * 8 + 3)],
97 power[RTWN_RIDX_HT_MCS(i * 8 + 4)],
98 power[RTWN_RIDX_HT_MCS(i * 8 + 5)],
99 power[RTWN_RIDX_HT_MCS(i * 8 + 6)],
100 power[RTWN_RIDX_HT_MCS(i * 8 + 7)]);
132 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
152 * target power in dBm.
160 power[ridx] = base[chain].pwr[0][ridx];
164 power[ridx] = base[chain].pwr[0][ridx];
170 if (power[ridx] > max)
171 power[ridx] = max;
174 power[ridx] = base[chain].pwr[group][ridx];
176 power[ridx] = base[chain].pwr[0][ridx];
179 /* Compute per-CCK rate Tx power. */
181 power[ridx] += rt->cck_tx_pwr[chain][group];
190 /* Compute per-OFDM rate Tx power. */
194 power[ridx] += ofdmpow;
196 /* Compute per-MCS Tx power. */
202 power[ridx] += htpow;
206 if (power[ridx] > R92C_MAX_TX_PWR)
207 power[ridx] = R92C_MAX_TX_PWR;
209 if (power[ridx] > ic->ic_txpowlimit)
210 power[ridx] = ic->ic_txpowlimit;
217 uint8_t power[RTWN_RIDX_COUNT])
221 /* Write per-CCK rate Tx power. */
224 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]);
227 reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]);
228 reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_RIDX_CCK55]);
229 reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_RIDX_CCK11]);
233 reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_RIDX_CCK1]);
234 reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_RIDX_CCK2]);
235 reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_RIDX_CCK55]);
238 reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_RIDX_CCK11]);
241 /* Write per-OFDM rate Tx power. */
243 SM(R92C_TXAGC_RATE06, power[RTWN_RIDX_OFDM6]) |
244 SM(R92C_TXAGC_RATE09, power[RTWN_RIDX_OFDM9]) |
245 SM(R92C_TXAGC_RATE12, power[RTWN_RIDX_OFDM12]) |
246 SM(R92C_TXAGC_RATE18, power[RTWN_RIDX_OFDM18]));
248 SM(R92C_TXAGC_RATE24, power[RTWN_RIDX_OFDM24]) |
249 SM(R92C_TXAGC_RATE36, power[RTWN_RIDX_OFDM36]) |
250 SM(R92C_TXAGC_RATE48, power[RTWN_RIDX_OFDM48]) |
251 SM(R92C_TXAGC_RATE54, power[RTWN_RIDX_OFDM54]));
252 /* Write per-MCS Tx power. */
254 SM(R92C_TXAGC_MCS00, power[RTWN_RIDX_HT_MCS(0)]) |
255 SM(R92C_TXAGC_MCS01, power[RTWN_RIDX_HT_MCS(1)]) |
256 SM(R92C_TXAGC_MCS02, power[RTWN_RIDX_HT_MCS(2)]) |
257 SM(R92C_TXAGC_MCS03, power[RTWN_RIDX_HT_MCS(3)]));
259 SM(R92C_TXAGC_MCS04, power[RTWN_RIDX_HT_MCS(4)]) |
260 SM(R92C_TXAGC_MCS05, power[RTWN_RIDX_HT_MCS(5)]) |
261 SM(R92C_TXAGC_MCS06, power[RTWN_RIDX_HT_MCS(6)]) |
262 SM(R92C_TXAGC_MCS07, power[RTWN_RIDX_HT_MCS(7)]));
265 SM(R92C_TXAGC_MCS08, power[RTWN_RIDX_HT_MCS(8)]) |
266 SM(R92C_TXAGC_MCS09, power[RTWN_RIDX_HT_MCS(9)]) |
267 SM(R92C_TXAGC_MCS10, power[RTWN_RIDX_HT_MCS(10)]) |
268 SM(R92C_TXAGC_MCS11, power[RTWN_RIDX_HT_MCS(11)]));
270 SM(R92C_TXAGC_MCS12, power[RTWN_RIDX_HT_MCS(12)]) |
271 SM(R92C_TXAGC_MCS13, power[RTWN_RIDX_HT_MCS(13)]) |
272 SM(R92C_TXAGC_MCS14, power[RTWN_RIDX_HT_MCS(14)]) |
273 SM(R92C_TXAGC_MCS15, power[RTWN_RIDX_HT_MCS(15)]));
280 uint8_t power[RTWN_RIDX_COUNT];
284 memset(power, 0, sizeof(power));
285 /* Compute per-rate Tx power values. */
286 rtwn_r92c_get_txpower(sc, i, c, power);
287 /* Optionally print out the power table */
288 r92c_dump_txpower(sc, i, power);
289 /* Write per-rate Tx power values to hardware. */
290 r92c_write_txpower(sc, i, power);
295 * Only reconfigure the transmit power if there's a valid BSS node and
297 * configure the transmit power.
369 /* Set Tx power for this new channel. */