Lines Matching +full:realtek +full:- +full:mdio
1 /*-
16 * 4. Neither the name of the author nor the names of any co-contributors
35 * RealTek 8129/8139 PCI NIC driver
38 * the RealTek chipset. Datasheets can be obtained from
39 * www.realtek.com.tw.
46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
50 * gains that bus-master DMA usually offers.
54 * on a longword (32-bit) boundary. This means we almost always have to
57 * is 32-bit aligned within the mbuf's data area. The presence of only
72 * On the bright side, the 8139 does have a built-in PHY, although
73 * rather than using an MDIO serial interface like most other NICs, the
75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
79 * chip. The 8129 has a serial MDIO interface for accessing the MII where
80 * the 8139 lets you directly access the on-board PHY registers. We need
135 "RealTek 8129 10/100BaseTX" },
137 "RealTek 8139 10/100BaseTX" },
139 "RealTek 8139 10/100BaseTX" },
141 "RealTek 8139 10/100BaseTX CardBus" },
143 "RealTek 8100 10/100BaseTX" },
151 "D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
153 "D-Link DFE-530TX+ 10/100BaseTX" },
155 "D-Link DFE-690TXD 10/100BaseTX" },
159 "Corega FEther CB-TXD" },
161 "Corega FEtherII CB-TXD" },
163 "Peppercon AG ROL-F" },
165 "Planex FNW-3603-TX" },
167 "Planex FNW-3800-TX" },
169 "Compaq HNE-300" },
171 "LevelOne FPC-0106TX" },
173 "Edimax EP-4103DL CardBus" }
217 * MII bit-bang glue
259 nitems(rl_devs) - 1);
279 d = addr | sc->rl_eecmd_read;
355 * Read the MII serial port for the MII bit-bang module.
373 * Write the MII serial port for the MII bit-bang module.
395 if (sc->rl_type == RL_8139) {
424 device_printf(sc->rl_dev, "bad phy register\n");
441 if (sc->rl_type == RL_8139) {
463 device_printf(sc->rl_dev, "bad phy register\n");
483 mii = device_get_softc(sc->rl_miibus);
484 ifp = sc->rl_ifp;
489 sc->rl_flags &= ~RL_FLAG_LINK;
490 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
492 switch (IFM_SUBTYPE(mii->mii_media_active)) {
495 sc->rl_flags |= RL_FLAG_LINK;
502 * RealTek controllers do not provide any interface to
503 * Tx/Rx MACs for resolved speed, duplex and flow-control
518 hashes[1] |= (1 << (h - 32));
524 * Program the 64-bit multicast hash filter.
529 if_t ifp = sc->rl_ifp;
576 device_printf(sc->rl_dev, "reset never completed!\n");
580 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
602 if (vendor == t->rl_vid && devid == t->rl_did) {
603 device_set_desc(dev, t->rl_name);
626 ctx->rl_busaddr = segs[0].ds_addr;
650 sc->rl_dev = dev;
652 sc->rl_twister_enable = 0;
654 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
655 ctx = device_get_sysctl_ctx(sc->rl_dev);
656 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
658 &sc->rl_twister_enable, 0, "");
660 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
662 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
672 * crummy design/construction on the part of RealTek. Memory
679 sc->rl_res_id = PCIR_BAR(0);
680 sc->rl_res_type = SYS_RES_IOPORT;
681 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
682 &sc->rl_res_id, RF_ACTIVE);
684 if (prefer_iomap == 0 || sc->rl_res == NULL) {
685 sc->rl_res_id = PCIR_BAR(1);
686 sc->rl_res_type = SYS_RES_MEMORY;
687 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
688 &sc->rl_res_id, RF_ACTIVE);
690 if (sc->rl_res == NULL) {
698 * Detect the Realtek 8139B. For some reason, this chip is very
703 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
705 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
708 sc->rl_btag = rman_get_bustag(sc->rl_res);
709 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
713 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
716 if (sc->rl_irq[0] == NULL) {
722 sc->rl_cfg0 = RL_8139_CFG0;
723 sc->rl_cfg1 = RL_8139_CFG1;
724 sc->rl_cfg2 = 0;
725 sc->rl_cfg3 = RL_8139_CFG3;
726 sc->rl_cfg4 = RL_8139_CFG4;
727 sc->rl_cfg5 = RL_8139_CFG5;
737 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
740 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
758 sc->rl_type = 0;
759 while(t->rl_name != NULL) {
760 if (rl_did == t->rl_did) {
761 sc->rl_type = t->rl_basetype;
767 if (sc->rl_type == 0) {
770 sc->rl_type = RL_8139;
782 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
788 if (sc->rl_type == RL_8139)
790 error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd,
806 if (sc->rl_type == RL_8139 &&
807 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
838 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
839 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
841 device_printf(sc->rl_dev, "couldn't set up irq\n");
866 ifp = sc->rl_ifp;
868 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
879 callout_drain(&sc->rl_stat_callout);
883 sc->suspended = 1;
887 if (sc->rl_intrhand[0])
888 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
889 if (sc->rl_irq[0])
890 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
891 if (sc->rl_res)
892 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
893 sc->rl_res);
900 mtx_destroy(&sc->rl_mtx);
914 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
923 &sc->rl_parent_tag);
925 device_printf(sc->rl_dev,
930 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
939 &sc->rl_cdata.rl_rx_tag);
941 device_printf(sc->rl_dev,
946 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
955 &sc->rl_cdata.rl_tx_tag);
957 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
964 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
965 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
966 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
968 device_printf(sc->rl_dev,
973 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
974 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
978 device_printf(sc->rl_dev,
982 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
986 sc->rl_cdata.rl_tx_chain[i] = NULL;
987 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
988 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
989 &sc->rl_cdata.rl_tx_dmamap[i]);
991 device_printf(sc->rl_dev,
998 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
999 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1011 if (sc->rl_cdata.rl_rx_tag != NULL) {
1012 if (sc->rl_cdata.rl_rx_buf_paddr != 0)
1013 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1014 sc->rl_cdata.rl_rx_dmamap);
1015 if (sc->rl_cdata.rl_rx_buf_ptr != NULL)
1016 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1017 sc->rl_cdata.rl_rx_buf_ptr,
1018 sc->rl_cdata.rl_rx_dmamap);
1019 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1020 sc->rl_cdata.rl_rx_buf = NULL;
1021 sc->rl_cdata.rl_rx_buf_paddr = 0;
1022 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1023 sc->rl_cdata.rl_tx_tag = NULL;
1027 if (sc->rl_cdata.rl_tx_tag != NULL) {
1029 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1031 sc->rl_cdata.rl_tx_tag,
1032 sc->rl_cdata.rl_tx_dmamap[i]);
1033 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1036 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1037 sc->rl_cdata.rl_tx_tag = NULL;
1040 if (sc->rl_parent_tag != NULL) {
1041 bus_dma_tag_destroy(sc->rl_parent_tag);
1042 sc->rl_parent_tag = NULL;
1057 cd = &sc->rl_cdata;
1059 cd->rl_tx_chain[i] = NULL;
1064 sc->rl_cdata.cur_tx = 0;
1065 sc->rl_cdata.last_tx = 0;
1076 bzero(sc->rl_cdata.rl_rx_buf_ptr,
1078 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1088 * You know there's something wrong with a PCI bus-master chip design
1095 * is preceded by a 32-bit RX status word which specifies the length
1097 * the status word) is also 32-bit aligned. The frame length is in the
1102 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1109 if_t ifp = sc->rl_ifp;
1121 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1130 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1132 max_bytes = limit - cur_rx;
1137 if (sc->rxcycles <= 0)
1139 sc->rxcycles--;
1142 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1147 * RealTek chip is in the process of copying a packet into
1151 * RealTek should be shot for this.
1170 * XXX The RealTek chip includes the CRC with every
1176 total_len -= ETHER_CRC_LEN;
1185 rxbufpos = sc->rl_cdata.rl_rx_buf +
1187 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1188 rxbufpos = sc->rl_cdata.rl_rx_buf;
1190 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1195 m_copyback(m, wrap, total_len - wrap,
1196 sc->rl_cdata.rl_rx_buf);
1197 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1204 /* Round up to 32-bit boundary. */
1206 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1231 if_t ifp = sc->rl_ifp;
1250 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1252 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1261 (sc->rl_txthresh < 2016))
1262 sc->rl_txthresh += 32;
1271 oldthresh = sc->rl_txthresh;
1276 sc->rl_txthresh = oldthresh;
1279 RL_INC(sc->rl_cdata.last_tx);
1281 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1284 sc->rl_watchdog_timer = 0;
1292 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
1303 * Tune the so-called twister registers of the RTL8139. These
1308 switch (sc->rl_twister)
1318 sc->rl_twister = FIND_ROW;
1324 sc->rl_twister = DONE;
1334 sc->rl_twist_row = 3;
1336 sc->rl_twist_row = 2;
1338 sc->rl_twist_row = 1;
1340 sc->rl_twist_row = 0;
1341 sc->rl_twist_col = 0;
1342 sc->rl_twister = SET_PARAM;
1345 if (sc->rl_twist_col == 0)
1348 param[sc->rl_twist_row][sc->rl_twist_col]);
1349 if (++sc->rl_twist_col == 4) {
1350 if (sc->rl_twist_row == 3)
1351 sc->rl_twister = RECHK_LONG;
1353 sc->rl_twister = DONE;
1363 sc->rl_twister = DONE;
1366 sc->rl_twister = RETUNE;
1375 sc->rl_twist_row--;
1376 sc->rl_twist_col = 0;
1377 sc->rl_twister = SET_PARAM;
1396 * watchdog timeouts. This is a no-op in normal operations, but
1405 mii = device_get_softc(sc->rl_miibus);
1407 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1408 rl_miibus_statchg(sc->rl_dev);
1409 if (sc->rl_twister_enable) {
1410 if (sc->rl_twister == DONE)
1414 if (sc->rl_twister == DONE)
1423 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
1448 sc->rxcycles = count;
1480 if_t ifp = sc->rl_ifp;
1486 if (sc->suspended)
1503 for (count = 16; count > 0; count--) {
1549 * Hardware doesn't auto-pad, so we have to make sure
1552 if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1553 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1555 * The RealTek is brain damaged and wants longword-aligned
1559 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1572 * Make security-conscious people happy: zero out the
1577 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1578 m->m_pkthdr.len += padlen;
1579 m->m_len = m->m_pkthdr.len;
1582 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1593 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1622 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1644 RL_TXTHRESH(sc->rl_txthresh) |
1645 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1647 RL_INC(sc->rl_cdata.cur_tx);
1650 sc->rl_watchdog_timer = 5;
1675 if_t ifp = sc->rl_ifp;
1681 mii = device_get_softc(sc->rl_miibus);
1692 if (sc->rl_twister_enable) {
1699 sc->rl_twister = CHK_LINK;
1709 bcopy(if_getlladdr(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1715 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1746 sc->rl_txthresh = RL_TX_THRESH_INIT;
1754 sc->rl_flags &= ~RL_FLAG_LINK;
1757 CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1762 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1774 mii = device_get_softc(sc->rl_miibus);
1792 mii = device_get_softc(sc->rl_miibus);
1796 ifmr->ifm_active = mii->mii_media_active;
1797 ifmr->ifm_status = mii->mii_media_status;
1814 ((if_getflags(ifp) ^ sc->rl_if_flags) &
1821 sc->rl_if_flags = if_getflags(ifp);
1832 mii = device_get_softc(sc->rl_miibus);
1833 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1836 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1838 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1851 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1886 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1889 device_printf(sc->rl_dev, "watchdog timeout\n");
1890 if_inc_counter(sc->rl_ifp, IFCOUNTER_OERRORS, 1);
1894 if_setdrvflagbits(sc->rl_ifp, 0, IFF_DRV_RUNNING);
1906 if_t ifp = sc->rl_ifp;
1910 sc->rl_watchdog_timer = 0;
1911 callout_stop(&sc->rl_stat_callout);
1913 sc->rl_flags &= ~RL_FLAG_LINK;
1924 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
1930 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1931 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
1932 sc->rl_cdata.rl_tx_dmamap[i],
1934 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1935 sc->rl_cdata.rl_tx_dmamap[i]);
1936 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1937 sc->rl_cdata.rl_tx_chain[i] = NULL;
1959 sc->suspended = 1;
1967 * doesn't, re-enable busmastering, and restart the interface if
1979 ifp = sc->rl_ifp;
1984 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
1986 pmstat = pci_read_config(sc->rl_dev,
1990 pci_write_config(sc->rl_dev,
2004 sc->suspended = 0;
2029 if_setflagbits(sc->rl_ifp, 0, IFF_UP);
2046 ifp = sc->rl_ifp;
2049 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
2056 v = CSR_READ_1(sc, sc->rl_cfg1);
2060 CSR_WRITE_1(sc, sc->rl_cfg1, v);
2062 v = CSR_READ_1(sc, sc->rl_cfg3);
2066 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2068 v = CSR_READ_1(sc, sc->rl_cfg5);
2077 CSR_WRITE_1(sc, sc->rl_cfg5, v);
2083 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
2087 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2096 ifp = sc->rl_ifp;
2103 v = CSR_READ_1(sc, sc->rl_cfg3);
2105 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2110 v = CSR_READ_1(sc, sc->rl_cfg5);
2113 CSR_WRITE_1(sc, sc->rl_cfg5, v);