Lines Matching +full:read +full:- +full:strobe +full:- +full:delay
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998-2003
18 * 4. Neither the name of the author nor the names of any co-contributors
59 * o 64-bit DMA
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
178 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
180 "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
192 "TP-Link TG-3468 v2 (RTL8168) Gigabit Ethernet" },
196 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
198 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
208 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
243 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
366 * Send a read command and address to the EEPROM, check for ACK.
373 d = addr | (RL_9346_READ << sc->rl_eewidth);
376 * Feed in each bit and strobe the clock.
379 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
385 DELAY(100);
387 DELAY(150);
389 DELAY(100);
394 * Read a word of data stored in the EEPROM at address 'addr.'
403 * Send address of word we want to read.
412 DELAY(100);
416 DELAY(100);
423 * Read a sequence of words from the EEPROM.
433 DELAY(100);
455 /* Let the rgephy driver read the GMEDIASTAT register */
468 DELAY(25);
472 device_printf(sc->rl_dev, "PHY read failed\n");
477 * Controller requires a 20us delay to process next MDIO request.
479 DELAY(20);
500 DELAY(25);
504 device_printf(sc->rl_dev, "PHY write failed\n");
509 * Controller requires a 20us delay to process next MDIO request.
511 DELAY(20);
525 if (sc->rl_type == RL_8169) {
550 * Allow the rlphy driver to read the media status
559 device_printf(sc->rl_dev, "bad phy register\n");
563 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
579 if (sc->rl_type == RL_8169) {
587 if (sc->rl_type == RL_8139CPLUS) {
609 device_printf(sc->rl_dev, "bad phy register\n");
624 mii = device_get_softc(sc->rl_miibus);
625 ifp = sc->rl_ifp;
630 sc->rl_flags &= ~RL_FLAG_LINK;
631 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
633 switch (IFM_SUBTYPE(mii->mii_media_active)) {
636 sc->rl_flags |= RL_FLAG_LINK;
639 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
641 sc->rl_flags |= RL_FLAG_LINK;
649 * MACs for resolved speed, duplex and flow-control parameters.
662 hashes[1] |= (1 << (h - 32));
668 * Set the RX configuration and 64-bit multicast hash filter.
679 ifp = sc->rl_ifp;
682 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0)
684 else if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0)
710 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
718 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) {
740 DELAY(10);
745 device_printf(sc->rl_dev, "reset never completed!\n");
747 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
749 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
750 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
757 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
758 * lines connected to the bus, however for a 32-bit only card, they
760 * NIC will not work right if you plug it into a 64-bit slot: DMA
761 * operations will be done with 64-bit transfers, which will fail
762 * because the 64-bit data lines aren't connected.
770 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
778 if_t ifp = sc->rl_ifp;
799 * - Puts receiver in promiscuous mode
800 * - Enables digital loopback mode
801 * - Leaves interrupts turned off
805 sc->rl_testmode = 1;
808 sc->rl_flags |= RL_FLAG_LINK;
809 if (sc->rl_type == RL_8169)
814 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
816 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
821 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
824 DELAY(100000);
829 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
830 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
831 eh->ether_type = htons(ETHERTYPE_IP);
832 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
848 DELAY(100000);
855 DELAY(10);
859 device_printf(sc->rl_dev,
871 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
872 sc->rl_ldata.rl_rx_list_map,
874 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
875 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
877 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
878 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
880 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
881 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
884 cur_rx = &sc->rl_ldata.rl_rx_list[0];
886 rxstat = le32toh(cur_rx->rl_cmdstat);
889 device_printf(sc->rl_dev,
897 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
898 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
899 ntohs(eh->ether_type) != ETHERTYPE_IP) {
900 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
901 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
903 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
904 eh->ether_dhost, ":", eh->ether_shost, ":",
905 ntohs(eh->ether_type));
906 device_printf(sc->rl_dev, "You may have a defective 32-bit "
907 "NIC plugged into a 64-bit PCI slot.\n");
908 device_printf(sc->rl_dev, "Please re-install the NIC in a "
909 "32-bit slot for proper operation.\n");
910 device_printf(sc->rl_dev, "Read the re(4) man page for more "
918 sc->rl_testmode = 0;
919 sc->rl_flags &= ~RL_FLAG_LINK;
968 if (vendor == t->rl_vid && devid == t->rl_did) {
969 device_set_desc(dev, t->rl_name);
991 *addr = segs->ds_addr;
1002 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
1003 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
1014 if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
1019 NULL, NULL, &sc->rl_parent_tag);
1028 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
1031 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1041 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1042 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
1045 &sc->rl_ldata.rl_jrx_mtag);
1052 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1054 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1063 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1066 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1074 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1075 (void **)&sc->rl_ldata.rl_tx_list,
1077 &sc->rl_ldata.rl_tx_list_map);
1085 sc->rl_ldata.rl_tx_list_addr = 0;
1086 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1087 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1089 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1090 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1097 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1098 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1099 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1109 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1112 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1120 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1121 (void **)&sc->rl_ldata.rl_rx_list,
1123 &sc->rl_ldata.rl_rx_list_map);
1131 sc->rl_ldata.rl_rx_list_addr = 0;
1132 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1133 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1135 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1136 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1143 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1144 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1145 &sc->rl_ldata.rl_jrx_sparemap);
1151 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1152 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1153 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1161 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1162 &sc->rl_ldata.rl_rx_sparemap);
1167 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1168 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1169 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1177 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1180 &sc->rl_ldata.rl_stag);
1186 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1187 (void **)&sc->rl_ldata.rl_stats,
1189 &sc->rl_ldata.rl_smap);
1196 sc->rl_ldata.rl_stats_addr = 0;
1197 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1198 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1199 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1200 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1227 sc->rl_dev = dev;
1229 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1231 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1247 sc->rl_res_id = PCIR_BAR(1);
1248 sc->rl_res_type = SYS_RES_MEMORY;
1251 sc->rl_res_id = PCIR_BAR(2);
1253 sc->rl_res_id = PCIR_BAR(0);
1254 sc->rl_res_type = SYS_RES_IOPORT;
1256 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1257 &sc->rl_res_id, RF_ACTIVE);
1258 if (sc->rl_res == NULL && prefer_iomap == 0) {
1259 sc->rl_res_id = PCIR_BAR(0);
1260 sc->rl_res_type = SYS_RES_IOPORT;
1261 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1262 &sc->rl_res_id, RF_ACTIVE);
1264 if (sc->rl_res == NULL) {
1270 sc->rl_btag = rman_get_bustag(sc->rl_res);
1271 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1276 sc->rl_flags |= RL_FLAG_PCIE;
1277 sc->rl_expcap = reg;
1281 device_printf(dev, "MSI-X count : %d\n", msixc);
1287 /* Prefer MSI-X to MSI. */
1291 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1293 if (sc->rl_res_pba == NULL) {
1294 device_printf(sc->rl_dev,
1295 "could not allocate MSI-X PBA resource\n");
1297 if (sc->rl_res_pba != NULL &&
1300 device_printf(dev, "Using %d MSI-X message\n",
1302 sc->rl_flags |= RL_FLAG_MSIX;
1306 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
1307 if (sc->rl_res_pba != NULL)
1309 sc->rl_res_pba);
1310 sc->rl_res_pba = NULL;
1321 sc->rl_flags |= RL_FLAG_MSI;
1331 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1336 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
1338 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1340 if (sc->rl_irq[0] == NULL) {
1347 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1349 if (sc->rl_irq[i] == NULL) {
1359 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1371 if (sc->rl_expcap != 0) {
1372 cap = pci_read_config(dev, sc->rl_expcap +
1375 ctl = pci_read_config(dev, sc->rl_expcap +
1381 pci_write_config(dev, sc->rl_expcap +
1399 sc->rl_macrev = hwrev & 0x00700000;
1403 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev);
1404 while (hw_rev->rl_desc != NULL) {
1405 if (hw_rev->rl_rev == hwrev) {
1406 sc->rl_type = hw_rev->rl_type;
1407 sc->rl_hwrev = hw_rev;
1412 if (hw_rev->rl_desc == NULL) {
1418 switch (hw_rev->rl_rev) {
1420 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1424 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1429 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1434 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1442 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1447 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1454 sc->rl_flags |= RL_FLAG_WOLRXENB;
1457 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1460 sc->rl_flags |= RL_FLAG_MACSLEEP;
1463 if (sc->rl_macrev == 0x00200000)
1464 sc->rl_flags |= RL_FLAG_MACSLEEP;
1467 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1472 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1478 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1483 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1490 sc->rl_flags |= RL_FLAG_EARLYOFF;
1493 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1502 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1512 sc->rl_flags |= RL_FLAG_FASTETHER;
1514 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1516 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1525 sc->rl_flags |= RL_FLAG_PHYWAKE;
1530 sc->rl_flags |= RL_FLAG_MACRESET;
1536 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
1537 sc->rl_cfg0 = RL_8139_CFG0;
1538 sc->rl_cfg1 = RL_8139_CFG1;
1539 sc->rl_cfg2 = 0;
1540 sc->rl_cfg3 = RL_8139_CFG3;
1541 sc->rl_cfg4 = RL_8139_CFG4;
1542 sc->rl_cfg5 = RL_8139_CFG5;
1544 sc->rl_cfg0 = RL_CFG0;
1545 sc->rl_cfg1 = RL_CFG1;
1546 sc->rl_cfg2 = RL_CFG2;
1547 sc->rl_cfg3 = RL_CFG3;
1548 sc->rl_cfg4 = RL_CFG4;
1549 sc->rl_cfg5 = RL_CFG5;
1559 cfg = CSR_READ_1(sc, sc->rl_cfg1);
1561 CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
1562 cfg = CSR_READ_1(sc, sc->rl_cfg5);
1564 CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
1567 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1575 sc->rl_eewidth = RL_9356_ADDR_LEN;
1578 sc->rl_eewidth = RL_9346_ADDR_LEN;
1589 if (sc->rl_type == RL_8169) {
1591 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1592 sc->rl_txstart = RL_GTXSTART;
1593 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1594 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1597 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1598 sc->rl_txstart = RL_TXSTART;
1599 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1600 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1608 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1611 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1621 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1623 if (hw_rev->rl_rev == RL_HWREV_8401E)
1626 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1640 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
1641 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
1642 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) {
1655 NET_TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1661 if (sc->rl_type == RL_8169)
1664 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
1666 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1688 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0)
1716 * Some 32-bit cards were incorrectly wired and would
1717 * malfunction if plugged into a 64-bit slot.
1734 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1736 error = bus_setup_intr(dev, sc->rl_irq[0],
1738 &sc->rl_intrhand[0]);
1740 error = bus_setup_intr(dev, sc->rl_irq[0],
1742 &sc->rl_intrhand[0]);
1774 ifp = sc->rl_ifp;
1775 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1785 sc->suspended = 1;
1789 callout_drain(&sc->rl_stat_callout);
1790 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1813 if (sc->rl_intrhand[0] != NULL) {
1814 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1815 sc->rl_intrhand[0] = NULL;
1823 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1827 if (sc->rl_irq[0] != NULL) {
1828 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
1829 sc->rl_irq[0] = NULL;
1831 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
1833 if (sc->rl_res_pba) {
1835 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
1837 if (sc->rl_res)
1838 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1839 sc->rl_res);
1843 if (sc->rl_ldata.rl_rx_list_tag) {
1844 if (sc->rl_ldata.rl_rx_list_addr)
1845 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1846 sc->rl_ldata.rl_rx_list_map);
1847 if (sc->rl_ldata.rl_rx_list)
1848 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1849 sc->rl_ldata.rl_rx_list,
1850 sc->rl_ldata.rl_rx_list_map);
1851 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1856 if (sc->rl_ldata.rl_tx_list_tag) {
1857 if (sc->rl_ldata.rl_tx_list_addr)
1858 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1859 sc->rl_ldata.rl_tx_list_map);
1860 if (sc->rl_ldata.rl_tx_list)
1861 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1862 sc->rl_ldata.rl_tx_list,
1863 sc->rl_ldata.rl_tx_list_map);
1864 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1869 if (sc->rl_ldata.rl_tx_mtag) {
1870 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1871 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1872 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1873 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1875 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1877 if (sc->rl_ldata.rl_rx_mtag) {
1878 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1879 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1880 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1881 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1883 if (sc->rl_ldata.rl_rx_sparemap)
1884 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1885 sc->rl_ldata.rl_rx_sparemap);
1886 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1888 if (sc->rl_ldata.rl_jrx_mtag) {
1889 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1890 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
1891 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1892 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1894 if (sc->rl_ldata.rl_jrx_sparemap)
1895 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1896 sc->rl_ldata.rl_jrx_sparemap);
1897 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
1901 if (sc->rl_ldata.rl_stag) {
1902 if (sc->rl_ldata.rl_stats_addr)
1903 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1904 sc->rl_ldata.rl_smap);
1905 if (sc->rl_ldata.rl_stats)
1906 bus_dmamem_free(sc->rl_ldata.rl_stag,
1907 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1908 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1911 if (sc->rl_parent_tag)
1912 bus_dma_tag_destroy(sc->rl_parent_tag);
1914 mtx_destroy(&sc->rl_mtx);
1926 if (if_getmtu(sc->rl_ifp) > RL_MTU &&
1927 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
1928 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1930 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1931 desc = &sc->rl_ldata.rl_rx_list[idx];
1932 desc->rl_vlanctl = 0;
1933 cmdstat = rxd->rx_size;
1934 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1936 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1954 m->m_len = m->m_pkthdr.len = MCLBYTES;
1957 * This is part of an evil trick to deal with non-x86 platforms.
1958 * The RealTek chip requires RX buffers to be aligned on 64-bit
1959 * boundaries, but that will hose non-x86 machines. To get around
1961 * and for non-x86 hosts, we copy the buffer back six bytes
1968 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1969 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1976 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1977 if (rxd->rx_m != NULL) {
1978 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1980 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1983 rxd->rx_m = m;
1984 map = rxd->rx_dmamap;
1985 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1986 rxd->rx_size = segs[0].ds_len;
1987 sc->rl_ldata.rl_rx_sparemap = map;
1988 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1991 desc = &sc->rl_ldata.rl_rx_list[idx];
1992 desc->rl_vlanctl = 0;
1993 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1994 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1996 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1998 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
2017 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
2021 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
2022 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
2029 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
2030 if (rxd->rx_m != NULL) {
2031 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
2033 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
2036 rxd->rx_m = m;
2037 map = rxd->rx_dmamap;
2038 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
2039 rxd->rx_size = segs[0].ds_len;
2040 sc->rl_ldata.rl_jrx_sparemap = map;
2041 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
2044 desc = &sc->rl_ldata.rl_rx_list[idx];
2045 desc->rl_vlanctl = 0;
2046 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
2047 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
2049 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
2051 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
2064 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
2066 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2069 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
2081 bzero(sc->rl_ldata.rl_tx_list,
2082 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
2083 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
2084 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
2089 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
2090 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
2092 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2093 sc->rl_ldata.rl_tx_list_map,
2096 sc->rl_ldata.rl_tx_prodidx = 0;
2097 sc->rl_ldata.rl_tx_considx = 0;
2098 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
2108 bzero(sc->rl_ldata.rl_rx_list,
2109 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2110 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2111 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
2121 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2122 sc->rl_ldata.rl_rx_list_map,
2125 sc->rl_ldata.rl_rx_prodidx = 0;
2126 sc->rl_head = sc->rl_tail = NULL;
2127 sc->rl_int_rx_act = 0;
2137 bzero(sc->rl_ldata.rl_rx_list,
2138 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2139 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2140 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
2145 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2146 sc->rl_ldata.rl_rx_list_map,
2149 sc->rl_ldata.rl_rx_prodidx = 0;
2150 sc->rl_head = sc->rl_tail = NULL;
2151 sc->rl_int_rx_act = 0;
2173 ifp = sc->rl_ifp;
2178 if (if_getmtu(ifp) > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
2185 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2186 sc->rl_ldata.rl_rx_list_map,
2189 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2193 cur_rx = &sc->rl_ldata.rl_rx_list[i];
2194 rxstat = le32toh(cur_rx->rl_cmdstat);
2197 total_len = rxstat & sc->rl_rxlenmask;
2198 rxvlan = le32toh(cur_rx->rl_vlanctl);
2200 m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
2202 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2204 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
2209 * support multi-fragment packet.
2216 * If this is part of a multi-fragment packet,
2219 if (sc->rl_head != NULL) {
2220 m_freem(sc->rl_head);
2221 sc->rl_head = sc->rl_tail = NULL;
2226 m->m_len = RE_RX_DESC_BUFLEN;
2227 if (sc->rl_head == NULL)
2228 sc->rl_head = sc->rl_tail = m;
2230 m->m_flags &= ~M_PKTHDR;
2231 sc->rl_tail->m_next = m;
2232 sc->rl_tail = m;
2253 if (sc->rl_type == RL_8169)
2257 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
2262 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
2269 * If this is part of a multi-fragment packet,
2272 if (sc->rl_head != NULL) {
2273 m_freem(sc->rl_head);
2274 sc->rl_head = sc->rl_tail = NULL;
2291 if (sc->rl_head != NULL) {
2292 m_freem(sc->rl_head);
2293 sc->rl_head = sc->rl_tail = NULL;
2299 if (sc->rl_head != NULL) {
2301 m->m_len = total_len;
2303 m->m_len = total_len % RE_RX_DESC_BUFLEN;
2304 if (m->m_len == 0)
2305 m->m_len = RE_RX_DESC_BUFLEN;
2313 if (m->m_len <= ETHER_CRC_LEN) {
2314 sc->rl_tail->m_len -=
2315 (ETHER_CRC_LEN - m->m_len);
2318 m->m_len -= ETHER_CRC_LEN;
2319 m->m_flags &= ~M_PKTHDR;
2320 sc->rl_tail->m_next = m;
2322 m = sc->rl_head;
2323 sc->rl_head = sc->rl_tail = NULL;
2324 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2326 m->m_pkthdr.len = m->m_len =
2327 (total_len - ETHER_CRC_LEN);
2333 m->m_pkthdr.rcvif = ifp;
2338 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2341 m->m_pkthdr.csum_flags |=
2344 m->m_pkthdr.csum_flags |=
2352 m->m_pkthdr.csum_flags |=
2354 m->m_pkthdr.csum_data = 0xffff;
2362 m->m_pkthdr.csum_flags |=
2366 m->m_pkthdr.csum_flags |=
2372 m->m_pkthdr.csum_flags |=
2374 m->m_pkthdr.csum_data = 0xffff;
2378 maxpkt--;
2380 m->m_pkthdr.ether_vtag =
2382 m->m_flags |= M_VLANTAG;
2392 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2393 sc->rl_ldata.rl_rx_list_map,
2396 sc->rl_ldata.rl_rx_prodidx = i;
2414 cons = sc->rl_ldata.rl_tx_considx;
2415 if (cons == sc->rl_ldata.rl_tx_prodidx)
2418 ifp = sc->rl_ifp;
2424 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2425 sc->rl_ldata.rl_tx_list_map,
2428 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2430 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2440 txd = &sc->rl_ldata.rl_tx_desc[cons];
2441 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2442 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2443 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2444 txd->tx_dmamap);
2445 KASSERT(txd->tx_m != NULL,
2447 m_freem(txd->tx_m);
2448 txd->tx_m = NULL;
2457 sc->rl_ldata.rl_tx_free++;
2460 sc->rl_ldata.rl_tx_considx = cons;
2464 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2469 * interrupt that will cause us to re-enter this routine.
2475 sc->rl_watchdog_timer = 0;
2488 mii = device_get_softc(sc->rl_miibus);
2490 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2491 re_miibus_statchg(sc->rl_dev);
2500 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2525 sc->rxcycles = count;
2541 (sc->rl_flags & RL_FLAG_PCIE))
2542 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2570 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask);
2584 ifp = sc->rl_ifp;
2591 if (sc->suspended ||
2616 (sc->rl_flags & RL_FLAG_PCIE))
2617 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2638 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask);
2655 ifp = sc->rl_ifp;
2672 if (sc->rl_int_rx_act > 0) {
2683 if (sc->rl_int_rx_mod != 0 &&
2686 /* Rearm one-shot timer. */
2690 sc->rl_int_rx_act = 1;
2694 sc->rl_int_rx_act = 0;
2708 (sc->rl_flags & RL_FLAG_PCIE))
2709 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2753 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2754 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2755 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2756 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2767 if ((*m_head)->m_next != NULL ||
2782 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2783 m_new->m_pkthdr.len += padlen;
2784 m_new->m_len = m_new->m_pkthdr.len;
2788 prod = sc->rl_ldata.rl_tx_prodidx;
2789 txd = &sc->rl_ldata.rl_tx_desc[prod];
2790 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2800 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2801 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2816 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2817 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2821 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2826 * appear in all descriptors of a multi-descriptor transmit
2832 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2833 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2835 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2839 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2848 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2849 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2851 if (((*m_head)->m_pkthdr.csum_flags &
2854 if (((*m_head)->m_pkthdr.csum_flags &
2859 if (((*m_head)->m_pkthdr.csum_flags &
2862 if (((*m_head)->m_pkthdr.csum_flags &
2871 * appear in all descriptors of a multi-descriptor
2874 if ((*m_head)->m_flags & M_VLANTAG)
2875 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2880 desc = &sc->rl_ldata.rl_tx_list[prod];
2881 desc->rl_vlanctl = htole32(vlanctl);
2882 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2883 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2887 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2889 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2890 sc->rl_ldata.rl_tx_free--;
2893 sc->rl_ldata.rl_tx_prodidx = prod;
2897 desc = &sc->rl_ldata.rl_tx_list[ei];
2898 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2900 desc = &sc->rl_ldata.rl_tx_list[si];
2902 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2909 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2910 map = txd->tx_dmamap;
2911 txd->tx_dmamap = txd_last->tx_dmamap;
2912 txd_last->tx_dmamap = map;
2913 txd_last->tx_m = *m_head;
2944 struct netmap_kring *kring = NA(ifp)->tx_rings[0];
2945 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) {
2947 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2951 sc->rl_watchdog_timer = 5;
2958 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2962 sc->rl_ldata.rl_tx_free > 1;) {
2986 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
3000 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
3001 sc->rl_ldata.rl_tx_list_map,
3004 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
3021 sc->rl_watchdog_timer = 5;
3028 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
3029 pci_set_max_read_req(sc->rl_dev, 4096);
3035 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
3037 switch (sc->rl_hwrev->rl_rev) {
3041 CSR_WRITE_1(sc, sc->rl_cfg4,
3042 CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
3045 CSR_WRITE_1(sc, sc->rl_cfg4,
3046 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
3049 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
3051 switch (sc->rl_hwrev->rl_rev) {
3055 CSR_WRITE_1(sc, sc->rl_cfg4,
3056 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
3059 CSR_WRITE_1(sc, sc->rl_cfg4,
3060 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
3065 switch (sc->rl_hwrev->rl_rev) {
3067 pci_set_max_read_req(sc->rl_dev, 4096);
3071 pci_set_max_read_req(sc->rl_dev, 512);
3073 pci_set_max_read_req(sc->rl_dev, 4096);
3090 if_t ifp = sc->rl_ifp;
3098 mii = device_get_softc(sc->rl_miibus);
3114 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3117 device_printf(sc->rl_dev,
3127 device_printf(sc->rl_dev,
3136 device_printf(sc->rl_dev, "no memory for RX buffers\n");
3140 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3141 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
3143 pci_set_max_read_req(sc->rl_dev, 512);
3145 pci_set_max_read_req(sc->rl_dev, 4096);
3160 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
3167 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3168 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3170 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
3172 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3205 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3207 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3210 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3212 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3214 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) {
3221 * Enable transmit and receive for pre-RTL8168G controllers.
3224 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) == 0)
3230 if (sc->rl_testmode) {
3231 if (sc->rl_type == RL_8169)
3248 if (sc->rl_type == RL_8169) {
3257 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0)
3272 if (sc->rl_testmode)
3279 sc->rl_txthresh = RL_TX_THRESH_INIT;
3295 if (sc->rl_type == RL_8169)
3304 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3306 if (sc->rl_type == RL_8169)
3308 RL_USECS(sc->rl_int_rx_mod));
3310 if (sc->rl_type == RL_8169)
3319 if (sc->rl_type == RL_8169) {
3320 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3328 sc->rl_hwrev->rl_max_mtu +
3334 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3335 sc->rl_hwrev->rl_max_mtu == RL_MTU) {
3342 if (sc->rl_testmode)
3345 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
3351 sc->rl_flags &= ~RL_FLAG_LINK;
3354 sc->rl_watchdog_timer = 0;
3355 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3373 mii = device_get_softc(sc->rl_miibus);
3391 mii = device_get_softc(sc->rl_miibus);
3395 ifmr->ifm_active = mii->mii_media_active;
3396 ifmr->ifm_status = mii->mii_media_status;
3410 if (ifr->ifr_mtu < ETHERMIN ||
3411 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu ||
3412 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 &&
3413 ifr->ifr_mtu > RL_MTU)) {
3418 if (if_getmtu(ifp) != ifr->ifr_mtu) {
3419 if_setmtu(ifp, ifr->ifr_mtu);
3420 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3439 if (((if_getflags(ifp) ^ sc->rl_if_flags)
3448 sc->rl_if_flags = if_getflags(ifp);
3460 mii = device_get_softc(sc->rl_miibus);
3461 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3467 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
3471 if (ifr->ifr_reqcap & IFCAP_POLLING) {
3529 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3565 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
3568 ifp = sc->rl_ifp;
3570 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3572 "-- recovering\n");
3602 ifp = sc->rl_ifp;
3604 sc->rl_watchdog_timer = 0;
3605 callout_stop(&sc->rl_stat_callout);
3622 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) {
3628 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3629 for (i = RL_TIMEOUT; i > 0; i--) {
3630 if ((CSR_READ_1(sc, sc->rl_txstart) &
3633 DELAY(20);
3636 device_printf(sc->rl_dev,
3639 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
3642 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
3643 for (i = RL_TIMEOUT; i > 0; i--) {
3647 DELAY(100);
3650 device_printf(sc->rl_dev,
3655 DELAY(1000);
3659 if (sc->rl_head != NULL) {
3660 m_freem(sc->rl_head);
3661 sc->rl_head = sc->rl_tail = NULL;
3665 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3666 txd = &sc->rl_ldata.rl_tx_desc[i];
3667 if (txd->tx_m != NULL) {
3668 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3669 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3670 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3671 txd->tx_dmamap);
3672 m_freem(txd->tx_m);
3673 txd->tx_m = NULL;
3678 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3679 rxd = &sc->rl_ldata.rl_rx_desc[i];
3680 if (rxd->rx_m != NULL) {
3681 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
3682 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3683 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3684 rxd->rx_dmamap);
3685 m_freem(rxd->rx_m);
3686 rxd->rx_m = NULL;
3690 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3691 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3692 rxd = &sc->rl_ldata.rl_jrx_desc[i];
3693 if (rxd->rx_m != NULL) {
3694 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag,
3695 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3696 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag,
3697 rxd->rx_dmamap);
3698 m_freem(rxd->rx_m);
3699 rxd->rx_m = NULL;
3720 sc->suspended = 1;
3728 * doesn't, re-enable busmastering, and restart the interface if
3741 ifp = sc->rl_ifp;
3743 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3759 sc->suspended = 0;
3783 if_setflagbits(sc->rl_ifp, 0, IFF_UP);
3799 mii = device_get_softc(sc->rl_miibus);
3802 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3804 switch IFM_SUBTYPE(mii->mii_media_active) {
3815 miisc = LIST_FIRST(&mii->mii_phys);
3816 phyno = miisc->mii_phy;
3817 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3819 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
3820 re_miibus_writereg(sc->rl_dev, phyno,
3822 re_miibus_writereg(sc->rl_dev, phyno,
3824 DELAY(1000);
3831 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3833 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3846 device_printf(sc->rl_dev,
3850 * No link, force MAC to have 100Mbps, full-duplex link.
3854 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3855 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3868 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3871 ifp = sc->rl_ifp;
3873 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3879 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) {
3885 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
3887 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3894 v = CSR_READ_1(sc, sc->rl_cfg1);
3898 CSR_WRITE_1(sc, sc->rl_cfg1, v);
3900 v = CSR_READ_1(sc, sc->rl_cfg3);
3904 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3906 v = CSR_READ_1(sc, sc->rl_cfg5);
3915 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3921 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3930 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3934 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3945 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3951 v = CSR_READ_1(sc, sc->rl_cfg3);
3953 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3958 v = CSR_READ_1(sc, sc->rl_cfg5);
3961 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3971 ctx = device_get_sysctl_ctx(sc->rl_dev);
3972 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3977 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3982 &sc->rl_int_rx_mod, 0, sysctl_hw_re_int_mod, "I",
3985 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3986 error = resource_int_value(device_get_name(sc->rl_dev),
3987 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3989 if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3990 sc->rl_int_rx_mod > RL_TIMER_MAX) {
3991 device_printf(sc->rl_dev, "int_rx_mod value out of "
3994 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
4006 result = -1;
4008 if (error || req->newptr == NULL)
4014 if ((if_getdrvflags(sc->rl_ifp) & IFF_DRV_RUNNING) == 0) {
4018 bus_dmamap_sync(sc->rl_ldata.rl_stag,
4019 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
4021 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
4023 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
4025 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
4027 for (i = RL_TIMEOUT; i > 0; i--) {
4031 DELAY(1000);
4033 bus_dmamap_sync(sc->rl_ldata.rl_stag,
4034 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
4037 device_printf(sc->rl_dev,
4042 stats = sc->rl_ldata.rl_stats;
4043 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
4045 (uintmax_t)le64toh(stats->rl_tx_pkts));
4047 (uintmax_t)le64toh(stats->rl_rx_pkts));
4049 (uintmax_t)le64toh(stats->rl_tx_errs));
4051 le32toh(stats->rl_rx_errs));
4053 (uint32_t)le16toh(stats->rl_missed_pkts));
4055 (uint32_t)le16toh(stats->rl_rx_framealign_errs));
4057 le32toh(stats->rl_tx_onecoll));
4059 le32toh(stats->rl_tx_multicolls));
4061 (uintmax_t)le64toh(stats->rl_rx_ucasts));
4063 (uintmax_t)le64toh(stats->rl_rx_bcasts));
4065 le32toh(stats->rl_rx_mcasts));
4067 (uint32_t)le16toh(stats->rl_tx_aborts));
4069 (uint32_t)le16toh(stats->rl_rx_underruns));
4084 if (error || req->newptr == NULL)
4109 *nrxr = sc->rl_ldata.rl_rx_desc_cnt;
4112 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) ? MJUM9BYTES : MCLBYTES;
4129 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
4146 (sc->rl_flags & RL_FLAG_LINK) == 0)