Lines Matching defs:qlnxr_device_attr
243 struct qlnxr_device_attr { struct
245 u32 vendor_id;
246 u32 vendor_part_id;
247 u32 hw_ver;
248 u64 fw_ver;
250 u64 node_guid; /* node GUID */
251 u64 sys_image_guid; /* System image GUID */
253 u8 max_cnq;
254 u8 max_sge; /* Maximum # of scatter/gather entries
257 u16 max_inline;
258 u32 max_sqe; /* Maximum number of send outstanding send work
261 u32 max_rqe; /* Maximum number of receive outstanding receive
264 u8 max_qp_resp_rd_atomic_resc; /* Maximum number of RDMA Reads
269 u8 max_qp_req_rd_atomic_resc; /* The maximum depth per QP for
273 u64 max_dev_resp_rd_atomic_resc;
274 u32 max_cq;
275 u32 max_qp;
276 u32 max_mr; /* Maximum # of MRs supported */
277 u64 max_mr_size; /* Size (in bytes) of largest contiguous memory
280 u32 max_cqe;
281 u32 max_mw; /* Maximum # of memory windows supported */
282 u32 max_fmr;
283 u32 max_mr_mw_fmr_pbl;
284 u64 max_mr_mw_fmr_size;
285 u32 max_pd; /* Maximum # of protection domains supported */
286 u32 max_ah;
287 u8 max_pkey;
288 u32 max_srq; /* Maximum number of SRQs */
289 u32 max_srq_wr; /* Maximum number of WRs per SRQ */
290 u8 max_srq_sge; /* Maximum number of SGE per WQE */
291 u8 max_stats_queues; /* Maximum number of statistics queues */
292 u32 dev_caps;
347 u64 page_size_caps;
348 u8 dev_ack_delay;
349 u32 reserved_lkey; /* Value of reserved L_key */
350 u32 bad_pkey_counter;/* Bad P_key counter support
353 struct ecore_rdma_events events;