Lines Matching +full:ras +full:- +full:to +full:- +full:cas
2 * Copyright (c) 2017-2018 Cavium, Inc.
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 … (0x1<<0) // Signals an unknown address to the rf module.
43 … (0x1<<0) // Signals an unknown address to the rf module.
48 … (0x1<<0) // Signals an unknown address to the rf module.
53 … 0x001d14UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
54 … line) in the selected line (before shift).for selecting a line to output
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
83 …uring an EPROM Load, if a value of 0xFFFF is loaded to this field and a value of 0xFFFF is loaded …
85 …to starting the link. _ <15:8> is typically set to the appropriate chip number, from the FUS_FUS…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
93 …by firmware through the PCIE private register space VENDOR_ID to modify this read value to the hos…
102 …to master the bus when this bit is not set, the request is discarded. An interrupt will be generat…
104 … (0x1<<3) // Special cycle enable. Not applicable for PCI Express. Must be hardwired to zero.
106 …(0x1<<4) // Memory write and invalidate. Not applicable for PCI Express. Must be hardwired to zero.
108 … (0x1<<5) // VGA palette snoop. Not applicable for PCI Express. Must be hardwired to zero.
112 …7) // IDSEL stepping/wait cycle control. Not applicable for PCI Express. Must be hardwired to zero.
116 … (0x1<<9) // Fast back-to-back transaction enable. Not applicable for PCI Express. M…
124 …0x1<<20) // Capabilities list. Indicates presence of an extended capability item. Hardwired to one.
126 … (0x1<<21) // 66 MHz capable. Not applicable for PCI Express. Hardwired to zero.
128 … (0x1<<23) // Fast back-to-back capable. Not applicable for PCI Express. Har…
132 … (0x3<<25) // DEVSEL timing. Not applicable for PCI Express. Hardwired to 0x0.
145 …to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0. …
147 …to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0…
173 … (0x1<<23) // Fast Back to Back Transaction Cap…
185 …2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
189 …20 // This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)
194 …int function from issuing memory or IO requests. Also disables the ability to issue MSI messages. …
196 … (0x1<<3) // Does not apply to PCIE Path = i_cfg_fu…
198 … (0x1<<4) // Does not apply to PCIE Path = i_cfg_fu…
200 … (0x1<<5) // Does not apply to PCIE Path = i_cfg_fu…
202 … (0x1<<6) // This bit enables the write to the Master data pari…
204 … (0x1<<7) // Does not apply to PCIE Path = i_cfg_fu…
206 …ected by the function to be reported to the Root Complex. The function reports such errors to the …
208 … (0x1<<9) // Does not apply to PCIE Path = i_cfg_fu…
210 …to generate IntX interrupt messages (de-asserted) regardless of any internal chip logic. Setting t…
218 … (0x1<<20) // This bit is tied high to indicate that the de…
220 … (0x1<<21) // Does not apply to PCIE Path = i_cfg_fu…
224 … (0x1<<23) // Does not apply to PCIE. Path = i_cfg_f…
228 … (0x3<<25) // Does not apply to PCIE Path = i_cfg_fu…
230 …ompleter terminates a request by issuing Completer abort completion status to the requester Path =…
250 …n Revision ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
252 …ing Interface. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
254 … (0xff<<16) // Subclass Code to represent Device Type. Note: The access attributes of this fi…
256 … (0xff<<24) // Base Class Code to represent Device Type. Note: The access attributes of this fi…
259 …n by firmware through the PCI register space REVISION_ID value to modify the read value to the hos…
261 … (0xffffff<<8) // The 24-bit Class Code regist…
264 … legacy compatibility purposes and is not applicable to PCI Express device functionality. Writing …
266 … (0xff<<8) // Master latency timer. Not applicable for PCI Express, hardwired to 0x0.
268 … (0x7f<<16) // Configuration header format. Hardwired to 0x0 for type 0.
270 …on device bit is writable through PEM()_CFG_WR. The application must not write a zero to this bit.
272 …e BIST register functions are not supported. All 8 bits of the BIST register are hardwired to zero.
277 …INE_SIZE_REG_LATENCY_MASTER_TIMER_K2 (0xff<<8) // Does not apply to PCI Express.
281 …multifunction. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
288 … (0xff<<8) // This register does not apply to PCI express and must be hardwired to z…
290 …ADER_TYPE_BB (0xff<<16) // The 8-bit Header Type regis…
292 …-bit BIST register is used to initiate and report the results of any Built-In-Self-Test. This valu…
297 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
303 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
304 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
306 … (0x3<<1) // BAR0 32-bit or 64-bit. Note: The access attributes of this field a…
308 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
310 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
312 …-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI…
315 …1) // These bits indicate that BAR_1 may be programmed to map this adapter to anywhere in the 64-b…
317 … (0x1<<3) // This bit indicates that the area mapped by BAR_1 may be pre-fetched or cached by …
319 …the address within a 32-bit address space that will be card will respond in. These bits may be com…
322 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
323 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
325 … (0x3<<1) // BAR1 32-bit or 64-bit. Note: The access attributes of this field a…
327 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
329 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
331 … 0x000014UL //Access:RW DataWidth:0x20 // The 32-bit BAR_2 register pr…
335 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
341 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
342 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
344 … (0x3<<1) // BAR2 32-bit or 64-bit. Note: The access attributes of this field a…
346 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
348 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
350 …-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the…
353 …1) // These bits indicate that BAR_2 may be programmed to map this adapter to anywhere in the 64-b…
355 … (0x1<<3) // This bit indicates that the area mapped by BAR_2 may be pre-fetched or cached by …
357 …the address within a 32-bit address space that will be card will respond in. These bits may be com…
360 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
361 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
363 … (0x3<<1) // BAR3 32-bit or 64-bit. Note: The access attributes of this field a…
365 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
367 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
369 … 0x00001cUL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register pr…
373 … (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. T…
379 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
380 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
382 … (0x3<<1) // BAR4 32-bit or 64-bit. Note: The access attributes of this field a…
384 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
386 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
388 …-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the…
391 …1) // These bits indicate that BAR_3 may be programmed to map this adapter to anywhere in the 64-b…
393 … (0x1<<3) // This bit indicates that the area mapped by BAR_3 may be pre-fetched or cached by …
395 …the address within a 32-bit address space that will be card will respond in. These bits may be com…
398 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
399 …ace Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
401 … (0x3<<1) // BAR5 32-bit or 64-bit. Note: The access attributes of this field a…
403 … Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED…
405 … Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled …
407 … 0x000024UL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register pr…
412 … (0xffff<<0) // Subsystem vendor ID. Assigned by PCI-SIG, writable through…
414 … (0xffff<<16) // Subsystem ID. Assigned by PCI-SIG, writable through…
417 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
419 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
422 …-bit Subsystem Vendor ID register is used by the adapter manufacturer for identification. This val…
424 …-bit Subsystem ID register is used by the adapter manufacturer for identification. This value can …
431 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
432 …<<0) // Expansion ROM Enable. Note: The access attributes of this field are as follows: - Dbi: R
434 …Expansion ROM Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W
436 … 0x000030UL //Access:RW DataWidth:0x20 // The 32-bit Expansion ROM BAR…
437 …to one. If it is zero, the expansion BAR should not be programmed or used. This bit will only be R…
441 … of the Expansion ROM area or the address of it. The boundary form RO bits to RW bits is controlle…
446 … (0xff<<0) // First capability pointer. Points to power management cap…
449 … (0xff<<0) // Pointer to first item in the PCI Capability Structure. Note: The access attributes…
452 …-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list o…
459 … (0xff<<16) // Minimum grant (hardwired to 0x0).
461 … (0xff<<24) // Maximum latency (hardwired to 0x0).
466 …egister Field. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
469 …-bit Interrupt Line register is used to communicate interrupt line routing information. This field…
471 … (0xff<<8) // The 8-bit Interrupt Pin register is used to in…
473 …ANT_BB (0xff<<16) // Hardwired to zero Path = i_cfg_fu…
475 …M_LATENCY_BB (0xff<<24) // Hardwired to zero Path = i_cfg_fu…
480 … (0xff<<8) // Next capability pointer. Points to the PCIe capabilitie…
484 … (0x1<<19) // PME clock, hardwired to zero.
499 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
501 … Spec Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
505 …0x1<<20) // Immediate Readiness on Return to D0. Note: The access attributes of this field are a…
507 …alization Bit. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
509 … Requirements. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
511 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
513 …State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
515 …tion parameter. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
522 … (0x1<<8) // PME enable. A value of one indicates that the device is enabled to generate PME.
530 … (0x1<<22) // B2/B3 support, hardwired to zero.
532 … (0x1<<23) // Bus power/clock control enable, hardwired to zero.
537 …to this register. However, the read-back value is the actual power state, not the write value. No…
539 …No soft Reset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
541 …nder aux power. Sometimes it might remember the old value, even if you try to clear it by writing …
556 … // The 8-bit Power Management Capability ID is set to 1 to indicate that the next 8 bytes are a P…
558 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
564 …eration. This chip does not require the PCI clock to generate PME#, therefore this bit is hardwire…
568 …nce following a transition to the D0 un-initialized state. This device does not need this support,…
570 …is chip uses the Data Register feature for this so this field is hardwired to '0'. Path = i_cfg_fu…
584 …gh. This bit reflects the input value of the VAUX_PRESENT input pin. Path = input pins to pcie_vaux
587 …to set the power state. The register is implemented as two banks of two bits each. Can be written …
591 … (0x1<<3) // When device transitions from D3 to D0, device does not …
595 … (0x1<<8) // This bit enables the device to transmit PME messages. On HARD reset, this bit r…
597 …hich data is to be reported through the pm_data register. (Offset 0x4f) Select values other than t…
599 …to be used when interpreting the values in the PM data register. The hardware default value for th…
601 …erted low. This bit is cleared by writing a 1 in this bit position. At power-up, the chip must cle…
603 … (0xff<<16) // This register (PMCSR PCI to PCI Bridge Support E…
605 …rmware through the PCI register space (PM_Data_0_prg to PM_Data_8_prg) to modify the read values t…
610 … Next Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
614 …ssage Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
618 … (0x1<<23) // MSI 64-bit Address Capable. Note: The access attributes of this fiel…
623 … (0xff<<0) // The 8-bit VPD Capability ID is set to 3 to in…
625 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
629 …// This value is the 32-bit word address of the VPD value being accessed in the vpd_data register.…
631 …to control passing of data between the vpd_data register and Non-Volatile memory. To read a value,…
634 …essage Lower Address Field. Note: The access attributes of this field are as follows: - Dbi: R/W
638 …-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Addr…
640 …is reserved. For 64-bit it contains upper 16 bits of the Upper Address. Note: The access attribut…
642 …UL //Access:RW DataWidth:0x20 // The device driver is prohibited from writing to this register.
643 … (0xff<<0) // The 8-bit MSI Capability ID is set to 5 to in…
645 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
647 … (0x1<<16) // When this bit is set, the chip will generate MSI cycles to indicate interrupts …
651 … bits indicate the number of message that the chip is configured (allowed) to generate. Path = i_c…
658 …-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is …
660 …-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is …
670 … Control register allows a specific number of the lower bits (up to 6) to be modified to indicate …
676 … (0xff<<8) // Next capability pointer. Points to the MSI-X Capabilities b…
682 …, it must be 0 for an endpoint device. Therefore, the application must not write a one to this bit.
689 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
695 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
697 …essage Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
704 …is not supported. Therefore, the application must not write any value other than 0x0 to this field.
712 … (0x1<<15) // Role-based error reporting…
718 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
721 …ize Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
723 …ons Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
725 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
727 … (0x7<<6) // Applies to endpoints only L0s acceptable latency. Note: The access attributes of…
729 … (0x7<<9) // Applies to endpoints only L1 acceptable latency. Note: The access attributes of…
731 … (0x1<<15) // Role-based Error Reporting Implemented. Note: The access attributes of th…
737 …dpoints only). Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
750 …er sizes are not supported by CNXXXX. DPI_SLI_PRT()_CFG[MPS] must be set to the same value as th…
752 … (0x1<<8) // Extended tag field enable. Set this bit to enable extended tags.
762 …vel reset. [I_FLR] must not be written to one via the indirect PEM()_CFG_WR. It should only ever…
764 …or example a replay-timer timeout. Also, it can be set if we get any of the errors in PCIEEP_UCOR…
766 …e receive any of the errors in PCIEEP_UCOR_ERR_MSK that has a severity set to nonfatal and does no…
768 …e receive any of the errors in PCIEEP_UCOR_ERR_MSK that has a severity set to fatal. Malformed TLP…
770 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
772 … (0x1<<20) // AUX power detected. Set to one if AUX power det…
774 … (0x1<<21) // Transaction pending. Set to 1 when nonposted requests are not yet completed a…
779 …S_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
789 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
791 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
795 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
803 …_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
816 …to allow software to locally boot and perform preconfiguration and bug fixes. Setting [MLW] and […
826 … (0x1<<19) // Surprise down error reporting capable. Set to 0 for endpoint devic…
830 … (0x1<<21) // Link bandwidth notification capability. Set to 0 for endpoint devic…
837 …In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The …
839 …In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The …
841 …ment) Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
843 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
845 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
847 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
855 …ty Compliance. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
857 …/ Port Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
864 … (0x1<<4) // Link disable. Not applicable for an upstream port or endpoint device. Hardwired to 0.
866 … (0x1<<5) // Retrain link. Not applicable for an upstream port or endpoint device. Hardwired to 0.
872 … (0x1<<8) // Enable clock power management. Hardwired to 0 if clock power man…
882 … link speeds vector (in the link capabilities 2 register) that corresponds to the current link spe…
886 …(0x1<<27) // Link training. Not applicable for an upstream port or endpoint device, hardwired to 0.
890 … // Data link layer active. Not applicable for an upstream port or endpoint device, hardwired to 0.
899 …d Completion Boundary (RCB). Note: The access attributes of this field are as follows: - Dbi: R/W
901 …_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_EN…
903 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
909 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
911 …e Autonomous Width Disable. Note: The access attributes of this field are as follows: - Dbi: R/W
913 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
915 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
923 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
925 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
929 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
931 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
942 … (0x1<<7) // 32-bit AtomicOp supporte…
944 … (0x1<<8) // 64-bit AtomicOp supporte…
946 … (0x1<<9) // 128-bit AtomicOp supporte…
948 … (0x1<<10) // No RO-enabled PR-PR passing. (This bit applies to…
956 …SUPP_E5 (0x1<<16) // 10-bit tag completer sup…
958 …SUPP_E5 (0x1<<17) // 10-bit tag requestor sup…
964 … (0x1<<21) // End-end TLP prefix suppor…
966 … (0x3<<22) // Max end-end TLP prefixes. 0x…
981 …_128_CAS_CPL_SUPP_K2 (0x1<<9) // 128 Bit CAS Completer Supported.
983 …R2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
994 …to 55 ms. 0x1 = 50 us to 100 us. 0x2 = 1 ms to 10 ms. 0x3 = 16 ms to 55 ms. 0x6 = 65 ms to 210…
1010 …EN_E5 (0x1<<12) // 10-bit tag requester ena…
1014 … (0x1<<15) // End-end TLP prefix blocki…
1017 …/ Completion Timeout Value. Note: The access attributes of this field are as follows: - Dbi: R/W
1049 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1052 …to this field that does not correspond to a speed included in the supported link speeds field, the…
1054 …ware is permitted to force a link to enter compliance mode at the speed indicated in the target li…
1056 …peed for device-specific reasons other than attempting to correct unreliable link operation by red…
1058 …) // Selectable deemphasis. Not applicable for an upstream port or endpoint device. Hardwired to 0.
1060 …-deemphasized voltage level at the transmitter pins: 0x0 = 800-1200 mV for full swing 400-600 mV …
1062 … (0x1<<10) // Enter modified compliance. When this bit is set to one, the device tran…
1064 … (0x1<<11) // Compliance SOS. When set to one, the LTSSM is required to send …
1066 …Compliance state if the entry occurred due to the TX compliance receive bit being one. 0x0 = -6 d…
1068 …ting at 5 GT/s speed, this bit reflects the level of deemphasis. 0 = -6 dB. 1 = -3.5 dB. The v…
1091 …K_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
1095 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1097 …EMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
1101 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
1103 … transmission. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1105 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
1107 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
1126 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
1128 … (0x7ff<<16) // System sw reads this field to determine the MSI-X table size N, which is encod…
1134 …le bit in the MSI message control register is 0, the function is permitted to use MSIX request ser…
1137 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X table into mem…
1142 … (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X PBA into memor…
1149 … (0xff<<8) // This registers contains the pointer to the next PCI capabil…
1151 …on. PCI Express Capability structure version number. These bits are hardwired to 2h. Path= cfg_defs
1157 …-X vector is used for the interrupt message generated in association with any of the status bits o…
1160 …MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
1164 …f<<16) // MSI-X table size encoded as (table size - 1). Writable through PEM()_CFG_WR. This fiel…
1166 …ctors associated with the function are masked, regardless of their respective per-vector mask bits.
1168 … (0x1<<31) // MSI-X enable. If MSI-X is enabled,…
1170 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
1171 …TRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
1173 … (0xff<<8) // MSI-X Next Capability Pointer. Note: The access attributes of this f…
1175 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
1177 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
1179 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
1194 … (0x1<<15) // Indicate device is conforming to the ECN, PCI Express…
1205 … (0x7<<0) // MSI-X table BAR indicator register (BIR). Indicates which BAR is u…
1207 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1209 … 0x0000b4UL //Access:RW DataWidth:0x20 // MSI-X Table Offset and BI…
1210 … (0x7<<0) // MSI-X Table Bar Indicator Register Field. Note: The access attributes of …
1212 … (0x1fffffff<<3) // MSI-X Table Offset. Note: The access attributes of this field …
1217 …L_ERR_REPORT_EN_BB (0x1<<1) // Non-Fatal Error Reporting…
1227 …(0x1<<8) // Extended Tag Field Enable. This capability when set allows DUT to generate more than 3…
1231 … (0x1<<10) // This bit when set enables device to draw aux power indep…
1233 … (0x1<<11) // Enable No Snoop. When this bit is set to 1, PCIE initiates a …
1237 …r_supported bit in private device_capability register is set. A write of 1 to this bit initiates F…
1241 …TAL_ERR_DET_BB (0x1<<17) // Non-Fatal Error Detected.…
1247 …t is indicating that part needs VAUX and detects the VAUX is present. Path= input to pcie_vaux_pipe
1249 …1) // This is bit is read back a 1, whenever a non-posted request initiated by PCIE core is pendin…
1252 … (0x7<<0) // MSI-X PBA BAR indicator register (BIR). Indicates which BAR is us…
1254 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
1256 … 0x0000b8UL //Access:RW DataWidth:0x20 // MSI-X PBA Offset and BIR …
1257 … (0x7<<0) // MSI-X PBA BIR. Note: The access attributes of this field are…
1259 … (0x1fffffff<<3) // MSI-X PBA Offset. Note: The access attributes of this field a…
1272 …ment. These bits are programmable through register. The feature itself has to be enabled in versio…
1274 …e Down error condition. RC: Not supported and hardwired to 0. EP: Not supported and hardwired to 0…
1276 …to 1b if the component supports the optional capability of reporting the DL_Active state of the Da…
1278 …ple Link speeds. RC: Field is implemented. EP: Not supported and hardwired to 0. Path= i_cfg_func.…
1291 … (0x1<<4) // Requesting PHY to disable the link. This bit is only applicabl…
1293 … (0x1<<5) // Requesting PHY to retrain the link. This bit is only applicabl…
1295 … (0x1<<6) // Common Clock Configuration. Value used by logic is resolved to 1 only if all functi…
1297 …to entering the L0 state, and the transmission of 1024 TS1 ordered sets in the L1 state prior to e…
1299 …r Management: RC: N/A and hardwired to 0. EP: When this bit is set, the device is permitted to use…
1301 …to correct unreliable Link operation by reducing Link width. Other functions are reserved. RC: Not…
1303 …terrupt to indicate that the Link Bandwidth Management Status bit has been Set. RC: N/A and hardwi…
1305 …terrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set. RC: Not implemente…
1315 … (0x1<<27) // EP: This bit is N/A and is hardwired to 0. Path= i_cfg_func.…
1317 … (0x1<<28) // Slot Clock configuration. This bit is read-only by host, but rea…
1319 …Link Layer Link Active: returns a 1b to indicate the DL_Active state, 0b otherwise. Not implemente…
1341 …00c8UL //Access:R DataWidth:0x20 // For EP this register is not applicable and hardwired to 0.
1342 …00ccUL //Access:R DataWidth:0x20 // For EP this register is not applicable and hardwired to 0.
1355 … (0xff<<8) // VPD Pointer to Next Capability. Note: The access attributes of this field…
1357 …0x7fff<<16) // VPD Address. Note: The access attributes of this field are as follows: - Dbi: R/W
1359 … (0x1<<31) // VPD Flag. Note: The access attributes of this field are as follows: - Dbi: R/W
1385 …ter Enable. When this bit is set, function and associated VF's are enabled to make Atomic Op reque…
1389 …_capability_2 register is set. When this bit is set, function is permitted to set ID based Orderin…
1391 …_capability_2 register is set. When this bit is set, function is permitted to set ID based Orderin…
1404 … will read all 0's to allow compliance with PCIE spec 1.1. To enable this register, reset comply_p…
1411 …this bit selects the level of de-emphasis. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Value used …
1413 … (0x7<<7) // Value used by logic is resolved to the smaller binary v…
1425 … (0x1<<17) // Equalization Complete - when set, this indic…
1427 … (0x1<<18) // Equalization Phase 1 Successful - when set, this indic…
1429 … (0x1<<19) // Equalization Phase 2 Successful - when set, this indic…
1431 … (0x1<<20) // Equalization Phase 3 Successful - when set, this indic…
1433 … (0x1<<21) // This bit is set by hardware to request the link equalization process to…
1451 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1453 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1455 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1458 …0xffff<<0) // PCI Express Extended Capability ID. These bits are hardwired to 0001h indicating the…
1460 … (0xf<<16) // Capability ID Version. These bits are hardwired to 1h indicating the ve…
1518 …h as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bu…
1550 … (0x1<<5) // Surprise down error mask. Set to 0 for endpoint devic…
1597 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1603 …sk (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1605 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1637 … (0x1<<5) // Surprise down error severity. Set to 1 for endpoint devic…
1686 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1692 …ty (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1694 … Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
1701 … (0x1<<5) // Surprise Down Error Severity. Hardwire to 1'b1.
1751 …ATAL_ERR_STATUS_K2 (0x1<<13) // Advisory Non-Fatal Error Status.
1802 …ERR_MASK_K2 (0x1<<13) // Advisory Non-Fatal Error Mask. N…
1858 … (0x1f<<0) // First Error Pointer - These bits correspond to the bit …
1868 …x20 // The header log registers collect the header for the TLP corresponding to a detected error.
1879 …x20 // The header log registers collect the header for the TLP corresponding to a detected error.
1890 …x20 // The header log registers collect the header for the TLP corresponding to a detected error.
1901 …x20 // The header log registers collect the header for the TLP corresponding to a detected error.
1912 …012cUL //Access:R DataWidth:0x20 // For EP this register is not applicable and hardwired to 0.
1913 …0130UL //Access:R DataWidth:0x20 // For EP this register is not applicable and hardwired to 0.
1914 …0134UL //Access:R DataWidth:0x20 // For EP this register is not applicable and hardwired to 0.
1972 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1974 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1976 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1982 …nded VC Count. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1990 …on Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
1995 … (0xffff<<0) // Power Budgeting Extended Capability ID. Hardwired to 4. Path = cfg_defs
1997 …ability ID Version. These bits are hardwired to 1h indicating the version of the capability ID. Ha…
1999 …pecified an offset in the PCI address space of the next capability. The read-only value of this re…
2002 …_K2 (0x1<<0) // Requests Hardware to Load VC Arbitration …
2021 …// Reject Snoop Transactions. Note: The access attributes of this field are as follows: - Dbi: R
2023 … (0x3f<<16) // Maximum Time Slots-1 supported. Note: The access attributes of this field ar…
2044 …MAP_VC0_K2 (0x1<<0) // Bit 0 of TC to VC Mapping.
2046 …VC0_BIT1_K2 (0x7f<<1) // Bits 7:1 of TC to VC Mapping.
2077 … 0x000160UL //Access:R DataWidth:0x20 // The read-back value of this re…
2078 … (0xffff<<0) // Virtual channel Capability ID. Hardwired to 2. Path = cfg_defs
2080 …ability ID Version. These bits are hardwired to 1h indicating the version of the capability ID. Ha…
2093 … (0xfff<<20) // Next capability offset. Points to the secondary PCI Ex…
2096 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2098 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2100 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2124 … 0x000174UL //Access:RW DataWidth:0x20 // The read-back value of this re…
2125 … (0x1<<0) // This bit is hardwired to one because DUT is o…
2127 …e TCs that are mapped to the VC resource. This field is valid for all devices. Note: Bit 0 of this…
2131 …1<<31) // Enables virtual channel. This bit is hardwired to 1 for the default VC0 and writing to t…
2141 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2143 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2145 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2176 … 0x000180UL //Access:R DataWidth:0x20 // The read-only value of this re…
2177 … (0xffff<<0) // Vendor Specific Extended Capability ID. Hardwired to 0xB. Path = cfg_defs
2179 … (0xf<<16) // Vendor Specific Extended Capability version. Hardwired to 0x1. Path = cfg_defs
2201 … Allocated PB. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2203 … 0x000184UL //Access:R DataWidth:0x20 // The read-only value of this re…
2204 … (0xffff<<0) // VSEC ID. This field is a vendor-defined ID number tha…
2206 … (0xf<<16) // VSEC Rev. This field is a vendor-defined version numbe…
2208 …uding the PCI Express Enhanced Capability header, the Vendor-Specific header, and the Vendor-Speci…
2228 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2230 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2232 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2234 …bit 0 of the EXT_CAP_ENA for EP or bit 0 of RC_EXT_CAP_ENA for RC is reset to '0', reading this re…
2235 …pace. The bits are a power of 2 value that multiplies the PF VF Bar0 value to compute the starting…
2288 …pace. The bits are a power of 2 value that multiplies the PF VF Bar2 value to compute the starting…
2328 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2330 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2332 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2335 …pace. The bits are a power of 2 value that multiplies the PF VF Bar4 value to compute the starting…
2357 …0) // Perform Equalization. Note: The access attributes of this field are as follows: - Dbi: R/W
2359 …n Request Interrupt Enable. Note: The access attributes of this field are as follows: - Dbi: R/W
2382 …tter Preset 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2384 …Preset Hint 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2386 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2388 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2390 …tter Preset 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2392 …Preset Hint 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2394 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2396 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2405 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2406 …itter Preset2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2408 … Preset Hint2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2410 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2412 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2414 …itter Preset3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2416 … Preset Hint3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2418 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2420 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2423 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2424 …itter Preset4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2426 … Preset Hint4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2428 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2430 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2432 …itter Preset5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2434 … Preset Hint5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2436 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2438 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2441 …ster is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_…
2442 …itter Preset6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2444 … Preset Hint6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2446 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2448 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2450 …itter Preset7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2452 … Preset Hint7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2454 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2456 …BILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && P…
2458 …-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default,…
2461 … (0xf<<16) // LTR Capability version. Hardwired to 0x1.
2477 …is register specifies the maximum no-snoop latency that a device is premitted to request. Software…
2483 …is register specifies the maximum no-snoop latency that a device is premitted to request. Software…
2490 … 0x0001b8UL //Access:RW DataWidth:0x20 // SR-IOV Capability Header…
2491 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2493 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2495 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2497 … 0x0001b8UL //Access:R DataWidth:0x20 // The read-only value of this re…
2498 … (0xffff<<0) // ARI Extended Capability ID. Hardwired to 0xE.
2500 … (0xf<<16) // ARI Capability version. Hardwired to 0x1.
2507 … 0x0001bcUL //Access:RW DataWidth:0x20 // SR-IOV Capability Regist…
2510 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2515 …ISTER_MFVC_FUNC_GROUP_CAP_BB (0x1<<0) // Hardwired to 0
2517 …ISTER_ACS_FUNC_GROUP_CAP_BB (0x1<<1) // Hardwired to 0
2523 … (0xffff<<16) // Field is unused and is hardwired to 0.
2528 … 0x0001c0UL //Access:RW DataWidth:0x20 // SR-IOV Control and Statu…
2537 …to endpoint only). For a description of this standard PCIe register field, see the Single Root I/O…
2539 … 0x0001c0UL //Access:R DataWidth:0x20 // The read-only value of this re…
2540 … (0xffff<<0) // SRIOV Extended Capability ID. Hardwired to 0xE.
2542 … (0xf<<16) // SRIOV Capability version. Hardwired to 0x1.
2547 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2549 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2552 … (0x1<<0) // The capability is hardwired to 0.
2556 … (0x3fffffff<<2) // The capability is hardwired to 0.
2575 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
2576 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: STATUS_CONTROL_…
2585 … (0x1<<2) // This bit has no effect in IP. However spec has defined it to be RW.
2589 … (0x1<<4) // When set, the device is permitted to locate VF in Func Number 8 to 255. …
2591 … (0x7ff<<5) // The Status is hardwired to 0.
2593 … (0xffff<<16) // The Status is hardwired to 0.
2613 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" det…
2615 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". de…
2640 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2668 … associated with the PF. The First VFs RID is calculated by adding this field to the RID of the PF.
2670 … (0xffff<<16) // This field is hardwired to 1.
2683 …ramming in private space at 0x604. This field contains Device ID for every VF belonging to this PF.
2692 …to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the …
2693 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2695 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2697 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2699 …egister is based on programming in private space at 0x60C. Default indicates support from 4K to 4M.
2717 …to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the …
2718 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2720 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2722 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2724 … // Default value is 4K . This field defines the page size system will use to map VFs mem address.
2742 …to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the …
2743 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2745 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2747 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2749 …-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging t…
2752 … // These bits indicate that VF_BAR0 may be programmed to map this adapter to anywhere in the 64-b…
2754 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR0 may be pre-fetched or cached by …
2758 …t the address within a 32-bit address space that device will respond in. These bits may be combine…
2777 …to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the …
2778 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2780 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2782 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2784 … 0x0001e8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR1 register …
2802 …to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the …
2803 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2805 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2807 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2809 …-bit VF_BAR2 register programs the base address for the memory space mapped by the VFs belonging t…
2812 … // These bits indicate that VF_BAR2 may be programmed to map this adapter to anywhere in the 64-b…
2814 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR2 may be pre-fetched or cached by …
2818 …t the address within a 32-bit address space that device will respond in. These bits may be combine…
2837 …to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the …
2838 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2840 …n Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and …
2842 … Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W
2844 … 0x0001f0UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR3 register …
2867 …-bit VF_BAR4 register programs the base address for the memory space mapped by the VFs belonging t…
2870 … // These bits indicate that VF_BAR4 may be programmed to map this adapter to anywhere in the 64-b…
2872 … (0x1<<3) // This bit indicates that the area mapped by VF_BAR4 may be pre-fetched or cached by …
2876 …t the address within a 32-bit address space that device will respond in. These bits may be combine…
2896 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2898 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2900 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2902 … 0x0001f8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR5 register …
2920 …e: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common re…
2923 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2925 …ode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2927 …ter Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2929 …ocation Bit 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2931 …ocation Bit 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2933 …ST Table Size. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
2953 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
2957 … 0x000200UL //Access:R DataWidth:0x20 // The read-only value of this re…
2960 … (0xf<<16) // PTM Capability version. Hardwired to 0x1.
2982 … Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by…
2984 … Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by…
3007 … (0x1<<0) // When Set, Function is permitted to participate in PTM m…
3013 …uracy of the PTM clock. For endpoints, system software programs this field to the value representi…
3049 … 0x000210UL //Access:R DataWidth:0x20 // The read-only value of this re…
3050 … (0xffff<<0) // ATS Extended Capability ID. Hardwired to 0xF.
3052 … (0xf<<16) // ATS Capability version. Hardwired to 0x1.
3076 …<<5) // This bit when set indicates Untranslated Address is always aligned to 4K boundary. the val…
3080 … (0x1f<<16) // The value indicates to the Function, the mi…
3084 … (0x1<<31) // When set, function is enabled to cache translations.
3127 … 0x000220UL //Access:R DataWidth:0x20 // The read-only value of this re…
3128 … (0xffff<<0) // RBAR Extended Capability ID. Hardwired to 0x15.
3130 … (0xf<<16) // RBAR Capability version. Hardwired to 0x1.
3139 …5 (0x1<<2) // VF 10-bit tag requester sup…
3146 … (0x1<<4) // when Set, it indicates function will operate with Bar sized to 1M. Value reflected …
3148 … (0x1<<5) // when Set, it indicates function will operate with Bar sized to 2M. Value reflected …
3150 … (0x1<<6) // when Set, it indicates function will operate with Bar sized to 4M. Value reflected …
3152 … (0x1<<7) // when Set, it indicates function will operate with Bar sized to 8M. Value reflected …
3154 … (0x1<<8) // when Set, it indicates function will operate with Bar sized to 16M. Value reflected…
3156 … (0x1<<9) // when Set, it indicates function will operate with Bar sized to 32M. Value reflected…
3158 … (0x1<<10) // when Set, it indicates function will operate with Bar sized to 64M. Value reflected…
3160 … (0x1<<11) // when Set, it indicates function will operate with Bar sized to 128M. Value reflecte…
3162 … (0x1<<12) // when Set, it indicates function will operate with Bar sized to 256M. Value reflecte…
3164 … (0x1<<13) // when Set, it indicates function will operate with Bar sized to 512M. Value reflecte…
3166 … (0x1<<14) // when Set, it indicates function will operate with Bar sized to 1G. Value reflected …
3179 … (0x1<<4) // ARI capable hierarchy. 0 = All PFs have non-ARI capable hierarchy…
3181 …5 (0x1<<5) // VF 10-bit Tag Requester Ena…
3197 … (0xffff<<16) // Total VFs. Read-only copy of PCIEEP_S…
3204 … 0x000230UL //Access:R DataWidth:0x20 // The read-only value of this re…
3207 … (0xf<<16) // LTR Capability version. Hardwired to 0x1.
3212 …-ARI capable hierarchies. The PCIEEP_SRIOV_CTL[ACH] determines which one is being used for SR-IOV…
3214 …-ARI: 0x1. There are two VF stride registers; one for each ARI capable and non-ARI capable…
3217 … (0x1<<0) // Function supports NO ST mode of operation. This mode is required to be supported.
3231 … (0x7ff<<16) // Software reads this field to determine the STTable Size N, whihc is encoded…
3245 …-only value of this register is controlled by setting bit 2 of the EXT2_CAP_ENA for EP, By default…
3255 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3274 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mo…
3276 …me in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, bef…
3280 …me in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, bef…
3307 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3324 … (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR.
3350 …is not supported. Therefore, the application must not write any value other than 0x0 to this field.
3356 … (0x7ff<<16) // ST table size (limited by MSI-X table size).
3364 … (0xff<<0) // ST table 0 lower byte. Access can be tied to 0 by table size conf…
3366 … (0xff<<8) // ST table 0 upper byte. Access can be tied to 0 by table size conf…
3369 …d Capacity ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3371 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3373 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3375 … 0x000288UL //Access:RW DataWidth:0x20 // LTR Max Snoop and No-Snoop Latency Registe…
3380 …T_K2 (0x3ff<<16) // Max No-Snoop Latency Value.
3382 …LAT_SCALE_K2 (0x7<<26) // Max No-Snoop Latency Scale.
3384 … 0x00028cUL //Access:RW DataWidth:0x20 // Vendor-Specific Extended Cap…
3385 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3387 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3389 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
3391 … 0x000290UL //Access:R DataWidth:0x20 // Vendor-Specific Header.
3398 …- Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register det…
3399 …ear' code. The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11:…
3401 …ays '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no…
3403 …alue of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT…
3405 …a returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - ..…
3407 …- 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the Group For e…
3409 …s: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVEN…
3410 …-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time sp…
3411 … (0x1<<0) // Timer Start. - 0: Start/Restart - 1: Stop Th…
3413 …-based Duration Select. Selects the duration of time-based analysis. When "manual control" is sele…
3415 …-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_…
3417 …-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in …
3418 …- 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ…
3431 …set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_R…
3433 …- LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link …
3434 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG r…
3436 …to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection…
3438 …- ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 409…
3439 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG r…
3441 …nce number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - …
3443 …to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's c…
3445 …- If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the trans…
3446 …- If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_R…
3448 …ors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmissio…
3450 …- If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeo…
3451 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG r…
3453 …- Mask K symbol. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set)…
3455 …to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Hea…
3456 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG r…
3458 …-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Po…
3462 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is repr…
3464 … - For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These …
3465 …- If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG r…
3467 …ied TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK …
3469 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], …
3470 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], …
3471 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], …
3472 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], …
3473 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], …
3481 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], …
3483 … (0x1<<0) // ACS source validation. Hardwired to 0 for upstream port.…
3513 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], …
3519 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], …
3527 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], …
3533 … (0x3ff<<16) // Max no-snoop latency value.
3535 … (0x7<<26) // Max no-snoop latency scale.
3537 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], …
3545 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], …
3546 … 0x000300UL //Access:R DataWidth:0x20 // The read-only value of this re…
3549 … (0xf<<16) // Capability version. Hardwired to 0x1.
3554 …PCIPM_SUP_E5 (0x1<<0) // PCI-PM L12 supported.
3556 …PCIPM_SUP_E5 (0x1<<1) // PCI-PM L11 supported.
3564 …<8) // Port common mode restore time. Time (in us) required for this Port to reestablish common m…
3568 … (in us) that this Port requires the port on the opposite side of the Link to wait in L.1.2.Exit a…
3570 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], …
3572 …FORM_EQ_BB (0x1<<0) // N/A to endpoints
3574 …K_EQ_REQ_INT_EN_BB (0x1<<1) // N/A to endpoints
3577 …1_2_PCIPM_EN_E5 (0x1<<0) // PCI-PM L12 enable.
3579 …1_1_PCIPM_EN_E5 (0x1<<1) // PCI-PM L11 enable.
3587 …lue. Along with [L1_2_TH_SCA], this field indicates the LTR threshold use to determine if entry i…
3589 …s. 0x2 = 1024 ns. 0x3 = 32,768 ns. 0x4 = 1,048,575 ns. 0x5 = 33,554,432 ns. 0x6-7 = Reserved.
3591 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], …
3600 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], …
3602 …PRESETS0_BB (0xff<<0) // Applicable only to Upstream component.
3610 …RESETS1_BB (0xff<<16) // Applicable only to Upstream component.
3625 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], …
3627 …PRESETS2_BB (0xff<<0) // Applicable only to Upstream component.
3635 …RESETS3_BB (0xff<<16) // Applicable only to Upstream component.
3656 …to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], …
3658 …PRESETS4_BB (0xff<<0) // Applicable only to Upstream component.
3666 …RESETS5_BB (0xff<<16) // Applicable only to Upstream component.
3679 … (0xfff<<20) // Next capability offset. Points to the Vendor Specific RAS Data Pat…
3681 …to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*…
3682 …to insert. This counter is decremented while errors are been inserted. - If the counter value is …
3684 …ror Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EI…
3686 … Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs -…
3689 …PRESETS6_BB (0xff<<0) // Applicable only to Upstream component.
3697 …RESETS7_BB (0xff<<16) // Applicable only to Upstream component.
3713 …PRESETS8_BB (0xff<<0) // Applicable only to Upstream component.
3721 …RESETS9_BB (0xff<<16) // Applicable only to Upstream component.
3736 …ter data returned in the PCIEEP_RAS_EC_DATA[EV_CNTR_DATA]. 0x0-0x7 = Lane number. 0x8-0xF = Res…
3741 …P_PRESETS10_BB (0xff<<0) // Applicable only to Upstream component.
3749 …_PRESETS11_BB (0xff<<16) // Applicable only to Upstream component.
3759 …P_PRESETS12_BB (0xff<<0) // Applicable only to Upstream component.
3767 …_PRESETS13_BB (0xff<<16) // Applicable only to Upstream component.
3778 …-based duration select. Selects the duration of time-based analysis. 0x0 = Manual control. Ana…
3780 …EL_E5 (0xff<<24) // Time-based report select. …
3783 …P_PRESETS14_BB (0xff<<0) // Applicable only to Upstream component.
3791 …_PRESETS15_BB (0xff<<16) // Applicable only to Upstream component.
3800 …W DataWidth:0x20 // Silicon Debug Control 1. For more details, see the RAS DES section in the …
3801 …uring LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. -…
3805 …-reset exit. The core selects the greater value between this register and the value defined by the…
3807 …he value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0:…
3809 …W DataWidth:0x20 // Silicon Debug Control 2. For more details, see the RAS DES section in the …
3812 …this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This reques…
3814 …and the core detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State. Note:…
3816 …// Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle …
3818 …irect Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance S…
3820 …/ Detect Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active S…
3822 …(0x1<<16) // Framing Error Recovery Disable. This bit forces a transition to Recovery state when …
3824 … Per-lane). This viewport register returns the data selected by the following field: - LANE_SELEC…
3825 …er for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 …
3839 …th:0x20 // Silicon Debug Status(Layer1 LTSSM). For more details, see the RAS DES section in the …
3840 …- 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When …
3848 …-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negoti…
3850 … DataWidth:0x20 // Silicon Debug Status(PM). For more details, see the RAS DES section in the …
3851 …- 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDL…
3853 …- 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 08h: L1 - 09h: L1_BLOCK_…
3855 … Re-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host soft…
3870 …. Enables insertion of duplicate/nullified TLPs. For more details, refer to PCIEEP_RAS_EINJ_CTL5.
3872 …les insertion of errors into the packet selected. For more details, refer to PCIEEP_RAS_EINJ_CTL6…
3874 …ataWidth:0x20 // Silicon Debug Status(Layer2). For more details, see the RAS DES section in the …
3879 … (0x3<<24) // DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 1…
3888 …-FC DLLP. 0x3 = New TLP's ECRC error injection. 0x4 = TLP's FCRC error injection (128b/130b). 0…
3890 …e following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE - CREDIT_SE…
3891 …ort-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data …
3893 …IT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CRE…
3895 …iewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 d…
3897 …TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_D…
3899 …TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value …
3901 …YPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value …
3908 …to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's c…
3910 …ataWidth:0x20 // Silicon Debug Status(Layer3). For more details, see the RAS DES section in the …
3911 …- 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: T…
3918 … (0x3<<8) // DLLP type. Selects the type of DLLP errors to be inserted. 0x0 =…
3923 …ng - Mask K symbol. 0x0 = Reserved. 0x1 = COM/PAD(TS1 Order Set). 0x2 = COM/PAD(TS2 Order Set)…
3928 …-FC type. Selects the credit type. 0x0 = Posted TLP header credit value control. 0x1 = Non-Pos…
3932 …-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. The value is rep…
3934 …etermine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport re…
3935 …-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
3937 …the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/…
3939 …al Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11:…
3948 … (0x1<<8) // Specified TLP. Selects the specified TLP to be inserted. 0x0 =…
3950 …E_SEL fields in the SD_EQ_CONTROL1_REG register. For more details, see the RAS DES section in the …
3951 … (0x3f<<0) // Force Local Transmitter Pre-cursor. Indicates th…
3955 … (0x3f<<12) // Force Local Transmitter Post-Cursor. Indicates th…
3961 …fficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CUR…
3968 …E_SEL fields in the SD_EQ_CONTROL1_REG register. For more details, see the RAS DES section in the …
3969 … (0x3f<<0) // Force Remote Transmitter Pre-Cursor. Indicates th…
3973 … (0x3f<<12) // Force Remote Transmitter Post-Cursor. Indicates th…
3975 …ficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CU…
3979 …NVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_VIOLATION - EQ_REJECT_…
3982 …nformation. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x…
3993 …on finished successfully(EQ_CONVERGENCE_INFO=1). For more details, see the RAS DES section in the …
3994 …_K2 (0x3f<<0) // EQ Local Pre-Cursor. Indicates Lo…
3998 …K2 (0x3f<<12) // EQ Local Post-Cursor. Indicates Lo…
4005 …on finished successfully(EQ_CONVERGENCE_INFO=1). For more details, see the RAS DES section in the …
4006 …_K2 (0x3f<<0) // EQ Remote Pre-Cursor. Indicates Re…
4010 …K2 (0x3f<<12) // EQ Remote Post-Cursor. Indicates Re…
4023 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4025 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4027 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4038 …ou to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implement…
4039 …for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4055 …mpletion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. …
4068 … 0x000398UL //Access:RW DataWidth:0x20 // Corrected error (1-bit ECC) counter sele…
4071 …) // Enable correctable errors counters. - 1: counters increment when the core detects a correcta…
4073 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4075 …RT_OFF register. You can cycle this field value from 0 to 255 to access all counters according to …
4078 … 0x00039cUL //Access:R DataWidth:0x20 // Corrected error (1-bit ECC) counter data…
4081 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4086 … 0x0003a0UL //Access:RW DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) c…
4087 …errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared.
4089 … Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correct…
4091 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4093 …RT_OFF register. You can cycle this field value from 0 to 255 to access all counters according to …
4098 …Inverted error injection control. 0x0 = EINJ6_CHG_VAL_H[0/1/2/3] is used to replace bits specifi…
4100 …cts the TLP packets to inject errors into. 0x0 = TLP header. 0x1 = TLP prefix 1st 4-DWORDs. 0x…
4102 … 0x0003a4UL //Access:R DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) c…
4105 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4109 …he following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection mod…
4112 … (0x3<<4) // Error injection type: - 0: none - 1: 1-bit - 2: 2-bit
4114 … (0xff<<8) // Error injection count. - 0: errors are inserted in every TLP until you clear ERR…
4116 …ion takes place. You can cycle this field value from 0 to 255 to access all locations according to…
4118 … DataWidth:0x20 // Corrected errors locations. For more details, see the RAS Data Protection (DP…
4119 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4121 …RST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to …
4123 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4125 …AST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to …
4127 …ataWidth:0x20 // Uncorrected errors locations. For more details, see the RAS Data Protection (DP…
4128 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4130 …T_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to …
4132 …- 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region sele…
4134 …T_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to …
4136 …s mode: - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you mu…
4137 …EN_K2 (0x1<<0) // Write '1' to enable the core ente…
4139 … (0x1<<1) // Write '1' to enable the core to bring the …
4146 …-reset exit. The core selects the greater value between this register and the value defined by the…
4148 … value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY 0x0 = 40n…
4150 …:RW DataWidth:0x20 // Exit RASDP error mode. For more details, see the RAS Data Protection (DP…
4151 …DE_CLEAR_K2 (0x1<<0) // Write '1' to take the core out of…
4156 …equest. When this bit is set in L0 or L0s, the LTSSM starts transitioning to recovery state. This…
4158 … is set and the core detects REPLY_NUM rolling over 4 times, the LTSSM transitions to detect state.
4160 …// Direct Recovery.Idle to configuration. When this bit is set and the LTSSM is in recovery idle …
4162 …irect Polling.Compliance to detect. When this bit is set and the LTSSM is in polling compliance s…
4164 …<10) // Direct loopback slave to exit. When set and the LTSSM is in loopback slave active state, …
4166 …x1<<16) // Framing error recovery disable. This bit disables a transition to recovery state when …
4168 …x20 // RAM Address where a corrected error (1-bit ECC) has been detected. For more details, see …
4169 … (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been det…
4171 … (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been det…
4173 … // RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see …
4174 … (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been det…
4176 … (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been det…
4179 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4181 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4183 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4186 … silicon debug status register of Layer1-PerLane. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 …
4201 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4203 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4205 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4207 …cification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4210 …-STP/SDP/IDL token was received and it was not in TLP/DLLP reception. 0x02 = When current token w…
4218 …to one if both ports advertised the UpConfigure capability in the last Config.Complete. 0x4 = sel…
4221 … (0x1<<0) // PTM Enable. When set, this function is permitted to participate in the P…
4223 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4225 …s Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT
4228 … 0x17 = L0S_BLOCK_TLP. 0x18 = WAIT_LAST_PMDLLP. 0x19 = WAIT_DSTATE_UPDATE. 0x20-0x1F = Reserved.
4230 …S_L23RDY_WAIT4ALIVE. 0x0F = S_L23RDY_WAIT4IDLE. 0x10 = S_WAIT_LAST_PMDLLP. 0x10-0x1F = Reserved.
4232 …_Status bit. If host software does not clear PME_Status bit for 100ms (+50%/-5%), the DUT resends …
4239 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4241 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4243 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4257 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4259 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4261 …n the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4264 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4266 …ith the [CREDIT_SEL_VC], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determi…
4268 …] viewport-select fields determines that data that is returned by the [CREDIT_DATA0] and [CREDIT_D…
4270 …CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], and [CREDIT_SEL_TLP_TYPE] viewport-select fields determi…
4272 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4274 …CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = …
4277 … (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Requester will automatically at…
4279 … (0x1<<1) // PTM Requester Start Update - When set the PTM Requester will attempt a PTM Dia…
4281 …- Debug mode for PTM Timers. The 100us timer output will go high at 30us and the 10ms timer output…
4283 … (0xff<<8) // PTM Requester Long Timer - Determines the perio…
4286 …ion request rules. 0x0E = Invalid TLP type. 0x0F = Completion rules. 0x10-0x7E = Reserved. 0x7…
4291 … (0x1<<0) // PTM Requester Context Valid - Indicate that the Ti…
4293 … (0x1<<1) // PTM Requester Manual Update Allowed - Indicates whether or…
4298 …-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] view…
4300 …ct. Setting this field in conjunction with [EQ_LANE_SEL] determines the per-lane silicon debug EQ…
4330 … (0x3f<<0) // Force remote transmitter pre-cursor as selected by…
4345 … (DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to the rules a) from se…
4347 …e (DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to the rules b) from se…
4349 …se (DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to the rules c) from se…
4383 …his bit enables the advertisement of bar_1 as a 32-bit address. The value of this bit maps directl…
4385 …to re-try all cycles to the current Expansion ROM BAR area. When this bit is set, then no Expansio…
4387 …to re-try all cycles to the configuration space until it is cleared. This is used to block the hos…
4389 …to detect if the host already has the reset values of the configuration space. this may happen if …
4391 …en this value is non-zero, the Expansion ROM attention must be handled by an internal processor to…
4393 …16) // This bit when set is reflected in bit 3 of bar_1 and indicates that the BAR is pre-fetchable
4399 …s reset only reset by HARD Reset such that it can be used to detect initial power up if a non-zero…
4403 …to '1' forces the VF to drop any mem request that it receives. UR completion will be returned for …
4407 … (0x1<<24) // Setting this bit to '1' forces the PME message to be se…
4413 …lue interfaces to the PM_STATE value in the Power Management configuration space. Reads of this re…
4450 …quiring a BAR size greater than 1 GB, the corresponding bar1_size bits should be programmed to 0xF.
4452 …quiring a BAR size greater than 1 GB, the corresponding bar2_size bits should be programmed to 0xF.
4454 …quiring a BAR size greater than 1 GB, the corresponding bar3_size bits should be programmed to 0xF.
4456 …d be programmed to 0x0, as also the bar1_size_hiext bits. If desiring a bar size greater than 32K,…
4460 …d be programmed to 0x0, as also the bar1_size_hiext bits. If desiring a bar size greater than 32K,…
4462 …d be programmed to 0x0, as also the bar1_size_hiext bits. If desiring a bar size greater than 32K,…
4472 … (0xfff<<0) // PTM Requester TX Latency - Requester Transmit p…
4504 … (0xfff<<0) // PTM Requester RX Latency - Requester Receive pa…
4511 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4513 …be read from PCIEEP_RAS_TBA_CTL. You can cycle this field value from 0 to 255 to access all count…
4516 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4518 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4520 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
4525 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4530 … (0x1<<4) // Up to 1MB BAR Supported. Note: The access attributes of this fiel…
4532 … (0x1<<5) // Up to 2MB BAR Supported. Note: The access attributes of this fiel…
4534 … (0x1<<6) // Up to 4MB BAR Supported. Note: The access attributes of this fiel…
4536 … (0x1<<7) // Up to 8MB BAR Supported. Note: The access attributes of this fiel…
4538 … (0x1<<8) // Up to 16MB BAR Supported. Note: The access attributes of this fie…
4540 … (0x1<<9) // Up to 32MB BAR Supported. Note: The access attributes of this fie…
4542 … (0x1<<10) // Up to 64MB BAR Supported. Note: The access attributes of this fie…
4544 … (0x1<<11) // Up to 128MB BAR Supported. Note: The access attributes of this fie…
4546 … (0x1<<12) // Up to 256MB BAR Supported. Note: The access attributes of this fie…
4548 … (0x1<<13) // Up to 512MB BAR Supported. Note: The access attributes of this fie…
4550 … (0x1<<14) // Up to 1GB BAR Supported. Note: The access attributes of this fiel…
4552 … (0x1<<15) // Up to 2GB BAR Supported. Note: The access attributes of this fiel…
4554 … (0x1<<16) // Up to 4GB BAR Supported. Note: The access attributes of this fiel…
4556 … (0x1<<17) // Up to 8GB BAR Supported. Note: The access attributes of this fiel…
4558 … (0x1<<18) // Up to 16GB BAR Supported. Note: The access attributes of this fie…
4560 … (0x1<<19) // Up to 32GB BAR Supported. Note: The access attributes of this fie…
4562 … (0x1<<20) // Up to 64GB BAR Supported. Note: The access attributes of this fie…
4564 … (0x1<<21) // Up to 128GB BAR Supported. Note: The access attributes of this fie…
4566 … (0x1<<22) // Up to 256GB BAR Supported. Note: The access attributes of this fie…
4568 … (0x1<<23) // Up to 512GB BAR Supported. Note: The access attributes of this fie…
4571 …s bit will be set if there is a pending request for action by the firmware to handle a Vital Produ…
4578 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4580 …be read from PCIEEP_RAS_TBA_CTL. You can cycle this field value from 0 to 255 to access all count…
4587 …) // BAR Size. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) N…
4594 … register to be passed to the NVM interface. If the value is clear, then the host has requested th…
4599 …). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved.
4603 …to clear the INTF_REQ bit. When INTF_REQ is '1' and the WR bit is set, this word should be read an…
4607 … (0x3<<4) // Error injection type. 0x0 = None. 0x1 = 1-bit. 0x2 = 2-bit. 0x3 = Re…
4609 … 0x0 = errors are injected in every TLP until [ERR_INJ_EN] is cleared. 0x1 - 0xFF = number of err…
4611 …ere error injection takes place. You can cycle this field value from 0 to 255 to access all locat…
4619 …ot supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved.
4623 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4633 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4637 …pported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved.
4642 …the read value of the class_code register of the configuration space. The 24-bit Class Code regist…
4647 … (0x1<<0) // Set this bit to enable the core to enter RASD…
4649 … (0x1<<1) // Set this bit to enable the core to bring the …
4652 … pointers in the PCIE configuration space and allows each extra capability to be independently dis…
4669 … (0x1<<0) // Set this bit to take the core out of…
4686 …tes function does not perform an internal reset when transitioning from D3 to D0. the value is ref…
4713 …he configuration space. This value may be used by the completion processor to determine the data v…
4722 …he configuration space. This value may be used by the completion processor to determine the addres…
4724 … (0x7fffff<<0) // Only bit 0 is currently defined - remote scaled flow c…
4730 …ace. The lower two bits [1:0] are hard wired to zero. This value may be used by the completion pro…
4748 … (0x1<<0) // PTM enable. When set, this function is permitted to participate in the P…
4776 …to update enabled. When enabled, PTM Requester will automatically attempt to update its context e…
4778 …ster start update. When set the PTM Requester will attempt a PTM Dialogue to update it's context;…
4780 …ll go high at 100us (The Long Timer Value is ignored). There is no change to the 1us timer. The r…
4818 …- 0xF_FFFF) when the fus__bar2_size_conf is intact. When the fuse is blown, the CNXXXX advertises …
4826 … (0x7<<0) // BAR Index. Points to BAR2.
4832 …S = 0x1F). The BAR is disabled at runtime by writing all zeros through PEM()_CFG_WR to this field.
4835 …ddress registers located at 10h in configuration space is used to map the function's MSI-X table i…
4837 …ss contained by one of the functions Base address registers to point to the base of the MSI-X tabl…
4847 …ddress registers located at 10h in configuration space is used to map the function's MSI-X PBA int…
4849 …ss contained by one of the functions Base address registers to point to the base of the MSI-X PBA …
4859 …to host software driver. Typically 0x0 would indicate to the host driver that CNXXXX firmware is n…
4864 …t when set, hides any PCIE spec 2.0 defined registers (bits) and enables design to be 1.1 compliant
4866 …the ASPM optionality bit in the Link cap register. This bit is recommended to be set for newer PCI…
4885 …8) // This controls value in configuration space and allows FLR capability to be advertized by DUT.
4890 … is in FLR state. Func can be brought out of FLR state either by writing 1 to this register (at le…
4894 …g to this PF should be flushed. Software should clear this bit within 1 second of VF Enable being …
4918 …his bit enables the advertisement of bar_3 as a 32-bit address. The value of this bit maps directl…
4920 …<5) // This bit when set is reflected in bit 3 of bar_3 and indicates that the BAR is pre-fetchable
4925 … Timeout Ranges Supported. Controls value in same field in the config space 0xF- Ranges A,B,C and D
4931 …is defined in version.v. When this bit is set, IDO feature is made visible to external config acce…
4935 …to set this value to 2 or 3(also supported using Messages) This bit is valid only if PCIE_OBFF_SUP…
4951 …his bit enables the advertisement of bar_5 as a 32-bit address. The value of this bit maps directl…
4953 …it when set is reflected in bit 3 of bar_5 and indicates that the BAR is pre-fetchable. This regis…
5052 … (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mo…
5054 …me in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, bef…
5058 …me in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, bef…
5063 … (0xfffff<<0) // This field is provided to program the cap ID a…
5084 …are compared against the user defined address range before it is forwarded to user. If requests do…
5088 …is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range …
5090 …is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range …
5096 …are compared against the user defined address range before it is forwarded to user. If requests do…
5100 …is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range …
5102 …is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range …
5116 … is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. Al…
5123 … (0x1<<4) // when Set, it indicates function will operate with Bar sized to 1M. Value programmed…
5125 … (0x1<<5) // when Set, it indicates function will operate with Bar sized to 2M. Value programmed…
5127 … (0x1<<6) // when Set, it indicates function will operate with Bar sized to 4M. Value programmed…
5129 … (0x1<<7) // when Set, it indicates function will operate with Bar sized to 8M. Value programmed…
5131 … (0x1<<8) // when Set, it indicates function will operate with Bar sized to 16M. Value programme…
5133 … (0x1<<9) // when Set, it indicates function will operate with Bar sized to 32M. Value programme…
5135 … (0x1<<10) // when Set, it indicates function will operate with Bar sized to 64M. Value programme…
5137 … (0x1<<11) // when Set, it indicates function will operate with Bar sized to 128M. Value programm…
5139 … (0x1<<12) // when Set, it indicates function will operate with Bar sized to 256M. Value programm…
5141 … (0x1<<13) // when Set, it indicates function will operate with Bar sized to 512M. Value programm…
5143 … (0x1<<14) // when Set, it indicates function will operate with Bar sized to 1G. Value programmed…
5148 …sponding bits in the ari_control_register. This field should be programmed to indicate the next fu…
5156 …_VF_NUM register in the tl_reg private register space. Each PF is expected to have a multiple of 8…
5163 …s bit enables the advertisement of VF BAR0 as a 64-bit address. The value of this bit maps directl…
5165 … when set is reflected in bit 3 of VF BAR0 and indicates that the BAR is pre-fetchable. This regis…
5171 …s bit enables the advertisement of VF BAR2 as a 64-bit address. The value of this bit maps directl…
5173 … when set is reflected in bit 3 of VF BAR2 and indicates that the BAR is pre-fetchable. This regis…
5181 …ing bits in the SRIOV Extended Capability Cfg register. This field is used to describe vendor spec…
5183 …ter. This field indicates page sizes supported by the PF. PFs are required to support 4k, 8K, 64K,…
5185 …to be independently disabled by manipulation of the next pointer values. The read values for each …
5189 …to the PF Default value of the link list is adv err, which has to be present always to allow exten…
5192 …re of PF configuration space is used to map the function's MSI-X table into memory space. All the …
5194 …e of the functions Base address registers to point to the base of the MSI-X table . All the VF's t…
5197 …ture in PF configuration space is used to map the VF's's MSI-X PBA into memory space. All the VF's…
5199 …ress contained by one of the functions Base address registers to point to the base of the MSI-X PBA
5209 …s bit enables the advertisement of VF BAR4 as a 64-bit address. The value of this bit maps directl…
5211 … when set is reflected in bit 3 of VF BAR4 and indicates that the BAR is pre-fetchable. This regis…
5213 …ograms the first VF allocation for a PF. All the VFs within IP are assumed to reside in a contiguo…
5214 …UM for PF is encoded in this register. The number of VFs assigned to a PF is assumed to be a multi…
5217 …his field describes the number of System pages needed by VF BAR0 belonging to PF. User Page Size(U…
5219 …his field describes the number of System pages needed by VF BAR2 belonging to PF. User Page Size(U…
5221 …his field describes the number of System pages needed by VF BAR4 belonging to PF. User Page Size(U…
5226 …ter. This field qhen Set, indicates the Untranslated Address always aligns to a 4K byte boundary. …
5235 … is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. Al…
5244 … or payload size changes. If the user changes this value they should refer to the PCIe specificati…
5246 … or payload size changes. If the user changes this value they should refer to the PCIe specificati…
5249 …to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-7…
5251 …to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-4…
5260 …the link to the state specified by [LINK_STATE]. The force link pulse triggers link renegotiation.…
5262 …0x3f<<16) // Link state. The link state that the PCI Express bus is forced to when bit 15 (force l…
5264 …to logical idle symbol, SKP OS to logical idle symbol, and FTS sequence to SKP OS to do deskew for…
5267 … (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe. Note: This reg…
5269 … (0xf<<8) // Forced Link Command. The link command that the core is forced to transmit when you se…
5271 …to allow your software to force the LTSSM state machine into a specific state, and to force the co…
5273 … (0x3f<<16) // Forced LTSSM State. The LTSSM state that the core is forced to when you set the FOR…
5275 …to D-state register to go low-power. This register is intended for applications that do not let th…
5278 … (0xff<<0) // ACK frequency. The number of pending ACKs specified here (up to 255) before sending …
5280 …to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered sets that a…
5282 …to be transmitted when transitioning from L0s to L0 when common clock is used. The maximum number …
5284 … (0x7<<24) // L0s entrance latency. Values correspond to: 0x0 = 1 ms. 0x1 = …
5286 … (0x7<<27) // L1 entrance latency. Values correspond to: 0x0 = 1 ms. 0x1 = …
5288 …ve in L0s. Allow core to enter ASPM L1 even when link partner did not go to L0s (receive is not in…
5290 … 0x00070cUL //Access:RW DataWidth:0x20 // Ack Frequency and L0-L1 ASPM Control Regis…
5291 …to 255) before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature is tur…
5293 …to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a…
5295 …to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a…
5297 …to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7…
5299 … Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 …
5301 … (0x1<<30) // ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has …
5304 … (0x1<<0) // Other message request. When software writes a one to this bit, the PCI Ex…
5308 …->1 transition, the PCIe core sends TS ordered sets with the loopback bit set to cause the link pa…
5310 … (0x1<<3) // Reset assert. Triggers a recovery and forces the LTSSM to the hot reset state …
5318 … (0x1<<7) // Fast link mode. Sets all internal timers to fast mode for simula…
5322 … to limit the number of lanes that the PCIe will attempt to use. If the value of 0xF set by the ha…
5335 …ites a '1' to this bit, the core transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VEN…
5339 …-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during C…
5341 … (0x1<<3) // Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state …
5347 …to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use sh…
5351 …to connect to the link partner. When you have unused lanes in your system, then you must change th…
5370 … (0xf<<27) // Set the implementation-specific number of la…
5372 … (0x1<<31) // Disable lane-to-lane deskew. Disables the internal lane-t…
5375 …or Transmit (not supported for x16). Optional feature that causes the core to insert skew between …
5381 … (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the intern…
5384 … (0xff<<0) // Max number of functions supported. Used for SR-IOV.
5397 …-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in inc…
5399 …n increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For…
5403 …to 1b. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Sc…
5406 …to wait between transmitting SKP ordered sets. Note that the controller actually waits the number …
5445 …to wait between transmitting SKP ordered sets. Note that the core actually waits the number of sym…
5451 …- 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to al…
5460 … (0x1<<3) // Mask core filter to handle flush request.
5492 … 0x000734UL //Access:R DataWidth:0x20 // Transmit Non-Posted FC Credit Stat…
5493 … (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-poste…
5495 … (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-post…
5514 …e credit queue overflow. Indicates insufficient buffer space available to write to the P/NP/CPL cr…
5518 …ation queue write error. Indicates insufficient buffer space available to write to the serializati…
5520 …lization queue read error. Indicates the serialization queue has attempted to read an incorrectly …
5522 …ill override the FC latency timer value that the core calculates according to the PCIe specificati…
5524 …ill override the FC latency timer value that the core calculates according to the PCIe specificati…
5533 …ill override the FC latency timer value that the core calculates according to the PCIe specificati…
5535 …ill override the FC latency timer value that the core calculates according to the PCIe specificati…
5547 …xff<<0) // WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R
5549 …xff<<8) // WRR Weight for VC1. Note: The access attributes of this field are as follows: - Dbi: R
5551 …ff<<16) // WRR Weight for VC2. Note: The access attributes of this field are as follows: - Dbi: R
5553 …ff<<24) // WRR Weight for VC3. Note: The access attributes of this field are as follows: - Dbi: R
5565 …xff<<0) // WRR Weight for VC4. Note: The access attributes of this field are as follows: - Dbi: R
5567 …xff<<8) // WRR Weight for VC5. Note: The access attributes of this field are as follows: - Dbi: R
5569 …ff<<16) // WRR Weight for VC6. Note: The access attributes of this field are as follows: - Dbi: R
5571 …ff<<24) // WRR Weight for VC7. Note: The access attributes of this field are as follows: - Dbi: R
5580 …-buffer configuration, writable through PEM()_CFG_WR. However, the application must not change thi…
5588 …he TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration,…
5590 …ines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration,…
5592 … 0x000748UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Posted Rec…
5593 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5595 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5603 …ly in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ord…
5605 …eues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs …
5614 …-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 2…
5616 … (0x3<<24) // VC0 scale non-posted header credits.
5618 … (0x3<<26) // VC0 scale non-posted data credits.
5622 … 0x00074cUL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Non-Posted Receive…
5623 …-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segm…
5625 …-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the …
5640 …-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 2…
5648 … 0x000750UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Completion…
5649 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5651 …or VC0, used only in the segmented-buffer configuration. Note: The access attributes of this fiel…
5660 …to block TLPS. By default TL will send all pending dma requests and completions when PM requests i…
5682 … (0x1<<12) // This bit if set will force DUT to not reset its RID af…
5688 …1<<15) // If set, completions received for a function which is in FLR will not be directed to user.
5690 … (0x1<<16) // If set, this causes func0 to be hidden
5694 … (0x1<<18) // when set, forces MSI_En to low.
5700 … (0x1<<21) // When set, it enables WAKE generation in any L-state, when PME_EN bi…
5706 … (0x1<<24) // When set, it prevents PM from re-entering L1 when programmed to non-D0 p…
5708 … (0x1<<25) // This bit is used by PCIE SERDES to determine source of …
5714 … (0x1<<28) // In RC mode, when set, it enables pcie_scnd_rst_b to be asserted when Sec…
5716 … (0x1<<29) // In RC mode, when set, it forces pcie_scnd_rst_b to be asserted
5721 … (0x1<<0) // Enable check to determine if mem requests do not have upper 32 bits o…
5723 … (0x1<<1) // Enable checks to determine TLP doesn …
5725 … (0x1<<2) // Enable check to determine if the len…
5727 … (0x1<<3) // Enable check to determine if receive…
5733 … (0x1<<6) // Enable checks to determine completion…
5735 … (0x1<<7) // Enable Check to determine if the rou…
5743 … (0x1<<11) // This bit is used to disable function 1. …
5745 … (0x1<<12) // This bit is used to disable function 2.
5747 … (0x1<<13) // This bit is used to disable function 3.
5749 … (0x1<<14) // This bit is used to disable function 4.
5751 … (0x1<<15) // This bit is used to disable function 5.
5753 … (0x1<<16) // This bit is used to disable function 6.
5755 … (0x1<<17) // This bit is used to disable function 7.
5759 …n completions and not wait for LTR message to be sent first even though device state may have chan…
5767 … (0x1<<23) // This bit instructs h/w to send an LTR message …
5769 … (0x1<<24) // This bit enables CRS status to be automatically cleared when internal timer is …
5771 … (0x1<<25) // This bit instructs h/w to send an LTR message …
5773 …to ASPM L1 when ASPM LTR is enabled. The unit of this timer is us. This time is in addition to the…
5775 … (0x1<<30) // This bit instructs h/w to send an LTR message …
5777 … (0x1<<31) // This bit instructs h/w to immediately send an …
5843 …to inform the link partner about the PHY's ability to recover synchronization after a low power st…
5845 …to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Ind…
5847 …to logical Lane0 by the flip operation performed in detect. 0x0 = Reserved. 0x1 = Connect lo…
5853 …s the voltage level that the PHY should drive. When set to one, indicates low swing. When set to 0…
5855 …ance receive bit. When set to one, signals LTSSM to transmit TS ordered sets with the compliance r…
5857 … (0x1<<20) // Set the deemphasis level for upstream ports. 0 = -6 dB. 1 = -3.5 dB.
5859 …to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state a…
5862 …to inform the link partner about the PHY's ability to recover synchronization after a low power st…
5864 …to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Ind…
5866 …to logical Lane0 by the flip operation performed in Detect. Allowed values are: - 3'b000: Connect…
5868 …to include the hardware for this feature in the core. For more details, see the 'Lane Reversal' ap…
5870 …to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is ini…
5872 …ld. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Note: The …
5874 …to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "…
5876 …to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the lin…
5878 …to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state a…
5885 …re not released by IP if FIFO at the DL-TL boundary reaches a critical threshold. This feature all…
5887 …-posted credit is available to user when bit is set. The credits to user are artificially reduced …
5891 …ables entry into L1, due to function being in D0unint state. When set, it would require all enable…
5897 … (0x1<<16) // This bit when set prevents DUT from entering L1 due to being in non-d0 state.
5899 …to prevent link from re-entering L1, when link comes out of L1 into L0 due to PM_PME. The default …
5909 …cess:RW DataWidth:0x20 // PHY Control Register. Memory mapped register to cfg_phy_control GPIO…
5910 …/Access:RW DataWidth:0x20 // This register stores the status of errors to generate pcie_err_at…
5982 … (0x1<<0) // This bit is used to disable function 8.
5984 … (0x1<<1) // This bit is used to disable function 9.
5986 … (0x1<<2) // This bit is used to disable function 10.
5988 … (0x1<<3) // This bit is used to disable function 11.
5990 … (0x1<<4) // This bit is used to disable function 12.
5992 … (0x1<<5) // This bit is used to disable function 13.
5994 … (0x1<<6) // This bit is used to disable function 14.
5996 … (0x1<<7) // This bit is used to disable function 15.
6003 … Values are multiplied by this scale field to yield an absolute time value expressable in a range …
6011 … Values are multiplied by this scale field to yield an absolute time value expressable in a range …
6020 … Values are multiplied by this scale field to yield an absolute time value expressable in a range …
6028 … Values are multiplied by this scale field to yield an absolute time value expressable in a range …
6037 … Values are multiplied by this scale field to yield an absolute time value expressable in a range …
6045 … Values are multiplied by this scale field to yield an absolute time value expressable in a range …
6054 … Values are multiplied by this scale field to yield an absolute time value expressable in a range …
6062 … Values are multiplied by this scale field to yield an absolute time value expressable in a range …
6131 …/Access:RW DataWidth:0x20 // This register stores the status of errors to generate pcie_err_at…
6257 …/Access:RW DataWidth:0x20 // This register stores the status of errors to generate pcie_err_at…
6321 … (0x7<<0) // Route the interrupt pin for Function 0 to any of INTA to INTD or no i…
6323 … (0x7<<3) // Route the interrupt pin for Function 1 to any of INTA to INTD or no i…
6325 … (0x7<<6) // Route the interrupt pin for Function 2 to any of INTA to INTD or no i…
6327 … (0x7<<9) // Route the interrupt pin for Function 3 to any of INTA to INTD or no i…
6329 … (0x7<<12) // Route the interrupt pin for Function 4 to any of INTA to INTD or no i…
6331 … (0x7<<15) // Route the interrupt pin for Function 5 to any of INTA to INTD or no i…
6333 … (0x7<<18) // Route the interrupt pin for Function 6 to any of INTA to INTD or no i…
6335 … (0x7<<21) // Route the interrupt pin for Function 7 to any of INTA to INTD or no i…
6340 … (0x7<<0) // Route the interrupt pin for Function 0 8o any of INTA to INTD or no interrupt.
6342 … (0x7<<3) // Route the interrupt pin for Function 9 to any of INTA to INTD or no i…
6344 … (0x7<<6) // Route the interrupt pin for Function 10 to any of INTA to INTD or no i…
6346 … (0x7<<9) // Route the interrupt pin for Function 11 to any of INTA to INTD or no i…
6348 … (0x7<<12) // Route the interrupt pin for Function 12 to any of INTA to INTD or no i…
6350 … (0x7<<15) // Route the interrupt pin for Function 13 to any of INTA to INTD or no i…
6352 … (0x7<<18) // Route the interrupt pin for Function 14 to any of INTA to INTD or no i…
6354 … (0x7<<21) // Route the interrupt pin for Function 15 to any of INTA to INTD or no i…
6359 …he Serdes MDIO regs in reset till PERST_N is released. Default behavior is to release Serdes MDIO …
6361 …will keep the micro in reset till PERST_N is released. Default behavior is to release micro from r…
6365 … (0x1<<3) // Tthis bit when set will allow bit 2 value to propogate to Serdes. This …
6369 …0x1<<5) // For gen3 serdes, this bit when set will allow bit 4 value to propogate to uc reset. Thi…
6373 …ta, allows interpreting Rx messages with routing errors or hdr type errors to be UR instead of mal…
6378 … (0x7f<<0) // Min number of PM clocks to wait after WAKE# sig…
6382 … (0x7f<<8) // Max number of PM clocks to wait after WAKE# signal transition to d…
6389 …if func1 is hidden either due to hide_func_1 pad being driven high or due to programming bit in TL…
6391 … (0x1<<1) // Set if func2 is hidden either due to hide_func_2 pad being driven high or due t…
6393 … (0x1<<2) // Set if func3 is hidden either due to hide_func_3 pad being driven high or due t…
6395 … (0x1<<3) // Set if func4 is hidden either due to hide_func_4 pad being driven high or due t…
6397 … (0x1<<4) // Set if func5 is hidden either due to hide_func_5 pad being driven high or due t…
6399 … (0x1<<5) // Set if func6 is hidden either due to hide_func_6 pad being driven high or due t…
6401 … (0x1<<6) // Set if func7 is hidden either due to hide_func_7 pad being driven high or due t…
6403 … (0x1<<7) // Set if func8 is hidden either due to hide_func_8 pad being driven high or due t…
6405 … (0x1<<8) // Set if func9 is hidden either due to hide_func_9 pad being driven high or due t…
6407 … (0x1<<9) // Set if func10 is hidden either due to hide_func_10 pad being driven high or due …
6409 … (0x1<<10) // Set if func11 is hidden either due to hide_func_11 pad being driven high or due …
6411 … (0x1<<11) // Set if func12 is hidden either due to hide_func_12 pad being driven high or due …
6413 … (0x1<<12) // Set if func13 is hidden either due to hide_func_13 pad being driven high or due …
6415 … (0x1<<13) // Set if func14 is hidden either due to hide_func_14 pad being driven high or due …
6417 … (0x1<<14) // Set if func15 is hidden either due to hide_func_15 pad being driven high or due …
6514 …/Access:RW DataWidth:0x20 // This register stores the status of errors to generate pcie_err_at…
6641 …gating feature when there is no receive traffic, receive queues and pre/post-queue pipelines are e…
6643 …/Access:RW DataWidth:0x20 // This register stores the status of errors to generate pcie_err_at…
6707 … (0x1<<0) // Gen3 receiver impedance ZRX-DC not compliant.
6709 …r for Gen3 data rate. The Gen3 scrambler/descrambler within the core needs to be disabled when the…
6711 … (0x1<<9) // Equalization phase 2 and phase 3 disable. This applies to downstream ports onl…
6719 … (0x1<<13) // The controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adap…
6727 …to Recovery state to perform Gen4 equalization. Link stays in Gen3 rate and DSP sends DLLPs to USP…
6729 …ate. If this register set to 0, USP sends 8GT EQ TS2. If this register set to 1, USP does not send…
6735 …-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is us…
6736 …-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defin…
6738 …4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the core needs to be disabled when the…
6740 …to downstream ports only. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and…
6744 … // Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalizatio…
6746 …to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during V…
6748 …to '1', the core as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and ev…
6801 …/Access:RW DataWidth:0x20 // This register stores the status of errors to generate pcie_err_at…
6845 …to this function will receive UR. 0x3 = PF is partially hidden. Config write accesses to this fu…
6847 … (0x3<<2) // PF1 hide control. Similar to [PF0].
6849 … (0x3<<4) // PF2 hide control. Similar to [PF0].
6851 … (0x3<<6) // PF3 hide control. Similar to [PF0].
6853 … (0x3<<8) // PF4 hide control. Similar to [PF0].
6855 … (0x3<<10) // PF5 hide control. Similar to [PF0].
6857 … (0x3<<12) // PF6 hide control. Similar to [PF0].
6859 … (0x3<<14) // PF7 hide control. Similar to [PF0].
6861 … (0x3<<16) // PF8 hide control. Similar to [PF0].
6863 … (0x3<<18) // PF9 hide control. Similar to [PF0].
6865 … (0x3<<20) // PF10 hide control. Similar to [PF0].
6867 … (0x3<<22) // PF11 hide control. Similar to [PF0].
6869 … (0x3<<24) // PF12 hide control. Similar to [PF0].
6871 … (0x3<<26) // PF13 hide control. Similar to [PF0].
6873 … (0x3<<28) // PF14 hide control. Similar to [PF0].
6875 … (0x3<<30) // PF15 hide control. Similar to [PF0].
6877 …:0x20 // The core supports the hiding of implemented physical functions. To enable this feature,…
6878 …G accesses to this function will receive UR. 0x11: PF is Partially Hidden. CfgWr accesses to this …
6911 … (0xf<<0) // Feedback mode. 0 = Direction of change. 1 = Figure of merit. 2-15 = Reserved.
6915 …to the assertion of RxEqEval: 0 = Abort the current evaluation; stop any attempt to modify the rem…
6925 … (0x1<<26) // Request core to send back-to-back EIEOS in Recovery.RcvrLock state unt…
6927 …or Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Con…
6928 … (0xf<<0) // Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserv…
6930 …- 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: …
6932 …to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the r…
6934 …- 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: P…
6936 …ter, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include…
6940 …equest core to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients ma…
6943 …imum time (in ms) to remain in EQ master phase. The LTSSM stays in EQ master phase for at least th…
6945 …to the remote partner in phase 2 for USP and phase 3 for DSP. Therefore, the remote partner will n…
6947 … (0xf<<10) // Convergence window aperture for C-1. Precursor coeffici…
6951 …to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control Re…
6952 …imum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least th…
6954 …to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0, EQ Master is performed without sending any…
6956 …TA_K2 (0xf<<10) // Convergence Window Aperture for C-1. Pre-cursor coefficient…
6958 …K2 (0xf<<14) // Convergence Window Aperture for C+1. Post-cursor coefficients m…
6961 …-Posted passing posted ordering rule control. Determines if a NP can pass halted P queue. 0x0 = …
6963 …lted P queue. 0x0 = CPL can not pass P (recommended). 0x1 = CPL can pass P. 0x2-0xFF = Reserved.
6966 …<0) // Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue…
6968 … Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1…
6971 … (0xffff<<0) // Loopback rxvalid (lane enable - 1 bit per lane).
6984 … (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This reg…
6987 …5 (0x1<<0) // Write to RO registers using D…
6989 …to be the controller. 0x0 = The controller drops all incoming I/O or Mem (after correspondin…
6991 …to request TLPs (with UR filtering status) that are chosen to forward to the application (when [DE…
6993 …mer values are: A value from 24,000 to 31,000 symbol times when extended synch is 0. A value…
6999 … 0x0008bcUL //Access:RW DataWidth:0x20 // DBI Read-Only Write Enable Reg…
7000 …to RO Registers Using DBI. When you set this field to "1", then some RO and HwInit bits are writab…
7005 …to configuration state through recovery state when this bit is set. If PCIEEP_RAS_EINJ_CTL6PE[LT…
7007 … (0x1<<7) // Upconfigure support. The core sends this value to the link upconfigure…
7009 … 0x0008c0UL //Access:RW DataWidth:0x20 // UpConfigure Multi-lane Control Register…
7010 …to: - 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configurat…
7012 …to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_c…
7014 …Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: Th…
7016 …x20 // This register is reserved for internal use. You should not write to this register and ch…
7017 …Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. 0x0 = Rx EIOS …
7019 …0 = Core waits for the PHY to assert phy_mac_pclkack_n before exiting L1. 1 = Core exits L1 wit…
7021 … waits for the PHY to acknowledge transition to P1 before entering L1. 1 = Core does not wait f…
7025 …ister. This register is reserved for internal use. You should not write to this register and ch…
7026 …to perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN …
7028 …- 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core wai…
7031 … (0x7fffffff<<0) // This number selects one entry to delete from the targ…
7033 …This is a one-shot bit. Writing a one triggers the deletion of the target completion LUT entry tha…
7035 … received application completions (on XALI0/1/2) corresponding to previously received non-posted r…
7036 … (0x7fffffff<<0) // This number selects one entry to delete of the TRGT_C…
7038 … A '1' write to this bit triggers the deletion of the target completion LUT entry that is specifie…
7046 … (0xf<<0) // Split table contents for tag0. this corresponds to Device_no[4:1] of PC…
7052 … (0x3<<10) // Split table Contents for tag0. This corresponds to attr field in PCIE h…
7054 … (0x1fff<<12) // Split table contents for tag0. This corresponds to the Byte count field.
7056 … (0x7f<<25) // Split table contents for tag0. This corresponds to the Lower address fi…
7058 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7059 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7060 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7061 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7062 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7063 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7064 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7065 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7066 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7067 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7068 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7069 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7070 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7071 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7072 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7073 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7074 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7075 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7076 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7077 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7078 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7079 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7080 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7081 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7082 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7083 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7084 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7085 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7086 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7087 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7088 …0x20 // This register is same as tl_status_0, except that it corresponds to split completion tab…
7096 … (0xff<<24) // Non-Posted Data credits a…
7105 …BB (0xf<<28) // Non-Posted Data credits a…
7114 … (0xff<<24) // Non-Posted Data credits c…
7123 …BB (0xf<<28) // Non-Posted Data credits c…
7134 … (0x1<<16) // Available Non-posted credit for tar…
7137 …B (0xff<<0) // Non-Posted header credits…
7139 …B (0xff<<8) // Non-Posted data credits a…
7146 … (0xf<<0) // Target Non-Posted request State …
7175 …to assume that VFs are residing on a bus number that is different than the one on which the PFs re…
7177 …UT from automatically setting VF offset to be greater than 256(when vf_nextbus, bit 0 is set). Use…
7179 …to automatically adjust the VF BAR size based on the System Page Size programming. When system Pag…
7182 …non-posted data credits since the last request for immediate update that are needed to force an im…
7184 …) // The number of accumulated non-posted header credits since the last request for immediate upda…
7186 …-posted credits are flagged for immediate update. When clear, the credits may or not be updated un…
7188 …the forced update if there are outstanding non-posted credits to update. The resolution on the tim…
7190 …-posted credit updates are forwarded to the DLL as immediate updates after a given number of micro…
7193 …d data credits since the last request for immediate update that are needed to force an immediate u…
7195 …header credits since the last request for immediate update that are needed to force an immediate u…
7197 …(If clear and infinite credits are advertised, the thresholds are not used to force immediate upda…
7199 …forced update if there are outstanding posted credits to update. The resolution on the timer is +/…
7201 …to the DLL as immediate updates after a given number of microseconds (see below) elapses since the…
7219 … (0x3ff<<0) // Length in bytes to which VDM messages are restricted to
7223 …1<<16) // VDM is enabled when this bit is set. PCIe will pass VDM messgaes to user interface when …
7226 … (0x1<<0) // This bit when set, forces hardware to generate a PTM Reque…
7228 … field when set will prevent hardware from generating attention when PTM req- response handshake h…
7232 … set inidcates that the PTM req-response handshake initiated by software has completed. This bit i…
7234 … (0x1<<31) // This field when set inidcates that the PTM req-response handshake co…
7244 …to '1' enables the tx TLP statistics collection. Hardware will count various types of TLPs in the …
7248 …seconds. When it is set to '0', software has to clear the reg_ttx_tlp_stat_en bit to stop the oper…
7251 …LP type that hardware can detect. Bit[7] is enable bit. If this bit is set to 1, then hardware wil…
7253 …P type that hardware can detect. Bit[15] is enable bit. If this bit is set to 1, then hardware wil…
7255 …P type that hardware can detect. Bit[23] is enable bit. If this bit is set to 1, then hardware wil…
7257 …P type that hardware can detect. Bit[31] is enable bit. If this bit is set to 1, then hardware wil…
7260 …p_type_0. Bits[7:0] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding…
7264 …_type_1. Bits[14:8] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding…
7268 …type_2. Bits[22:16] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding…
7272 …type_3. Bits[30:24] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding…
7274 …ber of TLPs that have been trasmitted. It is cleared when reg_ttx_tlp_stat_en goes from '0' to '1'.
7275 …ber of TLPs that have been trasmitted. It is cleared when reg_ttx_tlp_stat_en goes from '0' to '1'.
7277 …to '1' enables the rx TLP statistics collection. Hardware will count various types of TLPs program…
7281 …seconds. When it is set to '0', software has to clear the reg_trx_tlp_stat_en bit to stop the oper…
7284 …LP type that hardware can detect. Bit[7] is enable bit. If this bit is set to 1, then hardware wil…
7286 …P type that hardware can detect. Bit[15] is enable bit. If this bit is set to 1, then hardware wil…
7288 …P type that hardware can detect. Bit[23] is enable bit. If this bit is set to 1, then hardware wil…
7290 …P type that hardware can detect. Bit[31] is enable bit. If this bit is set to 1, then hardware wil…
7293 …p_type_0. Bits[7:0] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding…
7297 …_type_1. Bits[14:8] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding…
7301 …type_2. Bits[22:16] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding…
7305 …type_3. Bits[30:24] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding…
7307 …ber of TLPs that have been trasmitted. It is cleared when reg_trx_tlp_stat_en goes from '0' to '1'.
7308 …ber of TLPs that have been trasmitted. It is cleared when reg_trx_tlp_stat_en goes from '0' to '1'.
7323 …<<0) // Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7325 …<10) // Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7327 …/ Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7329 …) // No Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W
7331 …) // No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W
7333 …o Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W
7336 …he aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time duri…
7339 …to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY ha…
7346 … (0x3<<6) // Max delay (in 1 us units) between a MAC request to remove the clock on …
7389 … (0xff<<0) // When non-zero, indicates the maximum number of entries collected an…
7393 …dicates the FIFO address of the trigger location (where data corresponding to the trigger cycle is…
7397 … (0x1<<26) // Asserted when attn signal is generated and active. Write 1 to clear the attn.
7399 … (0x1<<27) // Enables to generate attention to trigger e…
7403 …the pretrigger buffer is filled, the trig_addr field is used to determine the amount of pre-trigge…
7407 … (0x1<<31) // When set by write, activates the DBG FIFO logic. To retrigger, this must…
7409 …000c04UL //Access:RW DataWidth:0x20 // Control and Status for accesses to DBG FIFO indirect re…
7422 … (0x1ff<<23) // Current write address to the external FIFO. B…
7424 …to the currently referenced indirect register via ind_raddr_reg or ind_waddr_reg. The registers ar…
7455 …- no FIFO selected to read by user if 001 - PL/DL FIFO is selected to read by user if 010 - TLDA…
7459 … (0x7<<12) // 000 - generic lane is selected 001 - predefined lane 1 010 - predefine…
7484 … (0x1<<8) // When set and in local mode, reads to PCIER_TLDA_RDFIFO_4 …
7486 … (0x1<<9) // When set, the FIFOs are linked in series to increase the depth o…
7488 … (0x1<<10) // When set, the FIFOs are linked in parallel to increase the width o…
7490 …nterface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
7494 …iggered, indicates that data at the trigger has been collected (as opposed to filtered out based o…
7496 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read fr…
7498 … (0x7f<<15) // The number of pre-trigger samples to keep. pretr…
7500 …FIFO write address at the time of the trigger. Use bit 13 of this register to determine if there w…
7502 … // Set if pretrigger data was expected and enough data samples were collected prior to the trigger
7506 … (0x1<<31) // When set by write, activates the TLDA logic. To retrigger, this must…
7521 … (0x7f<<24) // Current write address to the external FIFO.
7523 …to the currently referenced indirect register via ind_raddr_reg or ind_waddr_reg. Registers are mo…
7524 …ite reads of PCIER_TLDA0_RDFIFO_4, the data in these registers is advanced to the next half of the…
7525 … 0x000c50UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the FIFO
7526 … 0x000c54UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the FIFO
7527 … 0x000c58UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the FIFO
7528 … 0x000c5cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the FIFO
7534 … (0x1<<8) // When set and in local mode, reads to PCIER_TLDA_RDFIFO_4 …
7536 … (0x1<<9) // When set, this indicates the FIFOs are linked in series to increase the depth o…
7538 … (0x1<<10) // When set, this indicates the FIFOs are linked in parallel to increase the width o…
7540 …nterface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
7544 …iggered, indicates that data at the trigger has been collected (as opposed to filtered out based o…
7546 … (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read fr…
7548 … (0x7f<<15) // The number of pre-trigger samples to keep. pretr…
7550 …FIFO write address at the time of the trigger. Use bit 13 of this register to determine if there w…
7552 … // Set if pretrigger data was expected and enough data samples were collected prior to the trigger
7556 … (0x1<<31) // When set by write, activates the TLDA logic. To retrigger, this must…
7571 … (0x3f<<24) // Current write address to the external FIFO.
7573 …to the currently referenced indirect register via ind_raddr_reg or ind_waddr_reg. Registers are mo…
7574 …ite reads of PCIER_TLDA1_RDFIFO_4, the data in these registers is advanced to the next half of the…
7575 …000c70UL //Access:R DataWidth:0x20 // Bits [127:96] of the current half-data from the second …
7576 …x000c74UL //Access:R DataWidth:0x20 // Bits [95:64] of the current half-data from the second …
7577 …x000c78UL //Access:R DataWidth:0x20 // Bits [63:32] of the current half-data from the second …
7578 …0x000c7cUL //Access:R DataWidth:0x20 // Bits [31:0] of the current half-data from the second …
7582 … (0x1<<1) // PHY: Disable Inverse Polarity. Setting this bit to '1' disables the pol…
7596 … (0x1<<10) // PHY: Disable Electrical Idle Retrain. Setting this bit to '1' prevents link fr…
7598 … (0x1<<11) // DL: Disable Auto Credit Update. If this bit is set to '1', DL will not aut…
7600 … (0x1<<12) // DL:Disable hardware from triggering link retraining due to Replay timer roll ov…
7602 … (0x1<<13) // DL: Force L0 to L1. When this bit is set to '1', DL will send PM_Ente…
7606 …Force Receiver Detect All. When this bit is set to '1', internal Receiver Detected signals are for…
7610 … (0x1<<27) // DL: Force L0 to L2. When this bit is set to '1', DL will send PM_Ente…
7616 …/ PHY: Direct Recovery to Configuration State. When this bit is set to '1', LTSSM is directed to t…
7619 …time that DL doesn't have any TLP/DLLP to transmit before DL requests PL to enter L0s. The actual …
7625 …// When this bit is set, the software value will be used for UpdateFC Latency of Non-Posted credit.
7627 … (0x1<<10) // DL: When this bit is set to '1', Replay Timer wi…
7629 … (0x1<<11) // PHY: Force to TX L0s. Setting this bit to '1' forces LTSSM…
7633 … (0x1<<14) // This initiates Link re-training by directing PHY LTSSM to rec…
7637 …d, it is the time link doesn't have any activity. The actual time is equal to (MAX_DLP_L1_ENTRANCE…
7639 … before EP can initiate the next ASPM L1 request. The actual time is equal to (ASPM_L1_GAP * 256ns…
7641 … (0x1<<30) // Internal ASPM L1 Enable. When this bit is set to '1', hardware autono…
7643 … this bit is set to '1', user can directly control when to enter ASPM L1 using signal user_l1_ente…
7648 … (0x1<<2) // PHY: Disable SKP OS. When this bit is set to '1', periodic SKP OS…
7650 …ACK_LAT_TIMER. When this timer is disabled, ACK/NACK requests will be sent to PCIE bus as soon as …
7664 …1<<17) // DL: Enable Non-Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL w…
7678 … (0xfff<<0) // DL: Non-Posted Data for INITFC
7687 … (0x1<<8) // This bit is set to '1' if IP is configu…
7691 …DL: Minimum number of InitFC1 sets (i.e. P, NP, CPL) that DL will send before switching to InitFC2.
7700 … (0xffff<<16) // Reserved - always write 0
7703 …mbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calcul…
7705 …y for the replay timeout in symbol time. This delay is only applied to the hardware-calculated rep…
7707 …_BB (0x7ff<<21) // Reserved - always write 0
7712 …to the table in PCIE spec. Since the actual internal delay of the design is larger than the spec i…
7717 …mbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calcul…
7719 …y for the replay timeout in symbol time. This delay is only applied to the hardware-calculated rep…
7732 … (0x3ff<<12) // If DLP2TLP buffer fills up to the high water mark value, DL will send a fla…
7734 …to this high water mark value, DL will send a flag to TL restraining it from sending more Posted F…
7737 …mbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calcul…
7739 …y for the replay timeout in symbol time. This delay is only applied to the hardware-calculated rep…
7744 …to the table in PCIE spec. Since the actual internal delay of the design is larger than the spec i…
7751 …to the table in PCIE spec. Since the actual internal delay of the design is larger than the spec i…
7756 …of addresses that can be used to extend the debug bus0. First 2k belongs to PHY Second 2K belongs …
7758 …of addresses that can be used to extend the debug bus1. First 2k belongs to PHY Second 2K belongs …
7766 … (0x1<<31) // Enable GRC to control the driving of the debug bus. When this bit is set, it pr…
7769 …nsmitting a TLP. Generates pcie_err_att status to chip. This status is not cleared till a 1 is wri…
7781 … (0x1<<6) // Indicate un-decoded condition in de-framing l…
7791 … (0x1<<11) // Set if DL detects impossible condition to de-allocate entries in…
7799 … (0x1<<15) // DL TX Underrun. This bit is set to '1' if underrun occu…
7801 … (0x1<<16) // Detect DLLP with mismatched CRC-16 on receiving side.
7807 … (0x1<<19) // This signal is set to '1' when the TLP length that TL indicates to DL does …
7817 … (0x3ff<<0) // Total number of errors within 256us due to CRC16, LCRC, sequenc…
7837 … (0x3f<<0) // DL: Maximum time in microseconds that DL has to send at least one Up…
7839 … (0xff<<6) // DL: Maximum time in microseconds that DL has to send at least one Up…
7844 …to '1' to enable the T2D FIFO threshold feature. Depending on TL, DL bus width and clock relations…
7853 …ayfifo_testsize_sel is set to '1', this value is used as the Replay FIFO size. This value must be …
7855 …d2tfifo_testsize_sel is set to '1', this value is used as the D2T FIFO size. This value must be se…
7859 … (0x1<<30) // Replay FIFO Test Size Select. When this bit is set to '1', the value in re…
7861 … (0x1<<31) // D2T FIFO Test Size Select. When this bit is set to '1', the value in d2…
7865 … (0xffff<<0) // This value controls the register index sent to on the MDIO bus connected to the P…
7867 … (0xf<<16) // This value controls port address sent to on the MDIO bus connected to the P…
7869 … (0xfff<<20) // A write of '0' to these bits causes no action and allows the addr…
7874 … (0x1<<31) // This bit must be written as a '1' to initiate write cycle…
7879 …e, this bit will read as '1'. This bit is automatically cleared by a write to the mdio_addr regist…
7881 …8-bit header information that is sent to TL logic to build a TLP. The header information is passed…
7886 …xff<<0) // ATE TLP Count. Specify the number of TLP's to be transferred. When ate_tlp_go is set to…
7888 … ATE TLP Nullify. When this bit is set to '1', an internal signal is asserted together with the la…
7897 …et to '1', the TX User Interface is bypassed and internal logic generates packets to TL logic. Aft…
7901 …to read trx_reg_sb_op_done (bit[31]). If trx_reg_sb_op_done register value is 1, it indicates that…
7905 …not match with received TLP header. This bit can be cleared by writing '1' to reg_trx_clr_rx_tlp_s…
7907 …o not match with received TLP data. This bit can be cleared by writing '1' to reg_trx_clr_rx_tlp_s…
7911 …to ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x111c). trx_reg_err_tlp_num indicates the numbe…
7915 …to number of TLPs transmitted (ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x111c). This regist…
7935 … (0x1<<30) // This bit must be written as a '1' to initiate read cycle to the pmi_…
7937 … (0x1<<31) // This bit must be written as a '1' to initiate write cycle…
7944 …e, this bit will read as '1'. This bit is automatically cleared by a write to the serdes_pmi_wdata…
7967 … (0x1<<0) // Request a width change (ie -make the link wider, …
7969 … (0x1<<1) // Request a speed change (ie -make the link fast or…
7973 … (0x1<<5) // Enable the shortcut transition from Config.Complete to Recovery.RcvrLock So…
7975 … (0x1<<6) // For multi-lane links on a 2.0 compliant core, enable advertisement of …
7993 …dified Compliance Pattern must be of the same polarity (no mixed polarity) for the receiver to lock
7999 …iance when generating the Modified Compliance pattern and at least one lane goes to electrical idle
8001 … to Polling.Compliance from Polling.Active. This also causes the Compliance Receive bit in the out…
8005 …sis set in the Detect state (this propagates to the PCIe Serdes via the TxDeemph signal. 0 == -6 d…
8009 … (0x1<<24) // Directed transition from Loopback or Polling.Compliance states to Detect state
8011 … (0x1<<25) // Directed transition from L1 state to Recovery or L2 state to Detect.
8015 … (0x1<<27) // Disable use of electrical idle in Recovery.Speed - only use inferred el…
8017 … (0x1<<28) // For 2.0 compliant systems, default to the optional behavio…
8019 … (0x1<<29) // Disable the ability to compensate for lane reversal in multi-l…
8021 …0x1<<30) // Enable the clearing of directed_speed_change on the transition to Recovery.Idle. This …
8026 … (0x1<<0) // Force the PIPE interface to be 16-bit, even in Gen …
8028 …_BB (0x1<<1) // Disable entry to Polling.Compliance
8030 … (0x1<<2) // Enable the PIPE-style powerdown of unused lanes in a multi-…
8032 … (0x1<<3) // Enable the auxilliary powerdown of unused lanes in a multi-lane link.
8034 … (0x1<<4) // Initiate PL changes required for a far-end loopback
8036 …ation that cycles through the rates, deemphasis, and presets is reset back to the first configurat…
8038 …ts the transient misalignment of data at the end of L0 (when transitioning to L0s or L1). When cle…
8040 …to set the delay in clocks for the electrical idle signal (on the PIPE interface) so that EIDL OS …
8042 … (0x1<<12) // This signal goes to the PCIe Serdes to enable the PLL to p…
8044 … of received TS2 in Recovery.RcvrCfg for inferred electrical idle. This is to mimic the "Gen2 0.7 …
8046 … (0x3<<14) // This field programs the number of EIE symbols to send before the firs…
8056 … (0xf<<20) // The depth of the inferred electrical idle filter used to "deskew" the detecti…
8064 …27) // When training is sped up using bits 25 or 26, extend the timeout for Polling.Active to 72 us
8066 …x1<<28) // Speed up Polling.Active by restricting the number of TS1s to transmit to 32 (instead of…
8068 … (0x1<<29) // Clear the LTSSM histogram. Not self-clearing
8070 … (0x1<<30) // Clear the Gen2 debug histogram. Not self-clearing
8072 … (0x1<<31) // Clear the recovery histogram. Not self-clearing
8077 … (0x1ff<<7) // Minimum time (in 4 ns clocks) to hold the transmitter…
8079 … (0xfff<<16) // Minimum time (in 4 ns clocks) to hold the transmitter…
8081 …erved - only write 0. Spare flops for the PL - train_ctl_in[1:0]. [29] (PL_FIX_19) Enable Phase 3 …
8083 …lastic buffers will be prevented from adjusting - generating dynamic clock compensation events - p…
8085 … (0x1<<31) // Reserved - only write 0. Spare flop for the PL - train_ctl_in[3].…
8088 … (0x1ff<<0) // The maximum time to wait (using prescale…
8090 … (0x1f<<9) // The maximum time to wait (using prescale…
8092 … (0x1<<14) // Enable the "pins" gloopback - assumes an external …
8094 … (0x1<<15) // Wait for the Serdes to indicate speed chang…
8098 …/ Enable a stronger check at the end of lane deskew and clock compensation to look for aligned SKP…
8100 …to be presented to the DLL in Configuration.Idle or Recovery.Idle if the lane to lane deskew is co…
8108 … (0x1<<22) // Disable requirement for all lanes in EI on transition to P1
8110 … (0x1<<23) // Enable requirement for Serdes to be in P1 before rece…
8114 …// Change the rate to the Serdes to Gen1 in the Disabled state rather than waiting until the LTSSM…
8116 … (0x7<<26) // Select the delay to gate off data from the PL to the D…
8118 … (0x7<<29) // Select the delay to gate off data from the PL to the D…
8121 … (0x1<<0) // For RC only. Select the value to use for the deemphas…
8123 …(0x1<<1) // For RC only. Enale automatic speed match when the link must change to Gen1 (slow down).
8125 … (0x1<<2) // For RC only. Enale automatic speed match when the link must change to Gen2 (speed up).
8127 …ing/simulation purposes, speed up the timer used to wait after a failed automatic speed up/slow do…
8129 …ing/simulation purposes, speed up the timer used to wait after a failed automatic speed up/slow do…
8131 …or RC only. When the RC is automatically speeding up/slowing down the link to match advertised rat…
8137 … (0x1<<8) // Allow link partner to initiate speed chang…
8141 …0) // Sets the delay between the assertion of electrical idle to the power state change to P2. The…
8143 …to the power state change to P2. This is needed in Gen2 when entering L2. The minimum time to wait…
8145 … (0x1<<14) // Allow lanes to be put into P2 state during reset to s…
8149 …e exit from Compliance on 1.1-compliant systems on signal detect on any lane (spec says all lanes …
8151 … (0x1<<17) // The minimum number of lanes for signal detect to avoid entry to Compliance. …
8155 … (0x1f<<19) // Mask for indicating lanes to upconfigure (1, 2, 4…
8160 … (0x1f<<0) // Counter of 25 MHz clks for the mininum time to spend with external …
8162 …-counter of 25 MHz clks for the minimum time to spend waiting for the reference clock buffers in t…
8164 … (0x1f<<9) // Counter of 25 MHz clks for the maximum time to wait after assertion…
8166 …f<<14) // Counter of 25 MHz clks for the minimum time to wait between assertion of clkreq/auxclk t…
8168 …les the control of the Serdes device type to minimize the PLL lock time (when set, don't reuse the…
8170 … (0x3<<22) // Selects the low-frequency clock used to advance t…
8172 …-counter of 25 MHz clks for the minimum time to spend waiting for the reference clock buffers in t…
8174 … (0x1<<30) // Reserved - only write 0
8176 … (0x1<<31) // When set, disables entry to CLKREQ when L2/L23 i…
8179 …to delay between the start of active clkreq (not in the standby state) and the switchover from Ref…
8181 …B (0x3<<6) // Reserved - only write 0
8183 … (0x3f<<8) // Number of clocks at 25 MHz to delay between assertion of reset to th…
8185 … (0x3<<14) // Reserved - only write 0
8189 … (0x1<<17) // Use any PhyStatus to indicate the P0->P2 trans…
8193 …ux during perstb and keep it asserted while perstb is asserted. Default is to briefly reset on per…
8195 … (0xfff<<20) // Reserved - only write 0
8198 … (0xf<<0) // b0000: select pseudo-random value between 1 to 15 b0001 to b1…
8202 … (0x1f<<7) // This field selects the lanes where error is injected to. b1xxxx : random lan…
8212 … (0x1fff<<18) // Reserved - always write 0
8214 …and no retrain will occur, with the possiblity of incorrect training and fall back to lower speeds.
8223 … (0x1<<3) // If set, the link needed to be deskewed
8225 … (0x1<<4) // If set, the link needed to be retrained
8229 … (0x1<<6) // Request to retrain received fro…
8233 …1_BB (0xf<<8) // Reserved - only write 0
8254 …_1_BB (0xf<<8) // Reserved - only write 0
8261 … (0x1<<1) // Enable request to the Serdes to realign block…
8267 …ng loss of block alignment) before the link is retrained. This is to allow any EIOS to be seen sin…
8269 … (0x1<<8) // *** Do not modify!! Enable 16-bit data for all rate…
8271 … (0x1<<9) // Enable the EIOS detector to mask out data.
8277 …_BB (0x1<<12) // Allow locking to the data blocks in G…
8279 …L_BB (0x1<<13) // When retraining to enter compliance, th…
8283 …, null data is inserted on different relative blocks and the logic fixes that to a limited extent).
8287 … (0x3<<17) // Reserved - only write 0
8291 … (0xf<<20) // Minimum time (in PCLKs) to wait for EI exit usi…
8297 …1<<26) // Enable transmission of 128 TS2s in Recovery.RcvrCfg prior to transition to Recovery.Spee…
8312 … (0x1<<20) // Enable a bad/misplaced End-of-Data-Stream token as a…
8318 … (0x1<<23) // Enable the auxilliary bad TLP length to be reported as a fra…
8320 … (0x1<<24) // Enable the auxilliary bad sync header to be reported as an er…
8322 … (0x1<<25) // Enable the auxilliary alignment error to be reported as a fra…
8324 … (0x1<<26) // Enable the auxilliary alignment error to be reported as a fra…
8328 … (0x1<<28) // Enable auxilliary framing errors to cause a retrain (if …
8343 … (0x1<<5) // Software sets if it can disable data traffic during re-equalization.
8353 … (0x1<<13) // Disable requests from the Serdes to request equalization.
8363 … (0x1<<18) // Clear indication that a DLP was received on change to Gen3.
8373 … (0x1<<23) // Clear previously received presets on entry to Recovery.RcvrCfg
8375 … TS1 if the EC field is set to 2'b10 or 2'b11 depending on whether Slave is an RC or EP respective…
8379 … (0x1<<26) // Disable presets in Phase 2 (raw data to Serdes)
8383 …B (0x1<<28) // Reserved - only write 0
8385 … (0x1<<29) // Disable timeout counter delay waiting for EC bits to change in equalizati…
8392 … (0x1f<<0) // Delay value for raw electrical idle to sig detect in Gen3 m…
8398 … (0x1<<7) // For Gen3 TS1s in Equalization, match symbols 1 to 5 as well
8406 … (0x1<<11) // Enable Gen3 redo deskew on framing/post-deskew alignment issu…
8408 …LOCK_BB (0x1<<12) // Assert signal to PHY when idle_to_rlo…
8410 …XL0S_BB (0x1<<13) // Assert signal to PHY when Rx_L0s time…
8418 … (0x1<<17) // Select between requiring all EQ TS2s or any EQ TS2 to set start_eq_w_preset
8428 … (0x1<<22) // (PL_FIX_05) Enable preset-coefficient lookup fo…
8430 …0x1<<23) // (PL_FIX_05) Tx/Rx presets in phase 2 must match before preset signal to Serdes asserted
8432 … (0x7<<24) // (PL_FIX_14) Default Rx preset to send to the Serdes if no…
8447 …C_BB (0x1<<6) // SED read address auto-increment
8449 …R_ADDR_BB (0x1<<7) // SED clear read address to 0
8468 …ET_LUT_ENTRY_5_TO_0_BB (0x3f<<0) // Pre-cursor for the coeffi…
8472 …_LUT_ENTRY_17_TO_12_BB (0x3f<<12) // Post-cursor for the coeffi…
8478 …23) // Conbtrol bit to select the default preset to use in phase2 advertizement provided on pcie_r…
8480 …vertized by the EP to the Link partner-RC Transmitter in Phase2 EQ programmable preset value adver…
8488 … (0x1<<31) // [DEBUG_BIT]: enable conversion of preset to coefficients to serdes when …
8491 … (0xf<<0) // (PL_FIX_15) Transmitter preset to transmit in EP EQ TS…
8493 … (0x7<<4) // (PL_FIX_15) Receiver preset hint to transmit in EP EQ TS…
8523 …eemphasis register control programming of coefficients for preset-0(-6dB) and preset-1(-3.5dB) in …
8525 …ing index for preset 0 and 1 0: points to the preset 0 coefficients(-6dB) 1: points to the preset …
8529 …1<<20) // Gen2 deemphasis register select control bit to change from Preset-1(-3.5dB) to preset-0(…
8531 …-bit value poining to the corresponding index. 0: Selects Gen3 read preset lut pointing to the reg…
8572 … (0x1<<29) // Phase2: Skips Rx EQ evaluation to Serdes and wait for 22msec extended timeout…
8574 … (0x1<<30) // Phase3: Skips Rx EQ evaluation to Serdes and wait for 22msec extended timeout…
8576 … (0x1<<31) // RX reset EIEOS control bit for TS1(SYM6-Bit2) in Recovery.Equ…
8579 … (0x1<<0) // Enable bit to control the register…
8581 … (0x3f<<1) // Registered programmed 6-bit FULL SWING value …
8583 … (0x1<<7) // Enable bit to control the register…
8585 … (0x3f<<8) // Registered programmed 6-bit LOW FREQUENCY val…
8587 …FF_SEL_BB (0x1<<14) // Selects to the received coeffic…
8589 … (0x1<<15) // [DEBUG_BIT]: Disables the 1usec wait time for LP to response for preset …
8611 …<<26) // [DEBUG_BIT]: RC mode : Forces Gen3 equalization for every Speed change over from Gen1-Gen3
8613 … (0x1f<<27) // [DEBUG_BITS]: Equalization static debug 5-bit address control f…
8616 …x1<<0) // Enable Illegal Ordered Set After EDS Error. When this bit is set to '1', report Gen3 fra…
8618 … (0x1<<1) // Enable Ordered Set After SDS Error. When this bit is set to '1', report Gen3 fra…
8620 … (0x1<<2) // Enable Ordered Set with No EDS Error. When this bit is set to '1', report Gen3 fra…
8622 … (0x1<<3) // Enable Bad Framing CRC Error. When this bit is set to '1', report Gen3 fra…
8624 … (0x1<<4) // Enable Bad Framing Parity Error. When this bit is set to '1', report Gen3 fra…
8626 … (0x1<<5) // Enable Bad EDB Error. When this bit is set to '1', report Gen3 fra…
8628 … (0x1<<6) // Enable Bad Framing Symbol Error. When this bit is set to '1', report Gen3 fra…
8630 … (0x1<<7) // Enable Data After EDS Error. When this bit is set to '1', report Gen3 fra…
8633 …to '1' enables the master loopback operation. Normally, if lpbk_master_len is set to '0', software…
8635 … (0x1<<1) // Loopback Master Entry State. If this bit is set to '1', loopback is ent…
8637 …t to '1', the Compliance Receive bit in TS1 is set to '1' when loopback master initiates the loopb…
8639 … Compliance Receive. If this bit is set to '1', hardware automatically sets the Compliance Receive…
8641 …etting. When loopback is entered from Recov.Idle state and this bit is set to '1', hardware applie…
8643 … is set, SKP OS are periodically inserted to loopback data. If data is generated by PHY, MAC provi…
8645 … sets for each SKIP OS interval. For testing purpose, when this bit is set to '1', hardware insert…
8649 …0x1f<<8) // Loopback Master Pattern. This field specifies the data pattern to be transmitted durin…
8653 …liseconds. When it is set to '0', software has to clear the lpbk_master_ena bit to stop the operat…
8656 …aster doesn't receive the feedback from Loopback Slave, it will transition to Detect state after a…
8658 …aWidth:0x20 // The loopback status register is cleared when lpbk_master_ena goes from '0' to '1'.
8661 …to a new speed. 2. Entered from Recovery.Idle and bit lpbk_master_frc_setting is set to '1'. If da…
8668 …CURSOR_BB (0x3f<<8) // Loopback Master TS1 Pre-Cursor Coefficient. T…
8672 …URSOR_BB (0x3f<<20) // Loopback Master TS1 Post-cursor Coefficient. T…
8674 … (0x1<<26) // Loopback Master TS1 Selectable De-emphasis. This value …
8676 …tion.Linkwidth.Start and changed to a new speed. 2. Entered from Recovery.Idle and bit lpbk_master…
8679 … used when loopback is in Gen2 rate. Notes that for Gen1 the TX deemphasis is always set to -3.5db.
8682 … (0x1<<0) // Software LTSSM Enable. Setting this bit to '1' allows software to take con…
8684 …to operate as normal until LTSSM reaches to the state specified by sw_ltssm_topst and sw_ltssm_sub…
8686 …to this bit updates the internal software LTSSM state with the state specified by sw_ltssm_topst a…
8688 … (0x1<<3) // LTSSM Timeout Disable. When this bit is set to '1', all LTSSM timeo…
8692 …-level State. This field specifies the state of the sub-level state machine that software wants LT…
8696 …0) // Software LTSSM Top-level State. This field specifies the state of the top-level state machin…
8700 …l Enable. This bit reflects the internal software LTSSM enable that is set to '1' only when S/W is…
8703 …to '1' enables the PCIE statistic collection. Hardware will count various things such as the numbe…
8707 …roseconds. When it is set to '0', software has to clear the pcie_statis_ena bit to stop the operat…
8709 …er of TLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8711 …er of TLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8713 …r of DLLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8715 …r of DLLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8717 …dered set bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8719 …dered set bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
8721 …mber of TLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8723 …mber of TLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8725 …ber of DLLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8727 …ber of DLLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8729 …ordered set bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8731 …ordered set bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
8733 …rrors detected by Physical Layer Receiver. It is cleared when pcie_statis_ena goes from '0' to '1'.
8734 …LP CRC errors detected by Data Link Layer. It is cleared when pcie_statis_ena goes from '0' to '1'.
8735 …number errors detected by Data Link Layer. It is cleared when pcie_statis_ena goes from '0' to '1'.
8737 …to '1' enables the LTSSM statisic collection. When this bit is reset to '0', information is frozen…
8739 … (0x1<<1) // LTSSM Statistic Auto Increment. When this bit is set to '1', hardware automa…
8741 …to ltssm_statis_N are stored in FIFOs. This field indicates the current readback address of the LT…
8754 …e Acknowledge Time. This field contains the time since power state changed to when Serdes acknowle…
8756 …(0xff<<8) // Symbol Lock Time. This field contains the time it took Serdes to achieve symbol lock …
8763 …(0xff<<16) // L0s Exit Time. This field contains the time that LTSSM spent to exit L0s state. The …
8768 … field contains the number of L0s exit failures (i.e. LTSSM has to transition from L0s to Recovery…
8771 …ffer overflow/underflow errors) recorded by the link partner after locking to the Modified Complia…
8773 … (0x1<<7) // For lane 12: Set by the link partner when it locks to the Modified Complia…
8775 …i-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow…
8777 … (0x1<<15) // For lane 13 in a multi-lane system: Set by the link partner when it loc…
8779 …ffer overflow/underflow errors) recorded by the link partner after locking to the Modified Complia…
8781 … (0x1<<23) // For lane 14: Set by the link partner when it locks to the Modified Complia…
8783 …i-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow…
8785 … (0x1<<31) // For lane 15 in a multi-lane system: Set by the link partner when it loc…
8788 …ffer overflow/underflow errors) recorded by the link partner after locking to the Modified Complia…
8790 … (0x1<<7) // For lane 8: Set by the link partner when it locks to the Modified Complia…
8792 …i-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow…
8794 … (0x1<<15) // For lane 9 in a multi-lane system: Set by the link partner when it loc…
8796 …ffer overflow/underflow errors) recorded by the link partner after locking to the Modified Complia…
8798 … (0x1<<23) // For lane 10: Set by the link partner when it locks to the Modified Complia…
8800 …i-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow…
8802 … (0x1<<31) // For lane 11 in a multi-lane system: Set by the link partner when it loc…
8805 …ffer overflow/underflow errors) recorded by the link partner after locking to the Modified Complia…
8807 … (0x1<<7) // For lane 4: Set by the link partner when it locks to the Modified Complia…
8809 …i-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow…
8811 … (0x1<<15) // For lane 5 in a multi-lane system: Set by the link partner when it loc…
8813 …ffer overflow/underflow errors) recorded by the link partner after locking to the Modified Complia…
8815 … (0x1<<23) // For lane 6: Set by the link partner when it locks to the Modified Complia…
8817 …i-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow…
8819 … (0x1<<31) // For lane 7 in a multi-lane system: Set by the link partner when it loc…
8822 …ffer overflow/underflow errors) recorded by the link partner after locking to the Modified Complia…
8824 … (0x1<<7) // For lane 0: Set by the link partner when it locks to the Modified Complia…
8826 …i-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow…
8828 … (0x1<<15) // For lane 1 in a multi-lane system: Set by the link partner when it loc…
8830 …ffer overflow/underflow errors) recorded by the link partner after locking to the Modified Complia…
8832 … (0x1<<23) // For lane 2: Set by the link partner when it locks to the Modified Complia…
8834 …i-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow…
8836 … (0x1<<31) // For lane 3 in a multi-lane system: Set by the link partner when it loc…
8839 …rors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sen…
8841 …e 12: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is…
8843 …-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow …
8845 … lane 13 in a multi-lane system: Set by the local receiver when it locks to the received Modified …
8847 …rors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sen…
8849 …e 14: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is…
8851 …-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow …
8853 … lane 15 in a multi-lane system: Set by the local receiver when it locks to the received Modified …
8856 …rors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sen…
8858 …ne 8: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is…
8860 …-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow …
8862 …r lane 9 in a multi-lane system: Set by the local receiver when it locks to the received Modified …
8864 …rors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sen…
8866 …e 10: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is…
8868 …-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow …
8870 … lane 11 in a multi-lane system: Set by the local receiver when it locks to the received Modified …
8873 …rors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sen…
8875 …ne 4: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is…
8877 …-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow …
8879 …r lane 5 in a multi-lane system: Set by the local receiver when it locks to the received Modified …
8881 …rors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sen…
8883 …ne 6: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is…
8885 …-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow …
8887 …r lane 7 in a multi-lane system: Set by the local receiver when it locks to the received Modified …
8890 …rors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sen…
8892 …ne 0: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is…
8894 …-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow …
8896 …r lane 1 in a multi-lane system: Set by the local receiver when it locks to the received Modified …
8898 …rors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sen…
8900 …ne 2: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is…
8902 …-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow …
8904 …r lane 3 in a multi-lane system: Set by the local receiver when it locks to the received Modified …
8939 … (0xff<<0) // Gen2 Debug History - current. Changes are…
8957 … (0xff<<0) // Recovery History - current. Changes are…
9015 …) // The current state of the ATE loopback SM tracker: b00011 : IDLE state - not active b00101 : …
9017 … (0x1<<5) // Current state of the gloopback signal to the Serdes
9044 …CKALIGN_BB (0x1<<10) // Retraining occurred due to block misalignment
9062 …SOS_BB (0x1<<19) // This bit is set to '1' when the ordered…
9066 … 0x001d38UL //Access:R DataWidth:0x20 // PHY Debug - Polling Compliance s…
9067 … 0x001d3cUL //Access:R DataWidth:0x20 // PHY Debug - Equalization signals
9173 … (0x7ff<<0) // Debug signals that are muxed to the debug port 0.
9177 … (0x7ff<<16) // Debug signals that are muxed to the debug port 1.
9194 …to complete P0 to P2 change b0011 : State waiting for Tp0torefclk timer expiry b0100 : State waiti…
9248 … (0x1<<0) // Instantaneous value of the top-level user_allow_gen3 signal (sync'd to t…
9253 … (0xffff<<0) // Vendor ID. For SR-IOV VFs always 0xFFFF.
9255 … (0xffff<<16) // Device ID. For SR-IOV VFs always 0xFFFF.
9258 …ENDOR_ID_K2 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufact…
9263 …E_E5 (0x1<<0) // VF read-only zero.
9265 …E_E5 (0x1<<1) // VF read-only zero.
9267 …to master the bus when this bit is not set, the request is discarded. A interrupt will be generate…
9269 … (0x1<<3) // Special cycle enable. Not applicable for PCI Express. Must be hardwired to 0.
9271 … (0x1<<4) // Memory write and invalidate. Not applicable for PCI Express. Must be hardwired to 0.
9273 … (0x1<<5) // VGA palette snoop. Not applicable for PCI Express. Must be hardwired to 0.
9277 …1<<7) // IDSEL stepping/wait cycle control. Not applicable for PCI Express. Must be hardwired to 0.
9281 … (0x1<<9) // Fast back-to-back transaction enable. Not applicable for PCI Express. M…
9283 …S_E5 (0x1<<10) // VF read-only zero.
9289 … (0x1<<19) // INTx status. Not applicable for SR-IOV. Hardwired to 0.
9291 … (0x1<<20) // Capabilities list. Indicates presence of an extended capability item. Hardwired to 1.
9293 … (0x1<<21) // 66 MHz capable. Not applicable for PCI Express. Hardwired to 0.
9295 … (0x1<<23) // Fast back-to-back capable. Not applicable for PCI Express. Har…
9299 … (0x3<<25) // DEVSEL timing. Not applicable for PCI Express. Hardwired to 0x0.
9312 …to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0. …
9314 …to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0…
9340 …P_K2 (0x1<<23) // Fast Back to Back Transaction Cap…
9352 …_ERR_K2 (0x1<<30) // Fatal or Non-Fatal Error Message s…
9359 … (0xff<<8) // Read-only copy of the asso…
9361 … (0xff<<16) // Read-only copy of the asso…
9363 … (0xff<<24) // Read-only copy of the asso…
9370 …E_K2 (0xff<<16) // Subclass Code to represent Device Typ…
9372 …E_K2 (0xff<<24) // Base Class Code to represent Device Typ…
9375 …-only copy of the associated PF's PCIEEP()_CLSIZE[CLS]. The cache line size register is R/W for l…
9377 … (0xff<<8) // Master latency timer. Not applicable for PCI Express, hardwired to 0x0.
9379 … (0x7f<<16) // Configuration header format. Hardwired to 0x0 for type 0.
9381 … (0x1<<23) // Read-only copy of the asso…
9383 …he BIST register functions are not supported. All 8 bits of the BIST register are hardwired to 0x0.
9388 …ACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2 (0xff<<8) // Does not apply to PCI Express.
9397 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
9400 …E_K2 (0x3<<1) // BAR0 32-bit or 64-bit.
9407 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
9410 …E_K2 (0x3<<1) // BAR1 32-bit or 64-bit.
9417 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
9420 …E_K2 (0x3<<1) // BAR2 32-bit or 64-bit.
9427 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
9430 …E_K2 (0x3<<1) // BAR3 32-bit or 64-bit.
9437 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
9440 …E_K2 (0x3<<1) // BAR4 32-bit or 64-bit.
9447 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
9450 …E_K2 (0x3<<1) // BAR5 32-bit or 64-bit.
9459 … (0xffff<<0) // Read-only copy of the asso…
9461 … (0xffff<<16) // Read-only copy of the asso…
9464 …tem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9466 …tem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9469 … (0x1<<0) // Read-only copy of the asso…
9471 … (0x1fff<<19) // Read-only copy of the asso…
9474 … (0xff<<0) // First capability pointer. Points to the PCI Express capa…
9477 …K2 (0xff<<0) // Pointer to first item in the PC…
9480 … (0xff<<0) // VF's read-only zeros.
9482 … (0xff<<8) // VF's read-only zeros.
9484 … (0xff<<16) // VF's read-only zeros.
9486 … (0xff<<24) // VF's read-only zeros.
9496 … (0xff<<8) // Next capability pointer. Points to the MSI-X capabilities b…
9498 …_E5 (0xf<<16) // Read-only copy of the asso…
9500 … (0xf<<20) // Read-only copy of the asso…
9502 … (0x1<<24) // Read-only copy of the asso…
9504 … (0x1f<<25) // Read-only copy of the asso…
9515 …emented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9522 … (0x7<<0) // Read-only copy of the asso…
9524 … (0x3<<3) // Read-only copy of the asso…
9526 … (0x1<<5) // Read-only copy of the asso…
9528 … (0x7<<6) // Read-only copy of the asso…
9530 … (0x7<<9) // Read-only copy of the asso…
9532 … (0x1<<15) // Read-only copy of the asso…
9538 … (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core.
9545 …eld Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9547 …E_CAP_EP_L0S_ACCPT_LATENCY_K2 (0x7<<6) // Applies to endpoints only L0s a…
9549 …E_CAP_EP_L1_ACCPT_LATENCY_K2 (0x7<<9) // Applies to endpoints only L1 ac…
9551 …_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2 (0x1<<15) // Role-based Error Reporting…
9582 …el reset when written to one. [I_FLR] must not be written to one via the indirect PEM()_CFG_WR. …
9584 … example a replay-timer timeout. Also, it can be set if we get any of the errors in PCIEEPVF()_UC…
9586 …ceive any of the errors in PCIEEPVF()_UCOR_ERR_MSK that has a severity set to nonfatal and does no…
9588 …ceive any of the errors in PCIEEPVF()_UCOR_ERR_MSK that has a severity set to fatal. Malformed TLP…
9590 …ests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message shoul…
9592 …D_E5 (0x1<<20) // VF's read-only zeros.
9594 … (0x1<<21) // Transaction pending. Set to 1 when nonposted requests are not yet completed a…
9599 …_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting…
9609 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9611 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILI…
9615 …(0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R
9623 …STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected …
9634 … (0xf<<0) // Read-only copy of the asso…
9636 … (0x3f<<4) // Read-only copy of the asso…
9638 …5 (0x3<<10) // Read-only copy of the asso…
9640 … (0x7<<12) // Read-only copy of the asso…
9642 … (0x7<<15) // Read-only copy of the asso…
9644 … (0x1<<18) // Read-only copy of the asso…
9646 … (0x1<<19) // Read-only copy of the asso…
9648 …5 (0x1<<20) // Read-only copy of the asso…
9650 … (0x1<<21) // Read-only copy of the asso…
9652 … (0x1<<22) // Read-only copy of the asso…
9654 … (0xff<<24) // Read-only copy of the asso…
9657 …D_K2 (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the reset …
9659 …_K2 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset …
9663 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
9665 …- CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1…
9667 …er Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9675 … ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: R
9684 … (0x1<<4) // Link disable. Not applicable for an upstream port or endpoint device. Hardwired to 0.
9686 … (0x1<<5) // Retrain link. Not applicable for an upstream port or endpoint device. Hardwired to 0.
9702 … link speeds vector (in the link capabilities 2 register) that corresponds to the current link spe…
9706 …(0x1<<27) // Link training. Not applicable for an upstream port or endpoint device, hardwired to 0.
9710 … // Data link layer active. Not applicable for an upstream port or endpoint device, hardwired to 0.
9721 …_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_EN…
9723 …e Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description
9729 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9733 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9735 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9743 …figuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R
9745 …Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9749 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9751 …PABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITI…
9762 …-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dro…
9764 …-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dro…
9766 …-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dro…
9768 … (0x1<<10) // No RO-enabled PR-PR passing. (This bit applies to…
9776 …_CPL_SUPP_E5 (0x1<<16) // 10-bit tag completer sup…
9778 …_REQ_SUPP_E5 (0x1<<17) // 10-bit tag requestor sup…
9784 …5 (0x1<<21) // End-end TLP prefix suppor…
9786 … (0x3<<22) // Read-only copy of the asso…
9801 …IE_CAP_128_CAS_CPL_SUPP_K2 (0x1<<9) // 128 Bit CAS Completer Supported.
9803 …O_EN_PR2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
9828 …_REQ_EN_E5 (0x1<<12) // 10-bit tag requestor ena…
9832 … (0x1<<15) // Unsupported end-end TLP prefix blocki…
9854 … (0x7f<<1) // Read-only copy of the asso…
9867 …DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9870 …TLS_E5 (0xf<<0) // VF's read-only zeros.
9872 …EC_E5 (0x1<<4) // VF's read-only zeros.
9874 …HASD_E5 (0x1<<5) // VF's read-only zeros.
9876 …SDE_E5 (0x1<<6) // VF's read-only zeros.
9878 …TM_E5 (0x7<<7) // VF's read-only zeros.
9880 …MC_E5 (0x1<<10) // VF's read-only zeros.
9882 …SOS_E5 (0x1<<11) // VF's read-only zeros.
9884 …DE_E5 (0xf<<12) // VF's read-only zeros.
9886 … (0x1<<16) // Read-only copy of the asso…
9909 …ET_LINK_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the conten…
9913 …Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9915 …SEL_DEEMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. …
9919 …ed Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9921 … transmission. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Not…
9923 … // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of thi…
9925 … (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is alwa…
9942 …NTRL_MSIXCID_E5 (0xff<<0) // MSI-X capability ID.
9946 … (0x7ff<<16) // MSI-X table size encoded as (table size - 1)…
9948 …ctors associated with the function are masked, regardless of their respective per-vector mask bits.
9950 …X_CAP_CNTRL_MSIXEN_E5 (0x1<<31) // MSI-X enable.
9952 … 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next…
9953 …NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID.
9955 …TRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capability Poi…
9957 …-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PC…
9959 …(0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W
9961 … (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are…
9964 …BIR_E5 (0x7<<0) // Read-only copy of the asso…
9966 … (0x1fffffff<<3) // Read-only copy of the asso…
9968 … 0x0000b4UL //Access:R DataWidth:0x20 // MSI-X Table Offset and BI…
9969 …_PCI_MSIX_BIR_K2 (0x7<<0) // MSI-X Table Bar Indicator…
9971 …_PCI_MSIX_TABLE_OFFSET_K2 (0x1fffffff<<3) // MSI-X Table Offset.
9974 …R_E5 (0x7<<0) // Read-only copy of the asso…
9976 … (0x1fffffff<<3) // MSI-X table offset register. Base address of the M…
9978 … 0x0000b8UL //Access:R DataWidth:0x20 // MSI-X PBA Offset and BIR …
9979 …OFFSET_REG_PCI_MSIX_PBA_K2 (0x7<<0) // MSI-X PBA BIR.
9981 …_PCI_MSIX_PBA_OFFSET_K2 (0x1fffffff<<3) // MSI-X PBA Offset.
9991 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9993 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
9995 …bility Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10031 …Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10033 …ility Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10035 …ility Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
10052 …e: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common re…
10073 …(0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W
10078 … (0xff<<0) // ST Table 0 Lower Byte. Access can be tied to 0 by table size conf…
10080 … (0xff<<8) // ST Table 0 Upper Byte. Access can be tied to 0 by table size conf…
10083 … Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by…
10085 … Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by…
10095 … (0x1<<0) // ACS source validation. Hardwired to 0 for upstream port.…
10126 …0UL //Access:W DataWidth:0x20 // The BAR 0 mask register is invisible to host software and no…
10127 …to the BAR mask register rather than as a mask bit because bit 0 of a BAR is always masked from wr…
10131 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10132 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10134 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10136 …4UL //Access:W DataWidth:0x20 // The BAR 0 mask register is invisible to host software and no…
10137 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10138 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10140 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10142 …8UL //Access:W DataWidth:0x20 // The BAR 1 mask register is invisible to host software and no…
10143 …to the BAR mask register rather than as a mask bit because bit 0 of a BAR is always masked from wr…
10147 …cUL //Access:W DataWidth:0x20 // The BAR 1 mask register is invisible to host software and no…
10148 …0UL //Access:W DataWidth:0x20 // The BAR 2 mask register is invisible to host software and no…
10149 …to the BAR mask register rather than as a mask bit because bit 0 of a BAR is always masked from wr…
10153 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10154 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10156 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10158 …4UL //Access:W DataWidth:0x20 // The BAR 2 mask register is invisible to host software and no…
10159 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10160 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10162 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10164 …030UL //Access:W DataWidth:0x20 // The ROM mask register is invisible to host software and no…
10165 …to the BAR mask register rather than as a mask bit because bit 0 of a BAR is always masked from wr…
10169 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10170 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10172 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if RO…
10174 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10175 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10177 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10180 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10182 …-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-…
10184 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10185 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10187 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10189 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10190 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10192 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10194 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10195 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10197 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10199 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10200 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10202 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10204 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10205 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10207 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10209 … dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second regi…
10210 …led. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10212 …ask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (st…
10214 … 0x000004UL //Access:RW DataWidth:0x1 // Disable for SDM write to int_ram.
10216 … (0x1<<0) // Signals an unknown address to the rf module.
10222 … (0x1<<0) // Signals an unknown address to the rf module.
10225 … (0x1<<0) // Signals an unknown address to the rf module.
10227 … 0x000050UL //Access:W DataWidth:0x1 // Reset to error interrupt.
10228 … 0x000054UL //Access:W DataWidth:0x1 // Reset to parity interrupt.
10290 …-only access of the GPRE registers. Register can be accessed only when storm is stalled. Address b…
10292 … 0x000480UL //Access:R DataWidth:0x20 // 15-0 STORM0 GPRE0 bits 15:0. 31-16 STOR…
10293 …- misc_local_mux_other_stall, 20 - ram_mux_bkpt_stall, 19 - mux_lock_stall, 18 - pram_mux_pipe_st…
10294 … 0x000488UL //Access:RW DataWidth:0x1 // This register is used to define a stall condi…
10295 …egister is used to define the state of an independent stall source. This is the first of three pro…
10296 …gister is used to define the state of an independent stall source. This is the second of three pro…
10297 …egister is used to define the state of an independent stall source. This is the last of three prov…
10298 …provides a status to indicate whether or not the Storm is currently stalled. bit0- STORM A. bit1- …
10299 …register with any value causes all the internal and external stall sources to be reset, resulting …
10300 … 0x00049cUL //Access:W DataWidth:0x1 // Used to clear the latched st…
10303 …R DataWidth:0xf // This register delivers the PRAM address for the low-word instruction that…
10304 … DataWidth:0xf // This register delivers the PRAM address for the high-word instruction that…
10305 …gister with any value causes the PRAM ECC replay logic to be executed and the PRAM parity stall to…
10306 …ataWidth:0x1 // Writing this register with any value causes the PRAM parity error to be cleared.
10307 …to the Storm. A value of 1 means that the PortID will be taken as a single bit , a value of 2 mean…
10308 …the lsb of the CID in which to assign to bit-0 of the port ID. I.e. if port_id_wdth is set to 0x1 …
10309 …dth:0x1 // Defines the Storm register file set that is currently active. 0 - STORM A 1 - STORM B
10310 …- DRA WR STM Core_A, 3:5 - DRA WR STM Core_B, 6:8 - DRA RD STM Core_A, 9:11 - DRA RD STM Core_B, …
10311 … 0x0004c8UL //Access:R DataWidth:0x20 // Last read address from STORM to pram {add_p_out_high…
10312 … 0x0004c8UL //Access:R DataWidth:0x20 // Last read address from STORM to pram {add_p_out_high…
10313 …to the internal RAM by RBC. For this, any set bit in the data field will result in a corresponding…
10315 …th:0x20 // This register delivers the Storm PC for read-only debug access. 15-0 - STORM A. 31-16…
10316 …e access type defined in data_breakpoint_access_set), the STORMs bits 15:0 - IRAM stall start add…
10317 …efined in data_breakpoint_access_set), the STORMs will be stalled. bit15:0 - IRAM stall end addre…
10318 …- stall on read access. bit1 - stall on write access. bit3:2 - stall on write BE (bit2 -to IRAM'…
10319 …er defines the IRAM address for which the data breakpoint stall was set. bits 0:15 - IRAM address.
10320 … 0x0004e8UL //Access:R DataWidth:0x20 // Last read address from STORM to pram {add_p_out_high…
10321 … 0x0004ecUL //Access:RW DataWidth:0x1 // This register is used to define a stall condi…
10322 … 0x0004f0UL //Access:RW DataWidth:0x1 // This register is used to define a stall condi…
10323 … indirect registers defines the modulus (roll-over) values for the corresponding real time clocks.…
10326 …to select the Storm which is allowed to update the corresponding real-time clock with regard to th…
10329 …to define the initialization value for each of the real-time clocks. This value is assigned to the…
10332 …to select the Storm which is allowed to initialize the corresponding real-time clock with the valu…
10335 …// This array of indirect registers provides read access to the real time clock values. The sub-ad…
10337 …ontaining a bit per RTC used to enable each of the ten real-time clocks. The bit index corresponds…
10347 …or the most recent RBC read request issued. The valid bit is returned on bit-0 of the data. All ot…
10350 … (0x1<<0) // Writing a one to this register bit (transition from 0 to 1) causes the entire CAM to …
10356 …/ This register is set after the CAM initialization is started (by writing to cam_init) and remain…
10357 …0x20 // This array of registers returns the 128-bit CAM match vector returned in the most recent…
10359 … 0x000740UL //Access:RW DataWidth:0x1 // Used to activate/deactivate …
10360 …-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fas…
10361 …or used to disable any of the following debug sources for modes 2 and 3 on the fast debug channel:…
10362 …x2 // Vector used to disable any of the following debug sources for mode-4 on the fast debug ch…
10363 …to disable any of the following debug sources for mode-6 on the fast debug channel: b0-dra_in disa…
10364 …0 // Connection id that should compared with cid field of the data (in Dra-In message); Note: ap…
10365 …aWidth:0x8 // Event id that should compared with event id field of the data (in Dra-In message).
10366 …075cUL //Access:RW DataWidth:0x8 // Mask for event id. 1- specified bit is ignored; 0 - speci…
10367 …Width:0x8 // Used to provide a starting range for the event ID range filter. A range of event I…
10368 …aWidth:0x8 // Used to provide a ending range for the event ID range filter. A range of event ID…
10370 …- Filter off; in that case all data should be transmitted to the DBG block without any filtering i…
10372 …- use the recorded connection id field which arrives from the DBG block (dbg_sem_cid interface) fo…
10374 …TER_CID_EN (0x1<<3) // Used to enable CID/TID filte…
10376 …TER_EVNT_ID_EN (0x1<<4) // Used to enable Event ID filt…
10378 …SRC (0x3<<5) // Used to define the DRA-In source tha…
10380 …TER_DRA_SRC_EN (0x1<<7) // Used to enable DRA source fi…
10382 …TER_EVENT_ID_RANGE_EN (0x1<<8) // Used to enable filtering bas…
10384 …TER_STORE_EN (0x1<<9) // Used to enable the debug sto…
10386 …ess:RW DataWidth:0x10 // Used in conjunction with dbg_store_addr_value to filter the store dat…
10387 …cess:RW DataWidth:0x10 // Used in conjunction with dbg_store_addr_mask to filter the store dat…
10388 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
10398 …TER_CID_EN (0x1<<0) // Used to enable CID/TID filte…
10400 …TER_EVNT_ID_EN (0x1<<1) // Used to enable Event ID filt…
10402 …SRC (0x3<<2) // Used to define the DRA-In source tha…
10404 …TER_DRA_SRC_EN (0x1<<4) // Used to enable DRA source fi…
10406 …TER_EVENT_ID_RANGE_EN (0x1<<5) // Used to enable active statis…
10408 … 0x000a44UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10409 … 0x000a44UL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10410 … a vector for enabling/masking the various stall sources from contributing to the storm_stall_cycl…
10411 … 0x000a4cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10412 … 0x000a4cUL //Access:RC DataWidth:0x20 // Statistics - The accumulated numb…
10413 …idth:0x20 // Statistics - The accumulated number of Storm cycles in which the Storm has been idl…
10414 …- The accumulated number of Storm cycles in which the Storm has been idle due to having no threads…
10415 …idth:0x20 // Statistics - The accumulated number of Storm cycles in which the Storm has been idl…
10416 …idth:0x20 // Statistics - The accumulated number of Storm cycles in which the Storm has been idl…
10417 … 0x000a58UL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10418 … 0x000a5cUL //Access:R DataWidth:0x20 // Statistics - The accumulated numb…
10419 …idth:0x20 // Statistics - The accumulated number of Storm cycles in which the Storm has been idl…
10420 …idth:0x20 // Statistics - The accumulated number of Storm cycles in which the Storm has been idl…
10422 … Command data for VFC. VFC will accumulate all writing to this register till will be done write to…
10423 …th:0xc // Command address for VFC. Write to it should be done when all command data was already…
10425 …- response is ready. It is set when response cycle of 32 bit is ready from VFC block. It is reset …
10426 … 0x000c40UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST …
10428 …sed to select the BIST status word to read following the completion of a BIST test. Also used to s…
10429 … 0x000c4cUL //Access:R DataWidth:0x20 // Provides read-only access to the BIST stat…
10430 … 0x000cc0UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
10431 … 0x000cc4UL //Access:RW DataWidth:0x8 // command to CPU BIST
10432 … 0x000cc8UL //Access:RW DataWidth:0x8 // address to CPU BIST
10437 …to be executed with the CAM offset specified by the indirect register sub-address. Bits [3:0] of t…
10439 …UL //Access:RW DataWidth:0x20 // Provides a memory-mapped region for VFC configurations; up to…
10441 …hed). If lsb bit of addr = 0 => write to lock ID of addr[3:1] LOCK_VAL[31:0] if lsb bit of addr =…
10447 …ataWidth:0x20 // Internal RAM (if bit lsb of addr =0 => write to bits[31:0; otherwise to [63:32).
10458 … DataWidth:0x8 // This register includes bit per ALU vector: 0-4 long vectors; 5-11 short vec…
10459 …at will be written to DSt vector for analyze operation. If it is set to 1, then row from target ta…
10461 … to not existing address in VFC. Also it will be asserted when there is attempt to write to read o…
10471 …dress not equal to 12 bit or data cycle not equal 64 bit or number of data cycles bigger than 6. …
10473 …d when waitp is asserted and output FIFO is also full. It will be de-asserted aftre write 1 to it.
10475 …d when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write 1 to it.
10477 …n it was address overflow of KEY LSB part of RSS RAM. It will be de-asserted aftre write 1 to it.
10479 …hen it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write 1 to it.
10482 …rrupt. It may be asserted when it was CAM parity error. It will be de-asserted aftre write 1 to it.
10484 …may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write 1 to it.
10486 …. It may be asserted when it was RSS RAM parity error. It will be de-asserted aftre write 1 to it.
10515 … (0x1<<17) // Indicates if waitp from VFC to STORM is asserted.
10532 … 0x000038UL //Access:W DataWidth:0x1 // Write to this bit will cause to block re…
10534 … (0x1<<0) // Write 1 to this bit will cause reset of all CAM rows including valid bit and al…
10536 … (0x1<<2) // Write 1 to this bit will cause reset of all Target tables rows.…
10538 … (0x1<<1) // Write 1 to this bit will cause reset of all RSS RAM rows. Wr…
10540 …:RW DataWidth:0x1 // REQUIRED -If this bit is set then background mechanism for parity check …
10541 … 0x000044UL //Access:RW DataWidth:0x4 // Cam clock divider : may be equal to 2 only.
10542 … 0x000048UL //Access:RW DataWidth:0x3 // REQUIRED - 0 - parity is enabled;…
10543 … 0x00004cUL //Access:RW DataWidth:0xa // REQUIRED - 0 - interrupt is enabled;1- interr…
10552 …. When number of entries inside input FIFO is bigger or equal to this number then waitp to STORM w…
10553 …t then it disables selecting of commands from STORM. It will allow for RBC to configurate block. S…
10554 …aitp was raised to STORM as a result of full input FIFO. This vector will be reset after reading f…
10556 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
10557 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
10569 … (0x1<<16) // Ready indication from STORM to input arbiter.
10571 … (0x1<<17) // Ready indication from RBC to input arbiter.
10573 … (0x3<<18) // This field is set to 0.
10586 … // Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.
10587 … // Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.
10588 … // Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.
10589 … // Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.
10590 … // Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.
10591 … // Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.
10592 … // Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.
10593 … // Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.
10602 …//Access:RW DataWidth:0x1 // If this bit set to 0 then allows to work with 160 clients. If se…
10660 … (0x1<<0) // Signals an unknown address to the rf module.
10698 … (0x1<<0) // Signals an unknown address to the rf module.
10717 … (0x1<<0) // Signals an unknown address to the rf module.
10739 … (0x1<<0) // Indicates if to switch the CRC resul…
10741 … (0x1<<1) // Indicates if to ignore the input err…
10747 …machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
10781 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the instruction…
10782 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the lower 32 bi…
10783 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the upper 32 bi…
10784 …debug register. This register provides the number of data bytes remaining to be read from DB at t…
10790 … 0x000728UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
10791 … line) in the selected line (before shift).for selecting a line to output
10795 … 0x002000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
10800 …_E5 (0xff<<0) // 8-bit value from packag…
10802 …E5 (0xff<<8) // 8-bit value from packag…
10808 …C Transmit Path Enable. Should be set to '1' to enable the MAC transmit path, should be set to '0'…
10810 …AC Receive Path Enable. Should be set to '1' to enable the MAC receive path, should be set to '0' …
10816 …ble MAC Promiscuous Operation. If set to '1', all frames are received without any MAC address filt…
10820 …to '1', the CRC field of received frames is forwarded with the frame to the user application. If s…
10822 … Terminate / Forward Pause Frames. If set to '1', pause frames are forwarded to the user applicati…
10824 …/ Ignore received Pause frame quanta. If set to '1', received pause frames are ignored by the MAC.…
10826 …to '1', the MAC overwrites the source MAC address received from the client interface with the MAC …
10828 …nterface loopback. If set to '1', the signal loop_ena is set to '1'. If set to '0' (Reset value), …
10832 … (0x1<<12) // Self-Clearing Software Reset. When written with '1', all Statistics …
10834 … // Enable Reception of all Control Frames. If set to '1', all control frames are accepted. If set…
10840 … (0x1<<16) // Force Idle Generation. If set to '1', the MAC permane…
10846 …nable. If set to 1, the Core generates and processes PFC control frames according to the Priority …
10854 … (0x1<<23) // Instruct RS Layer to transmit LPI.
10860 …_K2_E5 (0x1<<26) // Self-Clearing TX FIFO rese…
10862 …to '0' (default), the MAC automatically inserts remote faults and idles in egress direction on det…
10879 …statistics use if it should be different from receive statistics. When set to 0 the FRM_LENGTH val…
10913 … (0x1<<5) // MDIO transaction preamble disable. Shortens transaction but is non-standard.
10917 … 5 to 511. The frequency is reg_clk/(2*divisor+1). The reset default is defined by the synthesis p…
10924 … (0x1<<14) // If written with 1, a read with address post-increment will be performed. Post-incr…
10928 … 0x000038UL //Access:RW DataWidth:0x20 // MDIO Data to write and last Data …
10929 …-bit data word. When written- Initiates a write transaction to the PHY. The MDIO_COMMAND register …
10931 …ice to read from or write to. After writing this register, an address-write transaction will be in…
10932 …0) // The MDIO_COMMAND register must have been initialized before the first write to this register.
10935 … (0x1<<0) // Local Fault Status. Set to '1' when the MAC det…
10937 … (0x1<<1) // Remote Fault Status. Set to '1' when the MAC det…
10939 … (0x1<<2) // PHY indicates loss-of-signal. Represents v…
10941 …t transmitted 1588 event frame is available in the register TS_TIMESTAMP. To clear TS_AVAIL, the …
10959 …E5 (0x1<<0) // Credit-based FIFO only: When…
10962 … (0xff<<0) // Credit-based FIFO only: Specifies the initial credit va…
10970 …ffff<<16) // Value to be sent for the PFC quanta value for that class when a class XOFF is trigger…
10975 … (0xffff<<16) // CL3_PAUSE_QUANTA; Value to be sent for the PFC …
10980 … (0xffff<<16) // CL5_PAUSE_QUANTA; Value to be sent for the PFC …
10985 … (0xffff<<16) // CL7_PAUSE_QUANTA; Value to be sent for the PFC …
11008 … (0xff<<0) // Status bit for software to read the current rec…
11012 … (0x1<<0) // Enable XGMII-64 (4byte alignment)
11016 … (0x1<<5) // Enable 1-step capable datapath…
11019 … (0x1<<0) // Configure saturation behavior. When set to 1, the counters saturate at all-1. O…
11021 … (0x1<<1) // Configure clear-on-read behavior. When set to 1, the counters are clea…
11023 …2) // Clear all counters command (self-clearing). When written with 1 all counters (tx and rx) are…
11057 … 0x000178UL //Access:R DataWidth:0x20 // Frames of 65 to 127 octets received
11058 … 0x00017cUL //Access:R DataWidth:0x20 // Frames of 65 to 127 octets received
11059 … 0x000180UL //Access:R DataWidth:0x20 // Frames of 128 to 255 octets received
11060 … 0x000184UL //Access:R DataWidth:0x20 // Frames of 128 to 255 octets received
11061 … 0x000188UL //Access:R DataWidth:0x20 // Frames of 256 to 511 octets received
11062 … 0x00018cUL //Access:R DataWidth:0x20 // Frames of 256 to 511 octets received
11063 … 0x000190UL //Access:R DataWidth:0x20 // Frames of 512 to 1023 octets received
11064 … 0x000194UL //Access:R DataWidth:0x20 // Frames of 512 to 1023 octets received
11065 … 0x000198UL //Access:R DataWidth:0x20 // Frames of 1024 to 1518 octets received
11066 … 0x00019cUL //Access:R DataWidth:0x20 // Frames of 1024 to 1518 octets received
11067 … 0x0001a0UL //Access:R DataWidth:0x20 // Frames of 1519 to FRM_LENGTH octets re…
11068 … 0x0001a4UL //Access:R DataWidth:0x20 // Frames of 1519 to FRM_LENGTH octets re…
11109 … 0x000278UL //Access:R DataWidth:0x20 // Frames of 65 to 127 octets transmitt…
11110 … 0x00027cUL //Access:R DataWidth:0x20 // Frames of 65 to 127 octets transmitt…
11111 … 0x000280UL //Access:R DataWidth:0x20 // Frames of 128 to 255 octets transmitt…
11112 … 0x000284UL //Access:R DataWidth:0x20 // Frames of 128 to 255 octets transmitt…
11113 … 0x000288UL //Access:R DataWidth:0x20 // Frames of 256 to 511 octets transmitt…
11114 … 0x00028cUL //Access:R DataWidth:0x20 // Frames of 256 to 511 octets transmitt…
11115 … 0x000290UL //Access:R DataWidth:0x20 // Frames of 512 to 1023 octets transmit…
11116 … 0x000294UL //Access:R DataWidth:0x20 // Frames of 512 to 1023 octets transmit…
11117 … 0x000298UL //Access:R DataWidth:0x20 // Frames of 1024 to 1518 octets transmit…
11118 … 0x00029cUL //Access:R DataWidth:0x20 // Frames of 1024 to 1518 octets transmit…
11119 … 0x0002a0UL //Access:R DataWidth:0x20 // Frames of 1519 to FRM_LENGTH.TX_MTU oc…
11120 … 0x0002a4UL //Access:R DataWidth:0x20 // Frames of 1519 to FRM_LENGTH.TX_MTU oc…
11158 …When 1, configure the FEC decoder to not indicate errors to the PCS layer; When 0, the FEC decode…
11163 … (0x1<<1) // Indicates the ability to disable error propagation to the P…
11167 …_K2_E5 (0xf<<8) // RS-FEC receive lane lock…
11169 … (0x1<<14) // Indicates, when 1 that the RS-FEC receiver has lock…
11173 …x20 // Counts number of corrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11174 …umber of corrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11176 …h:0x20 // Counts number of corrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11177 … (0xffff<<0) // Counts number of corrected FEC codewords upper 16-bits; None roll-over; Clears …
11179 …0 // Counts number of uncorrected FEC codewords lower 16-bits; None roll-over when upper 16-bits…
11180 …ber of uncorrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over …
11182 …0x20 // Counts number of uncorrected FEC codewords upper 16-bits; Clears on read; None roll-over.
11183 … (0xffff<<0) // Counts number of uncorrected FEC codewords upper 16-bits; None roll-over; Clears …
11186 …_E5 (0x3<<0) // FEC lane mapped to PMA lane 0.
11188 …_E5 (0x3<<2) // FEC lane mapped to PMA lane 1.
11190 …_E5 (0x3<<4) // FEC lane mapped to PMA lane 2.
11192 …_E5 (0x3<<6) // FEC lane mapped to PMA lane 3.
11194 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 0; None roll-over whe…
11195 … (corrected) 10-bit symbol errors found in lane 0 for correctable codewords only; Lower 16-bit of …
11197 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11198 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 0; Clears o…
11200 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 1; None roll-over whe…
11201 … (corrected) 10-bit symbol errors found in lane 1 for correctable codewords only; Lower 16-bit of …
11203 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11204 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 1; Clears o…
11206 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 2; None roll-over whe…
11207 … (corrected) 10-bit symbol errors found in lane 2 for correctable codewords only; Lower 16-bit of …
11209 …L //Access:R DataWidth:0x20 // Upper 16-bit of counter (with above register); Clears on read;…
11210 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 2; Clears o…
11212 …th:0x20 // Counts number of (corrected) 10-bit symbol errors found in lane 3; None roll-over whe…
11213 … (corrected) 10-bit symbol errors found in lane 3 for correctable codewords only; Lower 16-bit of …
11215 … DataWidth:0x20 // Upper 16 bit of counter (with above register); Clears on read; None roll-over.
11216 … (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 3; Clears o…
11218 … 0x000200UL //Access:RW DataWidth:0x20 // Additional control to enable RS-FEC operation.
11224 … (0xf<<0) // Per PMA lane FEC synchronization status; Bit 0=lane 0 up to Bit 3 = lane 3; Latc…
11228 …5) // The marker_check function (PCS sublayer) caused an alignment restart to the FEC; Latched hig…
11240 …_EMPTY_K2_E5 (0xf<<12) // Real-time indication from …
11248 …W DataWidth:0x20 // Bits 7:0; Must be written with the 8-bit value of 0x57 to enable RS-FEC tr…
11249 … (0xff<<0) // Bits 7:0; Must be written with 8-bit value 0x57 to enable RS-FEC tra…
11251 …//Access:RW DataWidth:0x20 // Bits 15:0. One bit per 10-bit Symbol; Each bit is applied to cor…
11252 … (0xffff<<0) // Bits 15:0. One bit per 10-bit Symbol; When a bit is 1 the test pattern is ap…
11254 … //Access:RW DataWidth:0x20 // Bits 9:0; A 10-bit value which XORed with a 10B symbol FEC enco…
11255 … (0x3ff<<0) // A 10-bit value which will be XORed with a 10B symbol after the…
11259 … 0x00021cUL //Access:RW DataWidth:0x20 // Enable register to control the triggers…
11265 … (0x1<<8) // Indicate full-duplex operation; alw…
11279 … (0x1<<15) // PCS soft-reset command; self-clearing
11284 … (0x1<<2) // Indicate link status; latch-low
11296 …x20 // Local Device Abilities for Autonegotiation. Contents differs for 1000Base-X or SGMII mode.
11297 … (0x1f<<0) // reserved; SGMII:=set to 1 to indicate SGMII to PHY
11299 … (0x1<<5) // Indicate full-duplex support; SGMII…
11301 … (0x1<<6) // Indicate half-duplex support; SGMII…
11305 … (0x1<<8) // Pause Support 2; SGMII:=EEE clock stop enable to PHY
11317 …/ Received Abilities during Autonegotiation. Contents differ depending on 1000Base-X or SGMII mode.
11320 … (0x1<<5) // Indicate full-duplex support; SGMII…
11322 … (0x1<<6) // Indicate half-duplex support; SGMII…
11341 … (0x1<<1) // Autoneg page received indication; latch-high
11345 … 0x00001cUL //Access:RW DataWidth:0x20 // Next Page data to transmit
11356 … (0x1<<15) // Next Pages to follow indication
11369 … (0x1<<15) // Next Pages to follow indication
11388 … (0x1<<1) // Use the SGMII autonegotiation results to set SGMII speed
11392 … (0x1<<4) // Set SGMII half-duplex mode when not …
11397 … supported in all Core variants; Counter is not accurate and intended only to be of help during te…
11413 …Y_K2_E5 (0x1<<1) // Set to 1 to indicate that the…
11436 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11465 … (0x7<<0) // PCS type selection; Writing 0 sets PCS_MODE to 0x03 setting Clause …
11468 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11470 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11472 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11474 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11476 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11478 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11495 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11497 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11499 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11502 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11505 …2_E5 (0x1<<0) // 1=PCS locked to received blocks.
11512 … (0xff<<0) // Errored blocks counter; None roll-over.
11514 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11520 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11521 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11523 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11524 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11526 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11527 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11529 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11530 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11532 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11533 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11535 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11536 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11538 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11539 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11541 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11542 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11549 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11551 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11555 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11556 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11558 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11559 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11561 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11562 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11586 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11587 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11589 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11590 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11592 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11593 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11595 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11596 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11611 … (0xffff<<0) // Scratch Register; Register address to test read and write …
11616 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11617 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11620 …HOLD_K2_E5 (0xf<<0) // A 4-bit value to define the tra…
11622 …0010UL //Access:RW DataWidth:0x20 // Vendor Specific Reg; Define Reduced-XLAUI PMA mode using …
11623 …_K2_E5 (0x1<<0) // Enable Reduced-XLAUI PMA mode using …
11627 …E5 (0xf<<4) // Set VL (0..3) to transmit to RXLAUI lane 0.
11629 …E5 (0xf<<8) // Set VL (0..3) to transmit to RXLAUI lane 1.
11668 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11688 …Y_K2_E5 (0x1<<1) // Set to 1 to indicate that the…
11711 … (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
11740 … (0x7<<0) // PCS type selection; Writing 0 sets PCS_MODE to 0x03 setting Clause …
11743 … (0x1<<0) // When 1, this PCS is 10GBase-R capable.
11745 … (0x1<<1) // When 1, this PCS is 10GBase-X capable.
11747 … (0x1<<2) // When 1, this PCS is 10GBase-W capable.
11749 … (0x1<<3) // When 1, this PCS is 10GBase-T capable.
11751 … (0x1<<4) // When 1, this PCS is 40GBase-R capable.
11753 … (0x1<<5) // When 1, this PCS is 100GBase-R capable.
11770 …_K2_E5 (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
11772 …5 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
11774 … (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
11777 … Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
11780 …2_E5 (0x1<<0) // 1=PCS locked to received blocks.
11787 … (0xff<<0) // Errored blocks counter; None roll-over.
11789 …ER_K2_E5 (0x3f<<8) // BER counter; None roll-over.
11795 … 0x000088UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11796 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11798 … 0x00008cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11799 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11801 … 0x000090UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11802 … (0xffff<<0) // 10GBase-R Test Pattern Seed A…
11804 … 0x000094UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed A…
11805 … (0x3ff<<0) // 10GBase-R Test Pattern Seed A…
11807 … 0x000098UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11808 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11810 … 0x00009cUL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11811 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11813 … 0x0000a0UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11814 … (0xffff<<0) // 10GBase-R Test Pattern Seed B…
11816 … 0x0000a4UL //Access:RW DataWidth:0x20 // 10G Base-R Test Pattern Seed B…
11817 … (0x3ff<<0) // 10GBase-R Test Pattern Seed B…
11824 …TESTPATTERN_K2_E5 (0x1<<2) // Receive test-pattern enable.
11826 …ESTPATTERN_K2_E5 (0x1<<3) // Transmit test-pattern enable.
11830 …0acUL //Access:R DataWidth:0x20 // Test Pattern Error Counter; Clears on read; None roll-over.
11831 … (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
11833 …0000b0UL //Access:R DataWidth:0x20 // BER High Order Counter of BER bits 21:6; None roll-over.
11834 … (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
11836 …00b4UL //Access:R DataWidth:0x20 // Error Blocks High Order Counter bits 21:8; None roll-over.
11837 …2_E5 (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
11853 …00320UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 0; Clears on read; None roll-over.
11854 …_E5 (0xffff<<0) // BIP error counter lane 0; None roll-over.
11856 …00324UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 1; Clears on read; None roll-over.
11857 …_E5 (0xffff<<0) // BIP error counter lane 1; None roll-over.
11859 …00328UL //Access:R DataWidth:0x20 // BIP Error Counter Lane 2; Clears on read; None roll-over.
11860 …_E5 (0xffff<<0) // BIP error counter lane 2; None roll-over.
11862 …0032cUL //Access:R DataWidth:0x20 // BIP Error Counter Lane 3; Clears on read; None roll-over.
11863 …_E5 (0xffff<<0) // BIP error counter lane 3; None roll-over.
11866 … (0xffff<<0) // Scratch Register; Register address to test read and write …
11871 …x20 // Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).
11872 … (0xffff<<0) // A 16-bit value defining the amount of data between markers; (dis…
11875 …HOLD_K2_E5 (0xf<<0) // A 4-bit value to define the tra…
11912 …2_E5 (0x1<<1) // When 0 PCS 4-lane MLD function is …
11962 …- off high-impedance 0x1 - CMU 0 0x3 - Lane 0 0x4 - Lane 1 0x5 - Lane 2 0x6 - Lane 3 0x15 - SoC ci…
11965 …rols the internal analog voltage or current from the respective macro sent to the atest1_o/atest2_…
12199 … (0x1<<4) // Clock gate enable for RX clock output to customer logics
12241 … (0x1<<4) // Clock gate enable for RX clock output to customer logics
12283 … (0x1<<4) // Clock gate enable for RX clock output to customer logics
12325 … (0x1<<4) // Clock gate enable for RX clock output to customer logics
12362 …<0) // PHY error status. 0x0 - no error 0x1 - PHY has an internal error detected by firmware. PHY …
12364 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12365 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit PHY error code. 0x0 - indicates that there i…
12367 …5 (0x1<<0) // Rebug error status. Write 1 to clear.
12383 … 0x000680UL //Access:RW DataWidth:0x8 // lower 8-bits of the 16-bit digital te…
12384 … 0x000684UL //Access:RW DataWidth:0x8 // higher 8-bits of the 16-bit digital te…
12393 …(0x1<<0) // Set if running a 1b simulation. Firmware may check this field to discover its runtime…
12400 …dth:0x8 // Command to the PHY firmware. It is expected that only the APB master writes to the c…
12402 …ew command to the PHY firmware. It is set automatically when CMD is written. It is expected to be …
12412 …h:0x8 // Response to the PHY firmware. It is expected that only the APB master writes to the Re…
12414 …w Response to the PHY firmware. It is set automatically when RSP is written. It is expected to be …
14398 …to allow a different clock frequency from cm0_clk_o. This clock can be used in gearbox application…
14429 …to be muxed into the half-rate TX clock path to provide visibility at the TX driver output. 0x0 -…
14431 …ion from the CMU macro to all lanes macros. 0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV…
14473 …x0 - CMU PLL is not locked 0x1 - indicates that CMU macro has successfully transitioned into the A…
14477 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14478 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14480 …macro error status. 0x0 - no error 0x1 - PHY CMU macro has an internal error detected by firmware.…
14515 … (0x1<<0) // CMU PLL regulator vddha setting. 0x0 - vddha is 1.5V nominal 0x1 - vddha …
14670 … (0x1<<0) // CMU PLL lock detector status. 0x0 - CMU PLL is not locked 0x1 - CMU PLL has locke…
14910 …x0 - CMU PLL is not locked 0x1 - indicates that CMU macro has successfully transitioned into the A…
14914 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14915 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit CMU error code. 0x0 - indicates that there i…
14917 …macro error status. 0x0 - no error 0x1 - PHY CMU macro has an internal error detected by firmware.…
14950 … (0x1<<0) // Select the reference clock. 0 - clk_ref 1- clk_pllref
15091 …1) // Enable for loading freq_offset sr as the offset to establish nominal frequency Freq_offset t…
15204 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
15206 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
15208 …<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission mode 0x1 - loop back parallel data …
15210 … // Near-End Analog NEA loopback mode enable. 0x0 - mission mode 0x1 - loop back quarter rate dat…
15286 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
15290 …) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be se…
15293 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
15336 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
15418 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15419 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
15421 …acro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware.…
15488 … 0x0062fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control input to the CDR
15490 …K2_E5 (0x1<<0) // Binary-coded DLPF control input to the CDR
15493 … (0x1<<0) // Indicates that DLPF control input to CDR is too high
15495 … (0x1<<1) // Indicates that DLPF control input to CDR is too low
15497 …s status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i t…
15500 …means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
15653 … 0x006628UL //Access:RW DataWidth:0x8 // Seed provided to the transmit nonce g…
15655 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
15673 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
15677 …MD has the ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PM…
15684 … (0x1<<0) // Page Received. To clear it, write 1 to it.
15688 … (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
15696 … 0x006650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
15697 … 0x006654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
15701 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
15704 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
15720 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
15722 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
15724 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
15726 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
15728 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
15730 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
15732 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
15734 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
15737 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
15739 …0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. F…
15741 …(0x1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. Fo…
15743 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
15746 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
15751 … (0x1<<1) // base page bit F1. It requests FEC to be turned on when su…
15753 …e bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For pri…
15755 …s FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IE…
15758 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15760 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15762 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15764 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15766 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15768 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15770 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15772 … It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G co…
15825 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
15828 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
15846 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
15848 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
15850 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
15852 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
15854 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
15856 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
15858 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
15860 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
15863 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
15865 …nk partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. F…
15867 …ink partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. Fo…
15869 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
15872 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
15877 … (0x1<<1) // Link partner base page bit F1. It requests FEC to be turned on when su…
15879 …e bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For pri…
15881 …s FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IE…
15884 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
15886 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
15888 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
15890 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
15892 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
15894 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15896 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
15898 … It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G co…
15949 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
15951 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
15953 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
15955 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
15957 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
15959 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
15961 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
15963 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
15966 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
15968 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
15970 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
15972 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
15974 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
15976 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
15978 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
15981 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
15994 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
15996 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
15998 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
16000 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
16002 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
16004 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
16006 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
16008 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
16011 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
16013 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
16015 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
16017 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
16019 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
16021 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
16564 …r IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
16621 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack…
16624 …0_ACK_K2_E5 (0x1<<0) // Set to 1 by firmware when u…
16627 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
16633 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
16641 … (0xf<<0) // Thermometer coded control to adjust the delay bet…
16742 …<<0) // Write 1 to request a command CMD execution. It should be held at 1 until fsm_status0.ack …
16744 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
16748 …E_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changing DFE …
16768 …dge from DFE after command execution. Will be set to 1 after a command is completed, and will clea…
16777 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
16779 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
16781 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
16783 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
16785 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16787 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16789 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16791 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16794 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16796 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16799 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16801 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16804 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16806 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16809 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16811 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16834 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16836 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16839 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16841 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16844 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16846 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16849 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16851 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
17203 …2_E5 (0x1<<0) // Enables the run-length detection digi…
17205 … 0x007410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
17207 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
17209 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
17371 … (0xf<<1) // Selects the pattern to transmitted: 0x1 � P…
17380 … 0x00781cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17381 … 0x007820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
17382 … 0x007824UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
17383 … 0x007828UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
17384 … 0x00782cUL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
17385 … 0x007830UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
17386 … 0x007834UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
17387 …ss:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp_len…
17416 …to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x84…
17420 … (0x1<<6) // Stops the error count from incrementing. Can be used to read back the BER da…
17422 … (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit…
17435 …0x007a50UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern lock.
17436 …0x007a54UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern lock.
17437 …07a58UL //Access:RW DataWidth:0x8 // Maximum number of errors allowed to trigger pattern lock.
17438 …07a5cUL //Access:RW DataWidth:0x8 // Maximum number of errors allowed to trigger pattern lock.
17439 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17440 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
17441 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17442 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
17444 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
17446 …ss:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp_len…
17571 …NT_INIT0_K2_E5 (0x3<<0) // How many times to repeat CTLE adaptati…
17573 …NT_INIT1_K2_E5 (0x3<<2) // How many times to repeat CTLE adaptati…
17590 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
17592 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
17616 …L_K2_E5 (0x3<<0) // Selects which HFG result to use for the initial …
17618 …L_K2_E5 (0x3<<2) // Selects which HFG result to use for the initial …
17665 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Patte…
17717 …07ce4UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
17718 …07ce8UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
17719 …07cecUL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
17770 … (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise proc…
17772 … (0x1<<2) // Output corresponding to link training signal…
17776 …d as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width Should be set to 500ns for 802.3 comp…
17778 … 0x007e0cUL //Access:RW DataWidth:0x8 // Number of additional frames to send after both rece…
17783 …CK_K2_E5 (0x1<<0) // Input to LTSM that receiver h…
17785 …ED_K2_E5 (0x1<<1) // Input to LTSM indicating that…
17787 …X_READY_K2_E5 (0x1<<2) // Input to LTSM indicating that…
17794 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
17796 … (0x1<<4) // Output from LSM corresponding to 802.3 defined local_…
17801 …ess:RW DataWidth:0x8 // Initial PRBS LFSR seed. This needs to be set according to the requir…
17806 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
17810 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
17817 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
17821 …E5 (0x3<<4) // Status report field for pre-cursor tap.
17823 …Y_K2_E5 (0x1<<6) // Status report field to indicate local recei…
17838 …/ This is the 802.3 defined training variable. It should be set according to corresponding LTSM o…
17843 …8 // Maximum number of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.
17857 … (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
17864 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
17868 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
17875 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
17879 … (0x3<<4) // Received status report field for pre-cursor tap.
17881 … (0x1<<6) // Received status report field to indicate local recei…
17886 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
17888 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
17890 …<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission mode 0x1 - loop back parallel data …
17892 … // Near-End Analog NEA loopback mode enable. 0x0 - mission mode 0x1 - loop back quarter rate dat…
17968 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
17972 …) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be se…
17975 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
18018 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
18100 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18101 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
18103 …acro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware.…
18170 … 0x0082fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control input to the CDR
18172 …K2_E5 (0x1<<0) // Binary-coded DLPF control input to the CDR
18175 … (0x1<<0) // Indicates that DLPF control input to CDR is too high
18177 … (0x1<<1) // Indicates that DLPF control input to CDR is too low
18179 …s status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i t…
18182 …means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
18335 … 0x008628UL //Access:RW DataWidth:0x8 // Seed provided to the transmit nonce g…
18337 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
18355 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
18359 …MD has the ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PM…
18366 … (0x1<<0) // Page Received. To clear it, write 1 to it.
18370 … (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
18378 … 0x008650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
18379 … 0x008654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
18383 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
18386 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
18402 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
18404 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
18406 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
18408 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
18410 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
18412 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
18414 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
18416 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
18419 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
18421 …0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. F…
18423 …(0x1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. Fo…
18425 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
18428 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
18433 … (0x1<<1) // base page bit F1. It requests FEC to be turned on when su…
18435 …e bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For pri…
18437 …s FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IE…
18440 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18442 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18444 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18446 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18448 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18450 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18452 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18454 … It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G co…
18507 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
18510 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
18528 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
18530 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
18532 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
18534 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
18536 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
18538 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
18540 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
18542 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
18545 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
18547 …nk partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. F…
18549 …ink partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. Fo…
18551 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
18554 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
18559 … (0x1<<1) // Link partner base page bit F1. It requests FEC to be turned on when su…
18561 …e bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For pri…
18563 …s FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IE…
18566 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
18568 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
18570 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
18572 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
18574 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
18576 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
18578 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
18580 … It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G co…
18631 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
18633 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
18635 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
18637 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
18639 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
18641 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
18643 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
18645 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
18648 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
18650 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
18652 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
18654 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
18656 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
18658 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
18660 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
18663 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
18676 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
18678 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
18680 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
18682 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
18684 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
18686 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
18688 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
18690 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
18693 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
18695 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
18697 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
18699 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
18701 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
18703 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
19246 …r IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
19303 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack…
19306 …0_ACK_K2_E5 (0x1<<0) // Set to 1 by firmware when u…
19309 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
19315 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
19323 … (0xf<<0) // Thermometer coded control to adjust the delay bet…
19424 …<<0) // Write 1 to request a command CMD execution. It should be held at 1 until fsm_status0.ack …
19426 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
19430 …E_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changing DFE …
19450 …dge from DFE after command execution. Will be set to 1 after a command is completed, and will clea…
19459 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
19461 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
19463 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
19465 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
19467 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19469 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19471 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19473 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
19476 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
19478 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19481 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
19483 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19486 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
19488 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19491 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
19493 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
19516 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
19518 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19521 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
19523 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19526 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
19528 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19531 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
19533 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
19885 …2_E5 (0x1<<0) // Enables the run-length detection digi…
19887 … 0x009410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
19889 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
19891 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
20053 … (0xf<<1) // Selects the pattern to transmitted: 0x1 � P…
20062 … 0x00981cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20063 … 0x009820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
20064 … 0x009824UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
20065 … 0x009828UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
20066 … 0x00982cUL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
20067 … 0x009830UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
20068 … 0x009834UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
20069 …ss:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp_len…
20098 …to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x84…
20102 … (0x1<<6) // Stops the error count from incrementing. Can be used to read back the BER da…
20104 … (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit…
20117 …0x009a50UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern lock.
20118 …0x009a54UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern lock.
20119 …09a58UL //Access:RW DataWidth:0x8 // Maximum number of errors allowed to trigger pattern lock.
20120 …09a5cUL //Access:RW DataWidth:0x8 // Maximum number of errors allowed to trigger pattern lock.
20121 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20122 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
20123 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20124 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
20126 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
20128 …ss:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp_len…
20253 …NT_INIT0_K2_E5 (0x3<<0) // How many times to repeat CTLE adaptati…
20255 …NT_INIT1_K2_E5 (0x3<<2) // How many times to repeat CTLE adaptati…
20272 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
20274 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
20298 …L_K2_E5 (0x3<<0) // Selects which HFG result to use for the initial …
20300 …L_K2_E5 (0x3<<2) // Selects which HFG result to use for the initial …
20347 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Patte…
20399 …09ce4UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
20400 …09ce8UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
20401 …09cecUL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
20452 … (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise proc…
20454 … (0x1<<2) // Output corresponding to link training signal…
20458 …d as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width Should be set to 500ns for 802.3 comp…
20460 … 0x009e0cUL //Access:RW DataWidth:0x8 // Number of additional frames to send after both rece…
20465 …CK_K2_E5 (0x1<<0) // Input to LTSM that receiver h…
20467 …ED_K2_E5 (0x1<<1) // Input to LTSM indicating that…
20469 …X_READY_K2_E5 (0x1<<2) // Input to LTSM indicating that…
20476 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
20478 … (0x1<<4) // Output from LSM corresponding to 802.3 defined local_…
20483 …ess:RW DataWidth:0x8 // Initial PRBS LFSR seed. This needs to be set according to the requir…
20488 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
20492 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
20499 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
20503 …E5 (0x3<<4) // Status report field for pre-cursor tap.
20505 …Y_K2_E5 (0x1<<6) // Status report field to indicate local recei…
20520 …/ This is the 802.3 defined training variable. It should be set according to corresponding LTSM o…
20525 …8 // Maximum number of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.
20539 … (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
20546 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
20550 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
20557 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
20561 … (0x3<<4) // Received status report field for pre-cursor tap.
20563 … (0x1<<6) // Received status report field to indicate local recei…
20568 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
20570 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
20572 …<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission mode 0x1 - loop back parallel data …
20574 … // Near-End Analog NEA loopback mode enable. 0x0 - mission mode 0x1 - loop back quarter rate dat…
20650 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
20654 …) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be se…
20657 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
20700 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
20782 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20783 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
20785 …acro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware.…
20852 … 0x00a2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control input to the CDR
20854 …K2_E5 (0x1<<0) // Binary-coded DLPF control input to the CDR
20857 … (0x1<<0) // Indicates that DLPF control input to CDR is too high
20859 … (0x1<<1) // Indicates that DLPF control input to CDR is too low
20861 …s status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i t…
20864 …means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
21017 … 0x00a628UL //Access:RW DataWidth:0x8 // Seed provided to the transmit nonce g…
21019 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
21037 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
21041 …MD has the ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PM…
21048 … (0x1<<0) // Page Received. To clear it, write 1 to it.
21052 … (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
21060 … 0x00a650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
21061 … 0x00a654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
21065 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
21068 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
21084 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
21086 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
21088 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
21090 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
21092 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
21094 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
21096 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
21098 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
21101 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
21103 …0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. F…
21105 …(0x1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. Fo…
21107 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
21110 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
21115 … (0x1<<1) // base page bit F1. It requests FEC to be turned on when su…
21117 …e bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For pri…
21119 …s FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IE…
21122 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21124 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21126 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21128 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21130 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21132 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21134 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21136 … It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G co…
21189 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
21192 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
21210 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
21212 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
21214 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
21216 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
21218 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
21220 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
21222 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
21224 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
21227 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
21229 …nk partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. F…
21231 …ink partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. Fo…
21233 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
21236 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
21241 … (0x1<<1) // Link partner base page bit F1. It requests FEC to be turned on when su…
21243 …e bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For pri…
21245 …s FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IE…
21248 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
21250 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
21252 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
21254 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
21256 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
21258 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
21260 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
21262 … It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G co…
21313 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
21315 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
21317 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
21319 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
21321 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
21323 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
21325 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
21327 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
21330 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
21332 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
21334 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
21336 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
21338 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
21340 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
21342 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
21345 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
21358 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
21360 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
21362 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
21364 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
21366 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
21368 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
21370 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
21372 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
21375 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
21377 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
21379 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
21381 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
21383 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
21385 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
21928 …r IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
21985 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack…
21988 …0_ACK_K2_E5 (0x1<<0) // Set to 1 by firmware when u…
21991 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
21997 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
22005 … (0xf<<0) // Thermometer coded control to adjust the delay bet…
22106 …<<0) // Write 1 to request a command CMD execution. It should be held at 1 until fsm_status0.ack …
22108 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
22112 …E_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changing DFE …
22132 …dge from DFE after command execution. Will be set to 1 after a command is completed, and will clea…
22141 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
22143 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
22145 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
22147 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
22149 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22151 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22153 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22155 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
22158 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
22160 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
22163 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
22165 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
22168 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
22170 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
22173 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
22175 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
22198 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
22200 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
22203 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
22205 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
22208 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
22210 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
22213 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
22215 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
22567 …2_E5 (0x1<<0) // Enables the run-length detection digi…
22569 … 0x00b410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
22571 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
22573 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
22735 … (0xf<<1) // Selects the pattern to transmitted: 0x1 � P…
22744 … 0x00b81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22745 … 0x00b820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
22746 … 0x00b824UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
22747 … 0x00b828UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
22748 … 0x00b82cUL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
22749 … 0x00b830UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
22750 … 0x00b834UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
22751 …ss:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp_len…
22780 …to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x84…
22784 … (0x1<<6) // Stops the error count from incrementing. Can be used to read back the BER da…
22786 … (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit…
22799 …0x00ba50UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern lock.
22800 …0x00ba54UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern lock.
22801 …0ba58UL //Access:RW DataWidth:0x8 // Maximum number of errors allowed to trigger pattern lock.
22802 …0ba5cUL //Access:RW DataWidth:0x8 // Maximum number of errors allowed to trigger pattern lock.
22803 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22804 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
22805 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22806 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
22808 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
22810 …ss:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp_len…
22935 …NT_INIT0_K2_E5 (0x3<<0) // How many times to repeat CTLE adaptati…
22937 …NT_INIT1_K2_E5 (0x3<<2) // How many times to repeat CTLE adaptati…
22954 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
22956 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
22980 …L_K2_E5 (0x3<<0) // Selects which HFG result to use for the initial …
22982 …L_K2_E5 (0x3<<2) // Selects which HFG result to use for the initial …
23029 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Patte…
23081 …0bce4UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
23082 …0bce8UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
23083 …0bcecUL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
23134 … (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise proc…
23136 … (0x1<<2) // Output corresponding to link training signal…
23140 …d as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width Should be set to 500ns for 802.3 comp…
23142 … 0x00be0cUL //Access:RW DataWidth:0x8 // Number of additional frames to send after both rece…
23147 …CK_K2_E5 (0x1<<0) // Input to LTSM that receiver h…
23149 …ED_K2_E5 (0x1<<1) // Input to LTSM indicating that…
23151 …X_READY_K2_E5 (0x1<<2) // Input to LTSM indicating that…
23158 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
23160 … (0x1<<4) // Output from LSM corresponding to 802.3 defined local_…
23165 …ess:RW DataWidth:0x8 // Initial PRBS LFSR seed. This needs to be set according to the requir…
23170 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
23174 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
23181 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
23185 …E5 (0x3<<4) // Status report field for pre-cursor tap.
23187 …Y_K2_E5 (0x1<<6) // Status report field to indicate local recei…
23202 …/ This is the 802.3 defined training variable. It should be set according to corresponding LTSM o…
23207 …8 // Maximum number of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.
23221 … (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
23228 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
23232 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
23239 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
23243 … (0x3<<4) // Received status report field for pre-cursor tap.
23245 … (0x1<<6) // Received status report field to indicate local recei…
23250 … // RX clock loopback mode enable. 0x0 - mission mode 0x1 - select recovered clock from CDR as s…
23252 … (0x1<<1) // TX clock loopback mode enable. 0x0 - mission mode 0x1 - MUX half-rate TX…
23254 …<2) // Far-End Analog FEA loopback mode enable. 0x0 - mission mode 0x1 - loop back parallel data …
23256 … // Near-End Analog NEA loopback mode enable. 0x0 - mission mode 0x1 - loop back quarter rate dat…
23332 …a from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4…
23336 …) // Controls tx_en for Far-End-Digital FED loopback mode. In FED loopback mode, tx_en will be se…
23339 … mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
23382 …de value for TX. It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-…
23464 …cess:RW DataWidth:0x8 // lower 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23465 …ess:RW DataWidth:0x8 // higher 8-bits of 16-bit lane error code. 0x0 - indicates that there …
23467 …acro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware.…
23534 … 0x00c2fcUL //Access:R DataWidth:0x8 // Binary-coded DLPF control input to the CDR
23536 …K2_E5 (0x1<<0) // Binary-coded DLPF control input to the CDR
23539 … (0x1<<0) // Indicates that DLPF control input to CDR is too high
23541 … (0x1<<1) // Indicates that DLPF control input to CDR is too low
23543 …s status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i t…
23546 …means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
23699 … 0x00c628UL //Access:RW DataWidth:0x8 // Seed provided to the transmit nonce g…
23701 … (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
23719 …-Negotiation ability bit shall be set to one to indicate that the link partner is able to particip…
23723 …MD has the ability to perform Auto-Negotiation. When read as a zero, it indicates that the PMA/PM…
23730 … (0x1<<0) // Page Received. To clear it, write 1 to it.
23734 … (0x1<<2) // Autoneg Parallel Detection Fault. Write 1 to clear it.
23742 … 0x00c650UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 7…
23743 … 0x00c654UL //Access:R DataWidth:0x8 // One-hot sticky capture of AN FSM states. Bits 1…
23747 … (0x7<<5) // Echoed Nonce Field bits 2-0. AN controller gen…
23750 … (0x3<<0) // Echoed Nonce Field bits 4-3. AN controller g…
23766 …ITY_1G_KX_K2_E5 (0x1<<0) // 1000Base-KX technology adverti…
23768 …LITY_10G_KX4_K2_E5 (0x1<<1) // 10GBase-KX4 technology advert…
23770 …LITY_10G_KR_K2_E5 (0x1<<2) // 10GBase-KR technology adverti…
23772 …LITY_40G_KR4_K2_E5 (0x1<<3) // 40GBase-KR4 technology advert…
23774 …LITY_40G_CR4_K2_E5 (0x1<<4) // 40GBase-CR4 technology advert…
23776 …ITY_100G_CR10_K2_E5 (0x1<<5) // 100GBase-CR10 technology adver…
23778 …ITY_100G_KP4_K2_E5 (0x1<<6) // 100GBase-KP4 technology advert…
23780 …ITY_100G_KR4_K2_E5 (0x1<<7) // 100GBase-KR4 technology advert…
23783 …ITY_100G_CR4_K2_E5 (0x1<<0) // 100GBase-CR4 technology advert…
23785 …0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. F…
23787 …(0x1<<2) // 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. Fo…
23789 …2_E5 (0x1f<<3) // technology advertised ability Field A15-A11
23792 …2_E5 (0x7f<<0) // technology advertised ability Field A22-A16
23797 … (0x1<<1) // base page bit F1. It requests FEC to be turned on when su…
23799 …e bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For pri…
23801 …s FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IE…
23804 … (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23806 … (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23808 … (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23810 … (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23812 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23814 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23816 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23818 … It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G co…
23871 …0_K2_E5 (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
23874 …3_K2_E5 (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
23892 …K2_E5 (0x1<<0) // Link partner 1000Base-KX technology adverti…
23894 …X4_K2_E5 (0x1<<1) // Link partner 10GBase-KX4 technology advert…
23896 …R_K2_E5 (0x1<<2) // Link partner 10GBase-KR technology adverti…
23898 …R4_K2_E5 (0x1<<3) // Link partner 40GBase-KR4 technology advert…
23900 …R4_K2_E5 (0x1<<4) // Link partner 40GBase-CR4 technology advert…
23902 …R10_K2_E5 (0x1<<5) // Link partner 100GBase-CR10 technology adver…
23904 …P4_K2_E5 (0x1<<6) // Link partner 100GBase-KP4 technology advert…
23906 …R4_K2_E5 (0x1<<7) // Link partner 100GBase-KR4 technology advert…
23909 …R4_K2_E5 (0x1<<0) // Link partner 100GBase-CR4 technology advert…
23911 …nk partner 25GBase-GR-S KR or CR technology advertised ability. It is defined in IEEE 802.3by. F…
23913 …ink partner 25GBase-GR KR or CR technology advertised ability. It is defined in IEEE 802.3by. Fo…
23915 … (0x1f<<3) // Link partner technology advertised ability Field A15-A11
23918 … (0x7f<<0) // Link partner technology advertised ability Field A22-A16
23923 … (0x1<<1) // Link partner base page bit F1. It requests FEC to be turned on when su…
23925 …e bit F2. It requests RS-FEC for 25G-GR 25G-KR/-CR link. It is defined in IEEE 802.3by. For pri…
23927 …s FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link. It is defined in IE…
23930 … (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium sp…
23932 … (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium sp…
23934 … (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium sp…
23936 … (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium sp…
23938 …advertised FEC field 0. It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specif…
23940 …EC field 1. It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
23942 … 2. It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/…
23944 … It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G co…
23995 … (0x1<<0) // Resolution result for 1000Base-KX. It is valid when…
23997 … (0x1<<1) // Resolution result for 10GBase-KX4. It is valid whe…
23999 … (0x1<<2) // Resolution result for 10GBase-KR. It is valid when…
24001 … (0x1<<3) // Resolution result for 40GBase-KR4. It is valid whe…
24003 … (0x1<<4) // Resolution result for 40GBase-CR4. It is valid whe…
24005 … (0x1<<5) // Resolution result for 100GBase-CR10. It is valid wh…
24007 … (0x1<<6) // Resolution result for 100GBase-KP4. It is valid whe…
24009 … (0x1<<7) // Resolution result for 100GBase-KR4. It is valid whe…
24012 … (0x1<<0) // Resolution result for 100GBase-CR4. It is valid whe…
24014 … (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR. It is v…
24016 … (0x1<<2) // Resolution result for 25GBase-GR KR or CR. It is v…
24018 … (0x1<<3) // Resolution result for 25GBase-KR. It is valid when…
24020 … (0x1<<4) // Resolution result for 25GBase-CR4. It is valid whe…
24022 … (0x1<<5) // Resolution result for 50GBase-KR2. It is valid whe…
24024 … (0x1<<6) // Resolution result for 50GBase-CR2. It is valid whe…
24027 … (0x1<<0) // Resolution result for Reed-Solomon FEC. It is v…
24040 …LITY_1G_KX_K2_E5 (0x1<<0) // link_status for 1000Base-KX
24042 …LITY_10G_KX4_K2_E5 (0x1<<1) // link_status for 10GBase-KX4
24044 …ILITY_10G_KR_K2_E5 (0x1<<2) // link_status for 10GBase-KR
24046 …LITY_40G_KR4_K2_E5 (0x1<<3) // link_status for 40GBase-KR4
24048 …LITY_40G_CR4_K2_E5 (0x1<<4) // link_status for 40GBase-CR4
24050 …TY_100G_CR10_K2_E5 (0x1<<5) // link_status for 100GBase-CR10
24052 …ITY_100G_KP4_K2_E5 (0x1<<6) // link_status for 100GBase-KP4
24054 …ITY_100G_KR4_K2_E5 (0x1<<7) // link_status for 100GBase-KR4
24057 …ITY_100G_CR4_K2_E5 (0x1<<0) // link_status for 100GBase-CR4
24059 … (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
24061 …ILITY_25G_KR_K2_E5 (0x1<<3) // link_status for 25GBase-KR
24063 …LITY_25G_CR_K2_E5 (0x1<<4) // link_status for 25GBase-CR4
24065 …LITY_50G_KR2_K2_E5 (0x1<<5) // link_status for 50GBase-KR2
24067 …LITY_50G_CR2_K2_E5 (0x1<<6) // link_status for 50GBase-CR2
24610 …r IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
24667 … (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack…
24670 …0_ACK_K2_E5 (0x1<<0) // Set to 1 by firmware when u…
24673 … (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
24679 … (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
24687 … (0xf<<0) // Thermometer coded control to adjust the delay bet…
24788 …<<0) // Write 1 to request a command CMD execution. It should be held at 1 until fsm_status0.ack …
24790 … (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
24794 …E_BEFORE_EVAL_K2_E5 (0x1<<7) // Set it to 1 when changing DFE …
24814 …dge from DFE after command execution. Will be set to 1 after a command is completed, and will clea…
24823 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
24825 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
24827 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
24829 … FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap…
24831 … (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24833 … (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24835 … (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24837 … (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
24840 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
24842 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
24845 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
24847 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
24850 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
24852 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
24855 …fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
24857 …ap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
24880 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
24882 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
24885 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
24887 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
24890 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
24892 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
24895 … fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
24897 …tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
25249 …2_E5 (0x1<<0) // Enables the run-length detection digi…
25251 … 0x00d410UL //Access:RW DataWidth:0x8 // Value of run-length which will tri…
25253 … (0x1<<0) // Indicates that the run-length filter is currently exceeding the specifie…
25255 … (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the speci…
25417 … (0xf<<1) // Selects the pattern to transmitted: 0x1 � P…
25426 … 0x00d81cUL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25427 … 0x00d820UL //Access:RW DataWidth:0x8 // Number of cycles between single bit-error injection
25428 … 0x00d824UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
25429 … 0x00d828UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
25430 … 0x00d82cUL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
25431 … 0x00d830UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
25432 … 0x00d834UL //Access:RW DataWidth:0x8 // Sets the Tx data bits to be flipped.
25433 …ss:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp_len…
25462 …to search for: 0x1 � PRBS 0xC1 0x2 � PRBS 0x221 0x3 � PRBS 0xA01 0x4 � PRBS 0xC001 0x5 � PRBS 0x84…
25466 … (0x1<<6) // Stops the error count from incrementing. Can be used to read back the BER da…
25468 … (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle. This will cause the bit…
25481 …0x00da50UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern lock.
25482 …0x00da54UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern lock.
25483 …0da58UL //Access:RW DataWidth:0x8 // Maximum number of errors allowed to trigger pattern lock.
25484 …0da5cUL //Access:RW DataWidth:0x8 // Maximum number of errors allowed to trigger pattern lock.
25485 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25486 …UL //Access:RW DataWidth:0x8 // Size of error sampling window to trigger pattern loss-of-lock.
25487 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25488 …//Access:RW DataWidth:0x8 // Minimum number of errors allowed to trigger pattern loss-of-lock.
25490 … (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
25492 …ss:RW DataWidth:0x8 // Determines the length of the UDP. Must be set to d160 modulus udp_len…
25617 …NT_INIT0_K2_E5 (0x3<<0) // How many times to repeat CTLE adaptati…
25619 …NT_INIT1_K2_E5 (0x3<<2) // How many times to repeat CTLE adaptati…
25636 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
25638 …and-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loo…
25662 …L_K2_E5 (0x3<<0) // Selects which HFG result to use for the initial …
25664 …L_K2_E5 (0x3<<2) // Selects which HFG result to use for the initial …
25711 … (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Patte…
25763 …0dce4UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
25764 …0dce8UL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
25765 …0dcecUL //Access:RW DataWidth:0x8 // How often in ms to run continuous adaptations 1ms to ~27…
25816 … (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise proc…
25818 … (0x1<<2) // Output corresponding to link training signal…
25822 …d as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width Should be set to 500ns for 802.3 comp…
25824 … 0x00de0cUL //Access:RW DataWidth:0x8 // Number of additional frames to send after both rece…
25829 …CK_K2_E5 (0x1<<0) // Input to LTSM that receiver h…
25831 …ED_K2_E5 (0x1<<1) // Input to LTSM indicating that…
25833 …X_READY_K2_E5 (0x1<<2) // Input to LTSM indicating that…
25840 …e. This value is only visible internally, and is not the signal_det value driven to PHY top-level.
25842 … (0x1<<4) // Output from LSM corresponding to 802.3 defined local_…
25847 …ess:RW DataWidth:0x8 // Initial PRBS LFSR seed. This needs to be set according to the requir…
25852 … (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 � h…
25856 … (0x3<<4) // Coefficient update request field for pre-cursor tap.
25863 … (0x3<<0) // Status report field for post-cursor tap. 2'b00 � n…
25867 …E5 (0x3<<4) // Status report field for pre-cursor tap.
25869 …Y_K2_E5 (0x1<<6) // Status report field to indicate local recei…
25884 …/ This is the 802.3 defined training variable. It should be set according to corresponding LTSM o…
25889 …8 // Maximum number of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.
25903 … (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
25910 … (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 � h…
25914 … (0x3<<4) // Received coefficient update request field for pre-cursor tap.
25921 … (0x3<<0) // Received status report field for post-cursor tap. 2'b00 � n…
25925 … (0x3<<4) // Received status report field for pre-cursor tap.
25927 … (0x1<<6) // Received status report field to indicate local recei…
25932 … (0xf<<0) // Static divider control for SOC0 The only access to this divider. Not an…
25934 … (0xf<<4) // Static divider control for SOC1 The only access to this divider. Not an…
25937 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
25941 … (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divider. Not an…
25946 … (0x7<<0) // Static divider control for the SSC block The only access to this divider. Not an…
25948 …<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
25950 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
25953 …AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
25965 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25966 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25967 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25969 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
25971 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
25972 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
25973 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
25974 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
25975 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
25976 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
25977 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
25978 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
25979 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
25980 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
25981 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
25982 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
25983 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
25984 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
25985 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
25986 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26004 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
26006 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
26008 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
26010 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26013 …lowing functions: [0] - active high, Override Enable [1] - SOC clock output enabl…
26015 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26017 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26019 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
26022 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26024 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26026 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26028 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26031 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
26033 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26035 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26037 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
26040 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
26042 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
26044 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
26096 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
26098 …00174UL //Access:RW DataWidth:0x8 // Number of reference clock cycles to count after qsample …
26100 … (0x3<<0) // Number of reference clock cycles to count after qsample …
26102 …E5 (0x1<<2) // State of qsample for PLL to be considered locked
26104 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
26109 …RCE_ILF_O_K2_E5 (0x3<<2) // CMU loop filter force to common mode
26134 …HB_PMA_CM_PFD_FORCE_DN_O_K2_E5 (0x1<<0) // Force PFD to output down
26136 …_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5 (0x1<<1) // Force PFD to output up
26138 …2_E5 (0x1<<2) // Override enable for overriding N-div value
26152 …_CM_I_DROPI_O_K2_E5 (0x1<<2) // Enable to reduce charge pump r…
26157 …1_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
26198 …sents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not ac…
26199 …sents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not ac…
26201 …sents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not ac…
26207 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
26214 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
26216 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
26227 …MP_CAL_OVR_EN_O_K2_E5 (0x1<<7) // override enable to use above value
26229 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
26231 …P_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
26243 …s:RW DataWidth:0x8 // In txterm calibration, the number refclk cycles to wait before sampling…
26245 … (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling…
26247 … (0x7<<1) // in txterm calibration, the number refclk cycles to wait before sampling…
26249 … (0xf<<4) // in txterm calibration, the number of samples to take from the same c…
26252 …set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to…
26261 …7:5 amux_ena[2:0] Bit 4:0 amux_sel_o[4:0] For detailed description please refer to Phy User manual.
26263 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
26271 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
26273 …BUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
26285 … 0x000264UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
26286 … 0x000268UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
26287 …Varies depending on function number. _13:06 - Address of first command to run _05:00 - Number of c…
26523 … 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b010 - pma_lX_rxb_iRecovered byte clock 3'b011 - ck_soc1_int…
26525 … (0x1<<3) // Clock divider for TX path branch 1 : 0-No division, 1- Divide by 2
26527 …h branch 2 clock : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b011 - ck_soc1_int_root 3'b010,3'b100,3'b1…
26529 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
26532 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26534 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
26536 …ck : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b0…
26538 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
26541 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26543 … (0x1<<3) // Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2
26545 …- qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmi…
26547 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
26550 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
26552 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
26555 …0_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
26557 … (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an…
26560 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divid…
26562 … (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1-…
26567 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
26569 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
26575 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
26577 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
26582 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
26584 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
26586 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26587 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
26588 …0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer to bist_gen…
26589 …0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer to bist_gen…
26590 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
26592 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
26599 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
26607 …. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This …
26609 …. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This …
26613 … (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
26619 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
26620 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26621 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26622 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26623 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
26631 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
26632 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
26633 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
26634 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
26635 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
26636 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
26637 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
26638 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
26639 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
26640 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
26641 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
26642 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
26643 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
26644 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
26645 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
26646 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
26647 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
26648 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
26649 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
26650 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
26655 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
26657 …E5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
26659 …_K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
26667 …e State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data…
26675 …UL //Access:RW DataWidth:0x8 // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
26677 … (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
26679 …ertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA c…
26680 …ertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA c…
26691 …mber of cycles of low signal detect output required for RX electrical idle to be declared. Clock c…
26695 …mber of cycles of low signal detect output required for RX electrical idle to be declared. Clock c…
26712 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
26714 …ed, without CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration …
26716 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
26720 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26721 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26722 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26724 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
26726 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
26736 … 0x001140UL //Access:RW DataWidth:0x8 // Number of cycles to wait before forcing …
26738 …T_TIMER_LEN_O_9_8_K2_E5 (0x3<<0) // Number of cycles to wait before forcing …
26750 … 0x001148UL //Access:RW DataWidth:0x8 // Number of cycles to wait before entering…
26754 …K_TIMER_LEN_O_9_8_K2_E5 (0x3<<0) // Number of cycles to wait before entering…
26758 …2_E5 (0x1<<4) // Control signal to force decoder into l…
26765 …5 (0x1<<2) // HS recovered clock to transmit loopback en…
26776 …_O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
26778 …0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor m…
26783 …_O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
26810 …(0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor m…
26828 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
26830 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
26846 … (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative pol…
26863 …X_CXP_MARGIN_K2_E5 (0xf<<0) // Value to minus/add from the c…
26865 …X_CXN_MARGIN_K2_E5 (0xf<<4) // Value to minus/add from the c…
26868 … (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling…
26870 … (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling…
26873 … (0xf<<0) // in txterm calibration, the number of samples to take from the same c…
26875 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
26877 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
26881 … (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_t…
26894 … 0x0011f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
26962 …_K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
26964 …K2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
26978 …SAMPLES_6_0_K2_E5 (0x7f<<0) // Max number of samples to be used for CMP Offs…
26990 … (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
27000 … (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE …
27005 … (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain…
27007 … (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_au…
27046 …set to 0 8-bit or 10-bit mode. 2'b11: the wo…
27048 …et to 0 10-bit or 20-bit mode. 2'b11: the mod…
27050 … 3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
27075 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
27087 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
27092 …to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 b…
27095 …to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 b…
27190 … (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
27192 … (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
27194 … (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
27198 … (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
27204 … offset from the midpoint code 127/128 that must be met for the comparator to be selected as adapt…
27239 …_ADAPT_USING_DLEV_GO_O_K2_E5 (0x1<<0) // Instucts to start TAP adapt usin…
27258 …G_PATT_O_K2_E5 (0x1<<5) // Forces the positive dlev training pattern to be used
27260 …G_PATT_O_K2_E5 (0x1<<6) // Forces the negative dlev training pattern to be used
27359 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
27361 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27363 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27365 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27369 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
27372 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27374 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27376 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27378 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
27380 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27382 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27387 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
27389 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
27402 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit st…
27407 …<0) // An internal FIFO is included to handle the communication between the external 64-bit data a…
27409 … (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to…
27411 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
27418 …ation calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
27431 … (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_l…
27433 …_SKIP_CDR_GEN3_O_K2_E5 (0x1<<1) // To skip cdr calibration…
27435 …_SKIP_CDR_GEN12_O_K2_E5 (0x1<<2) // To skip cdr calibration…
27439 … 0x0014ecUL //Access:RW DataWidth:0x8 // Delays the beacon_ena propagation to PMA
27441 …YED_COUNT_NUMBER_O_11_8_K2_E5 (0xf<<0) // Delays the beacon_ena propagation to PMA
27462 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
27464 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
27468 …ENA_O_K2_E5 (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
27470 …_O_K2_E5 (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
27481 …to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1'…
27488 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
27498 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
27501 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27503 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
27551 … (0x3<<0) // Static divider control for Lane GCFSM clock The only access to this divider. Not an…
27553 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
27554 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
27555 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
27556 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
27557 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
27558 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
27559 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
27560 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
27561 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
27562 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
27563 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
27564 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
27565 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
27566 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
27567 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
27568 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
27571 …es depending on function number. Bits 15-7: Address of first command to run Bits: 6-0: Number of…
27640 …or MFSM state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity …
27641 …or MFSM state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity …
27978 …_O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a programmabl…
27980 …O_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a programmabl…
27994 …E5 (0xf<<0) // Number of wait cycles for the CDR to lock [3:0] times 64
27996 …epeat of calibration for rate switch or electrical idle exit. Calibrations to be performed are sel…
27998 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of u…
28000 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
28002 …ONT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
28004 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
28005 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
28006 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
28007 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
28008 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
28009 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
28010 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
28014 …ECAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
28023 …ATE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
28054 …estbus select for comp_offset and tap_offset 1: Raw output from i_dfe_tap_dc_offset 0: Input to pma
28173 …NE_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
28175 …ADAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
28637 …E_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
28896 … (0xf<<0) // Static divider control for SOC0 The only access to this divider. Not an…
28898 … (0xf<<4) // Static divider control for SOC1 The only access to this divider. Not an…
28901 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
28905 … (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divider. Not an…
28910 … (0x7<<0) // Static divider control for the SSC block The only access to this divider. Not an…
28912 …<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
28914 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
28917 …_AHB_PMA_CM_DIVNSEL_O_6_0_K2_E5 (0x7f<<0) // CMU N-divider setting
28929 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28930 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28931 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28933 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
28935 … 0x003028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
28936 … 0x00302cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
28937 … 0x003030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
28938 … 0x003034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
28939 … 0x003038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
28940 … 0x00303cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
28941 … 0x003040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
28942 … 0x003044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
28943 … 0x003048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
28944 … 0x00304cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
28945 … 0x003050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
28946 … 0x003054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
28947 … 0x003058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
28948 … 0x00305cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
28949 … 0x003060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
28950 … 0x003064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
28968 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
28970 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
28972 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
28974 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28977 …lowing functions: [0] - active high, Override Enable [1] - SOC clock output enabl…
28979 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28981 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28983 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
28986 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28988 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28990 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28992 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
28995 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
28997 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
28999 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29001 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29004 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29006 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29008 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29060 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29062 …03174UL //Access:RW DataWidth:0x8 // Number of reference clock cycles to count after qsample …
29064 … (0x3<<0) // Number of reference clock cycles to count after qsample …
29066 …_E5 (0x1<<2) // State of qsample for PLL to be considered locked
29068 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29073 …ORCE_ILF_O_K2_E5 (0x3<<2) // CMU loop filter force to common mode
29098 …AHB_PMA_CM_PFD_FORCE_DN_O_K2_E5 (0x1<<0) // Force PFD to output down
29100 …8_AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5 (0x1<<1) // Force PFD to output up
29102 …K2_E5 (0x1<<2) // Override enable for overriding N-div value
29116 …A_CM_I_DROPI_O_K2_E5 (0x1<<2) // Enable to reduce charge pump r…
29121 …01_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29162 …sents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not ac…
29163 …sents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not ac…
29165 …sents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not ac…
29171 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29178 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29180 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29191 …EMP_CAL_OVR_EN_O_K2_E5 (0x1<<7) // override enable to use above value
29193 … 0x0031e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29195 …MP_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29207 …s:RW DataWidth:0x8 // In txterm calibration, the number refclk cycles to wait before sampling…
29209 … (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling…
29211 … (0x7<<1) // in txterm calibration, the number refclk cycles to wait before sampling…
29213 … (0xf<<4) // in txterm calibration, the number of samples to take from the same c…
29216 …set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to…
29227 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
29235 … 0x003210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29237 …TBUS_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29249 … 0x003264UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29250 … 0x003268UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29251 …Varies depending on function number. _13:06 - Address of first command to run _05:00 - Number of c…
29487 … (0xf<<0) // Static divider control for SOC0 The only access to this divider. Not an…
29489 … (0xf<<4) // Static divider control for SOC1 The only access to this divider. Not an…
29492 …7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Ov…
29496 … (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divider. Not an…
29501 … (0x7<<0) // Static divider control for the SSC block The only access to this divider. Not an…
29503 …<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
29505 … (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by…
29508 …HB_PMA_CM_DIVNSEL_6_0_O_K2_E5 (0x7f<<0) // CMU N-divider setting
29520 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29521 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29522 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29524 … the following functions: [27] - active high, Override Enable [26] - GCFSM Request flag [25:24] -…
29526 … 0x000028UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
29527 … 0x00002cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
29528 … 0x000030UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
29529 … 0x000034UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
29530 … 0x000038UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
29531 … 0x00003cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
29532 … 0x000040UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
29533 … 0x000044UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
29534 … 0x000048UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
29535 … 0x00004cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
29536 … 0x000050UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
29537 … 0x000054UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
29538 … 0x000058UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
29539 … 0x00005cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
29540 … 0x000060UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
29541 … 0x000064UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
29559 …errides for the following functions: [0] - active high, Override Enable [1] - SOC…
29561 …errides for the following functions: [0] - active high, Override Enable [1] - REF…
29563 …errides for the following functions: [0] - active high, Override Enable [1] - LOC…
29565 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29568 …lowing functions: [0] - active high, Override Enable [1] - SOC clock output enabl…
29570 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29572 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29574 …errides for the following functions: [0] - active high, Override Enable [1] - IDD…
29577 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29579 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29581 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29583 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29586 …errides for the following functions: [0] - active high, Override Enable [1] - PCS…
29588 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29590 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29592 …errides for the following functions: [0] - active high, Override Enable [1] - LF …
29595 …errides for the following functions: [0] - active high, Override Enable [1] - LFI…
29597 …errides for the following functions: [0] - active high, Override Enable [1] - PD …
29599 …errides for the following functions: [0] - active high, Override Enable [1] - RES…
29640 …0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag ov…
29642 …00174UL //Access:RW DataWidth:0x8 // Number of reference clock cycles to count after qsample …
29644 … (0x3<<0) // Number of reference clock cycles to count after qsample …
29646 …5 (0x1<<2) // State of qsample for PLL to be considered locked
29648 …PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycl…
29653 …CE_ILF_O_K2_E5 (0x3<<2) // CMU loop filter force to common mode
29678 …B_PMA_CM_PFD_FORCE_DN_O_K2_E5 (0x1<<0) // Force PFD to output down
29680 …AHB_PMA_CM_PFD_FORCE_UP_O_K2_E5 (0x1<<1) // Force PFD to output up
29682 …_E5 (0x1<<2) // Override enable for overriding N-div value
29696 …CM_I_DROPI_O_K2_E5 (0x1<<2) // Enable to reduce charge pump r…
29701 …_AHB_PMA_CM_DIVPSEL_O_K2_E5 (0x7f<<0) // CMU P-divider setting
29737 …sents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not ac…
29738 …sents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not ac…
29740 …sents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not ac…
29746 … // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down…
29753 … (0x3<<4) // Test i/p control source : 0-modulator 1-bypass modulator 2-modulator …
29755 … (0x1<<6) // Clock Select for High Speed clock source : 0-clk_hs_fbk 1-clk_hs_refout
29766 …P_CAL_OVR_EN_O_K2_E5 (0x1<<7) // override enable to use above value
29768 … 0x0001e0UL //Access:RW DataWidth:0x8 // Divider input for Div-by-N counter
29770 …_CAL_CLK_DIV_O_14_8_K2_E5 (0x7f<<0) // Divider input for Div-by-N counter
29782 …s:RW DataWidth:0x8 // In txterm calibration, the number refclk cycles to wait before sampling…
29784 … (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling…
29786 … (0x7<<1) // in txterm calibration, the number refclk cycles to wait before sampling…
29788 … (0xf<<4) // in txterm calibration, the number of samples to take from the same c…
29791 …set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to…
29802 …erride for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pi…
29810 … 0x000210UL //Access:RW DataWidth:0x8 // CMU Test Bus address 7-0
29812 …US_ADDR_OVR_O_10_8_K2_E5 (0x7<<0) // CMU Test Bus address 10-8
29818 …// Static divider control for CMU GCFSM clock in gen3 rate The only access to this divider. Not an…
29820 … // Static divider control for the SSC clock in gen3 rate. The only access to this divider. Not an…
29857 …PFD_FORCE_DN_GEN3_O_K2_E5 (0x1<<0) // Force PFD to output down in gen3 …
29859 …PFD_FORCE_UP_GEN3_O_K2_E5 (0x1<<1) // Force PFD to output up in gen3 ra…
29873 …CM_I_DROPI_GEN3_O_K2_E5 (0x1<<2) // Enable to reduce charge pump r…
29878 …A_CM_DIVPSEL_GEN3_O_K2_E5 (0x7f<<0) // CMU P-divider setting in ge…
29904 … 0x000264UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29905 … 0x000268UL //Access:RW DataWidth:0x8 // Inverts up_i when set to 1
29906 …Varies depending on function number. _13:06 - Address of first command to run _05:00 - Number of c…
30245 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
30248 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
30250 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
30253 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
30256 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
30258 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
30261 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
30263 … (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an…
30270 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divid…
30272 … (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1-…
30277 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
30279 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
30285 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
30287 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
30292 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
30294 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
30296 … 0x000824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30297 … 0x000828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
30298 …0x00082cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer to bist_gen…
30299 …0x000830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer to bist_gen…
30300 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
30302 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
30309 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
30317 …. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This …
30319 …. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This …
30323 … (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
30329 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
30330 … 0x000854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30331 … 0x000858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30332 … 0x00085cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30333 … 0x000860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
30341 … 0x000880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
30342 … 0x000884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
30343 … 0x000888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
30344 … 0x00088cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
30345 … 0x000890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
30346 … 0x000894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
30347 … 0x000898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
30348 … 0x00089cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
30349 … 0x0008a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
30350 … 0x0008a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
30351 … 0x0008a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
30352 … 0x0008acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
30353 … 0x0008b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
30354 … 0x0008b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
30355 … 0x0008b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
30356 … 0x0008bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
30357 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
30358 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
30359 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
30360 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
30365 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
30367 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
30369 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
30377 …e State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data…
30385 …UL //Access:RW DataWidth:0x8 // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
30387 … (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
30389 …ertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA c…
30390 …ertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA c…
30399 …mber of cycles of low signal detect output required for RX electrical idle to be declared. Clock c…
30403 …mber of cycles of low signal detect output required for RX electrical idle to be declared. Clock c…
30421 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
30423 …ed, without CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration …
30425 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
30429 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30430 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30431 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30433 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
30435 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
30445 … 0x000940UL //Access:RW DataWidth:0x8 // Number of cycles to wait before forcing …
30447 …_TIMER_LEN_O_9_8_K2_E5 (0x3<<0) // Number of cycles to wait before forcing …
30459 … 0x000948UL //Access:RW DataWidth:0x8 // Number of cycles to wait before entering…
30463 …_TIMER_LEN_O_9_8_K2_E5 (0x3<<0) // Number of cycles to wait before entering…
30467 …_E5 (0x1<<4) // Control signal to force decoder into l…
30474 … (0x1<<2) // HS recovered clock to transmit loopback en…
30485 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
30487 …0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor m…
30492 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
30519 …(0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor m…
30536 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
30538 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
30554 … (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative pol…
30577 …0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor m…
30602 …(0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor m…
30615 …_CXP_MARGIN_K2_E5 (0xf<<0) // Value to minus/add from the c…
30617 …_CXN_MARGIN_K2_E5 (0xf<<4) // Value to minus/add from the c…
30620 … (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling…
30622 … (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling…
30625 … (0xf<<0) // in txterm calibration, the number of samples to take from the same c…
30627 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
30629 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
30633 … (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_t…
30646 … 0x0009f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
30714 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
30716 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
30730 …AMPLES_6_0_K2_E5 (0x7f<<0) // Max number of samples to be used for CMP Offs…
30742 … (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
30752 … (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE …
30757 … (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain…
30759 … (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_au…
30794 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
30800 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
30802 … 0x000a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
30804 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
30806 … 0x000a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
30824 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
30832 …set to 0 8-bit or 10-bit mode. 2'b11: the wo…
30834 …et to 0 10-bit or 20-bit mode. 2'b11: the mod…
30836 … 3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
30861 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
30869 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
30872 …to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 b…
30875 …to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 b…
30970 … (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
30972 … (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
30974 … (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
30978 … (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
30984 … offset from the midpoint code 127/128 that must be met for the comparator to be selected as adapt…
31019 …ADAPT_USING_DLEV_GO_O_K2_E5 (0x1<<0) // Instucts to start TAP adapt usin…
31038 …_PATT_O_K2_E5 (0x1<<5) // Forces the positive dlev training pattern to be used
31040 …_PATT_O_K2_E5 (0x1<<6) // Forces the negative dlev training pattern to be used
31139 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
31141 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31143 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31145 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31149 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
31152 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31154 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31156 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31158 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
31160 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31162 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31167 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
31169 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
31182 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit st…
31187 …<0) // An internal FIFO is included to handle the communication between the external 64-bit data a…
31189 … (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to…
31191 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
31198 …ation calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
31200 …to the per lane transmit byte clock from PMA or its divided down version and this clock can be use…
31203 …per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmi…
31244 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
31246 … (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to ge…
31248 … (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read poi…
31256 … (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_l…
31258 …SKIP_CDR_GEN3_O_K2_E5 (0x1<<1) // To skip cdr calibration…
31260 …SKIP_CDR_GEN12_O_K2_E5 (0x1<<2) // To skip cdr calibration…
31266 … 0x000cecUL //Access:RW DataWidth:0x8 // Delays the beacon_ena propagation to PMA
31268 …ED_COUNT_NUMBER_11_8_O_K2_E5 (0xf<<0) // Delays the beacon_ena propagation to PMA
31289 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
31291 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
31295 …NA_O_K2_E5 (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
31297 …O_K2_E5 (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
31308 …to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1'…
31317 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
31325 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
31328 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
31330 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
31333 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
31336 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
31338 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
31341 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
31343 … (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an…
31350 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divid…
31352 … (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1-…
31357 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
31359 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
31365 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
31367 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
31372 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
31374 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
31376 … 0x001024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31377 … 0x001028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
31378 …0x00102cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer to bist_gen…
31379 …0x001030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer to bist_gen…
31380 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
31382 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
31389 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
31397 …. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This …
31399 …. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This …
31403 … (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
31409 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
31410 … 0x001054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31411 … 0x001058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31412 … 0x00105cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31413 … 0x001060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
31421 … 0x001080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
31422 … 0x001084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
31423 … 0x001088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
31424 … 0x00108cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
31425 … 0x001090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
31426 … 0x001094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
31427 … 0x001098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
31428 … 0x00109cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
31429 … 0x0010a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
31430 … 0x0010a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
31431 … 0x0010a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
31432 … 0x0010acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
31433 … 0x0010b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
31434 … 0x0010b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
31435 … 0x0010b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
31436 … 0x0010bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
31437 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
31438 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
31439 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
31440 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
31445 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
31447 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
31449 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
31457 …e State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data…
31465 …UL //Access:RW DataWidth:0x8 // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
31467 … (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
31469 …ertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA c…
31470 …ertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA c…
31479 …mber of cycles of low signal detect output required for RX electrical idle to be declared. Clock c…
31483 …mber of cycles of low signal detect output required for RX electrical idle to be declared. Clock c…
31501 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
31503 …ed, without CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration …
31505 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
31509 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31510 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31511 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31513 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
31515 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
31525 … 0x001140UL //Access:RW DataWidth:0x8 // Number of cycles to wait before forcing …
31527 …_TIMER_LEN_O_9_8_K2_E5 (0x3<<0) // Number of cycles to wait before forcing …
31539 … 0x001148UL //Access:RW DataWidth:0x8 // Number of cycles to wait before entering…
31543 …_TIMER_LEN_O_9_8_K2_E5 (0x3<<0) // Number of cycles to wait before entering…
31547 …_E5 (0x1<<4) // Control signal to force decoder into l…
31554 … (0x1<<2) // HS recovered clock to transmit loopback en…
31565 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
31567 …0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor m…
31572 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
31599 …(0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor m…
31616 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
31618 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
31634 … (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative pol…
31657 …0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor m…
31682 …(0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor m…
31695 …_CXP_MARGIN_K2_E5 (0xf<<0) // Value to minus/add from the c…
31697 …_CXN_MARGIN_K2_E5 (0xf<<4) // Value to minus/add from the c…
31700 … (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling…
31702 … (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling…
31705 … (0xf<<0) // in txterm calibration, the number of samples to take from the same c…
31707 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
31709 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
31713 … (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_t…
31726 … 0x0011f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
31794 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
31796 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
31810 …AMPLES_6_0_K2_E5 (0x7f<<0) // Max number of samples to be used for CMP Offs…
31822 … (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
31832 … (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE …
31837 … (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain…
31839 … (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_au…
31874 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
31880 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
31882 … 0x001280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
31884 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
31886 … 0x001288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
31904 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
31912 …set to 0 8-bit or 10-bit mode. 2'b11: the wo…
31914 …et to 0 10-bit or 20-bit mode. 2'b11: the mod…
31916 … 3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
31941 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
31949 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
31952 …to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 b…
31955 …to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 b…
32050 … (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
32052 … (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
32054 … (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
32058 … (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
32064 … offset from the midpoint code 127/128 that must be met for the comparator to be selected as adapt…
32099 …ADAPT_USING_DLEV_GO_O_K2_E5 (0x1<<0) // Instucts to start TAP adapt usin…
32118 …_PATT_O_K2_E5 (0x1<<5) // Forces the positive dlev training pattern to be used
32120 …_PATT_O_K2_E5 (0x1<<6) // Forces the negative dlev training pattern to be used
32219 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
32221 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32223 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32225 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32229 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
32232 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32234 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32236 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32238 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
32240 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32242 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32247 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
32249 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
32262 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit st…
32267 …<0) // An internal FIFO is included to handle the communication between the external 64-bit data a…
32269 … (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to…
32271 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
32278 …ation calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
32280 …to the per lane transmit byte clock from PMA or its divided down version and this clock can be use…
32283 …per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmi…
32324 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
32326 … (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to ge…
32328 … (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read poi…
32336 … (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_l…
32338 …SKIP_CDR_GEN3_O_K2_E5 (0x1<<1) // To skip cdr calibration…
32340 …SKIP_CDR_GEN12_O_K2_E5 (0x1<<2) // To skip cdr calibration…
32346 … 0x0014ecUL //Access:RW DataWidth:0x8 // Delays the beacon_ena propagation to PMA
32348 …ED_COUNT_NUMBER_11_8_O_K2_E5 (0xf<<0) // Delays the beacon_ena propagation to PMA
32369 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
32371 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
32375 …NA_O_K2_E5 (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
32377 …O_K2_E5 (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
32388 …to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1'…
32397 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
32405 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
32408 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
32410 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
32413 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
32416 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
32418 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
32421 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
32423 … (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an…
32430 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divid…
32432 … (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1-…
32437 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
32439 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
32445 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
32447 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
32452 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
32454 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
32456 … 0x001824UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32457 … 0x001828UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
32458 …0x00182cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer to bist_gen…
32459 …0x001830UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer to bist_gen…
32460 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
32462 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
32469 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
32477 …. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This …
32479 …. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This …
32483 … (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
32489 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
32490 … 0x001854UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32491 … 0x001858UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32492 … 0x00185cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32493 … 0x001860UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
32501 … 0x001880UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
32502 … 0x001884UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
32503 … 0x001888UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
32504 … 0x00188cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
32505 … 0x001890UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
32506 … 0x001894UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
32507 … 0x001898UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
32508 … 0x00189cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
32509 … 0x0018a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
32510 … 0x0018a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
32511 … 0x0018a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
32512 … 0x0018acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
32513 … 0x0018b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
32514 … 0x0018b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
32515 … 0x0018b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
32516 … 0x0018bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
32517 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
32518 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
32519 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
32520 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
32525 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
32527 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
32529 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
32537 …e State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data…
32545 …UL //Access:RW DataWidth:0x8 // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
32547 … (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
32549 …ertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA c…
32550 …ertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA c…
32559 …mber of cycles of low signal detect output required for RX electrical idle to be declared. Clock c…
32563 …mber of cycles of low signal detect output required for RX electrical idle to be declared. Clock c…
32581 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
32583 …ed, without CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration …
32585 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
32589 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32590 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32591 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32593 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
32595 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
32605 … 0x001940UL //Access:RW DataWidth:0x8 // Number of cycles to wait before forcing …
32607 …_TIMER_LEN_O_9_8_K2_E5 (0x3<<0) // Number of cycles to wait before forcing …
32619 … 0x001948UL //Access:RW DataWidth:0x8 // Number of cycles to wait before entering…
32623 …_TIMER_LEN_O_9_8_K2_E5 (0x3<<0) // Number of cycles to wait before entering…
32627 …_E5 (0x1<<4) // Control signal to force decoder into l…
32634 … (0x1<<2) // HS recovered clock to transmit loopback en…
32645 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
32647 …0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor m…
32652 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
32679 …(0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor m…
32696 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
32698 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
32714 … (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative pol…
32737 …0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor m…
32762 …(0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor m…
32775 …_CXP_MARGIN_K2_E5 (0xf<<0) // Value to minus/add from the c…
32777 …_CXN_MARGIN_K2_E5 (0xf<<4) // Value to minus/add from the c…
32780 … (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling…
32782 … (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling…
32785 … (0xf<<0) // in txterm calibration, the number of samples to take from the same c…
32787 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
32789 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
32793 … (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_t…
32806 … 0x0019f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
32874 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
32876 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
32890 …AMPLES_6_0_K2_E5 (0x7f<<0) // Max number of samples to be used for CMP Offs…
32902 … (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
32912 … (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE …
32917 … (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain…
32919 … (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_au…
32954 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
32960 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
32962 … 0x001a80UL //Access:R DataWidth:0x8 // Over equalization count 7-0
32964 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
32966 … 0x001a88UL //Access:R DataWidth:0x8 // Under equalization count 7-0
32984 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
32992 …set to 0 8-bit or 10-bit mode. 2'b11: the wo…
32994 …et to 0 10-bit or 20-bit mode. 2'b11: the mod…
32996 … 3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
33021 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
33029 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
33032 …to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 b…
33035 …to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 b…
33130 … (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
33132 … (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
33134 … (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
33138 … (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
33144 … offset from the midpoint code 127/128 that must be met for the comparator to be selected as adapt…
33179 …ADAPT_USING_DLEV_GO_O_K2_E5 (0x1<<0) // Instucts to start TAP adapt usin…
33198 …_PATT_O_K2_E5 (0x1<<5) // Forces the positive dlev training pattern to be used
33200 …_PATT_O_K2_E5 (0x1<<6) // Forces the negative dlev training pattern to be used
33299 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
33301 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33303 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33305 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33309 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
33312 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33314 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33316 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33318 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
33320 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33322 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33327 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
33329 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
33342 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit st…
33347 …<0) // An internal FIFO is included to handle the communication between the external 64-bit data a…
33349 … (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to…
33351 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
33358 …ation calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
33360 …to the per lane transmit byte clock from PMA or its divided down version and this clock can be use…
33363 …per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmi…
33404 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
33406 … (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to ge…
33408 … (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read poi…
33416 … (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_l…
33418 …SKIP_CDR_GEN3_O_K2_E5 (0x1<<1) // To skip cdr calibration…
33420 …SKIP_CDR_GEN12_O_K2_E5 (0x1<<2) // To skip cdr calibration…
33426 … 0x001cecUL //Access:RW DataWidth:0x8 // Delays the beacon_ena propagation to PMA
33428 …ED_COUNT_NUMBER_11_8_O_K2_E5 (0xf<<0) // Delays the beacon_ena propagation to PMA
33449 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
33451 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
33455 …NA_O_K2_E5 (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
33457 …O_K2_E5 (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
33468 …to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1'…
33477 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
33485 … (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
33488 … (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
33490 … (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
33493 … (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
33496 … (0x1<<0) // CMU Select for lane 0 - Select CMU0 1 - Select CMU1
33498 … (0x1<<1) // PMA TX Clock Select for TX CDR VCO 0 - CMU0 Clock 1 - CMU1 Clock
33501 …_K2_E5 (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Div…
33503 … (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an…
33510 … (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divid…
33512 … (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1-…
33517 … (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Gen…
33519 … (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 -…
33525 … (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 …
33527 … (0x1<<7) // Bist generator enable. 0 - Bist generator idle. 1 - Bist gen…
33532 …erator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - B…
33534 …// Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is e…
33536 … 0x002024UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33537 … 0x002028UL //Access:RW DataWidth:0x8 // Bist generator low-period control. If no…
33538 …0x00202cUL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer to bist_gen…
33539 …0x002030UL //Access:RW DataWidth:0x8 // Bist generator high-period control. Refer to bist_gen…
33540 … // Bist generator - Number of words between insert word insertions. Insertions are done in both …
33542 …) // Bist generator - Number of words between insert word insertions. Insertions are done in both …
33549 …- BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Align…
33557 …. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This …
33559 …. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This …
33563 … (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
33569 …-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corr…
33570 … 0x002054UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33571 … 0x002058UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33572 … 0x00205cUL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33573 … 0x002060UL //Access:RW DataWidth:0x8 // BIST Check User-defined pattern
33581 … 0x002080UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
33582 … 0x002084UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
33583 … 0x002088UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
33584 … 0x00208cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
33585 … 0x002090UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
33586 … 0x002094UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
33587 … 0x002098UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
33588 … 0x00209cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
33589 … 0x0020a0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
33590 … 0x0020a4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
33591 … 0x0020a8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
33592 … 0x0020acUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
33593 … 0x0020b0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
33594 … 0x0020b4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
33595 … 0x0020b8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
33596 … 0x0020bcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
33597 …/Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 1/2 - for the new ICA meth…
33598 … //Access:RW DataWidth:0x8 // Timing Window length for GCFSM for Gen 3 - for the new ICA meth…
33599 …cess:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA meth…
33600 …Access:RW DataWidth:0x8 // Timing Window length for cdr_ctrl for Gen 3 - for the new ICA meth…
33605 …LANE or LANE CSR Select for GCFSM Cycle Length registers 0 - Select COMLANE registers 1 - Sele…
33607 …5 (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
33609 …K2_E5 (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
33617 …e State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data…
33625 …UL //Access:RW DataWidth:0x8 // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
33627 … (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
33629 …ertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA c…
33630 …ertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA c…
33639 …mber of cycles of low signal detect output required for RX electrical idle to be declared. Clock c…
33643 …mber of cycles of low signal detect output required for RX electrical idle to be declared. Clock c…
33661 … (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
33663 …ed, without CISEL being asserted to the CDR. 0 - CDR control block will wait for ATT calibration …
33665 … // CDR control block wait for DFE signal. 0 - Do not wait for DFE calibration before enabling rx…
33669 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33670 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33671 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33673 …- Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlp…
33675 … (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
33685 … 0x002140UL //Access:RW DataWidth:0x8 // Number of cycles to wait before forcing …
33687 …_TIMER_LEN_O_9_8_K2_E5 (0x3<<0) // Number of cycles to wait before forcing …
33699 … 0x002148UL //Access:RW DataWidth:0x8 // Number of cycles to wait before entering…
33703 …_TIMER_LEN_O_9_8_K2_E5 (0x3<<0) // Number of cycles to wait before entering…
33707 …_E5 (0x1<<4) // Control signal to force decoder into l…
33714 … (0x1<<2) // HS recovered clock to transmit loopback en…
33725 …O_K2_E5 (0x7<<3) // Signal detect threshold select for div-by-2 rate
33727 …0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor m…
33732 …O_K2_E5 (0x7<<0) // Signal detect threshold select for div-by-4 rate
33759 …(0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor m…
33776 …-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, i…
33778 …) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps…
33794 … (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative pol…
33817 …0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor m…
33842 …(0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor m…
33855 …_CXP_MARGIN_K2_E5 (0xf<<0) // Value to minus/add from the c…
33857 …_CXN_MARGIN_K2_E5 (0xf<<4) // Value to minus/add from the c…
33860 … (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling…
33862 … (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling…
33865 … (0xf<<0) // in txterm calibration, the number of samples to take from the same c…
33867 …m value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
33869 …m value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
33873 … (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_t…
33886 … 0x0021f4UL //Access:RW DataWidth:0x8 // Bits 19-16: txdrv_cm_in[3:0] Bits 22-20: tx…
33954 …K2_E5 (0xf<<1) // Max limit value for BOOST auto-calibration
33956 …2_E5 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
33970 …AMPLES_6_0_K2_E5 (0x7f<<0) // Max number of samples to be used for CMP Offs…
33982 … (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
33992 … (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE …
33997 … (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain…
33999 … (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_au…
34034 … (0x1<<2) // TX Equalization Firmware over ride 0 - Disable firmware based adaptation 1 - …
34040 …Q_OVER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Over equalization count 9-8
34042 … 0x002280UL //Access:R DataWidth:0x8 // Over equalization count 7-0
34044 …_UNDER_EQ_CNT_I_9_8_K2_E5 (0x3<<0) // Under equalization count 9-8
34046 … 0x002288UL //Access:R DataWidth:0x8 // Under equalization count 7-0
34064 …EQ_RXRECAL_DONE_I_0_K2_E5 (0x1<<0) // TX - RECAL RX Equalizatio…
34072 …set to 0 8-bit or 10-bit mode. 2'b11: the wo…
34074 …et to 0 10-bit or 20-bit mode. 2'b11: the mod…
34076 … 3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
34101 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate3 …
34109 …Access:RW DataWidth:0x8 // Enables for various cdfe component during re-calibration in rate2 …
34112 …to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 b…
34115 …to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 b…
34210 … (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
34212 … (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
34214 … (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
34218 … (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
34224 … offset from the midpoint code 127/128 that must be met for the comparator to be selected as adapt…
34259 …ADAPT_USING_DLEV_GO_O_K2_E5 (0x1<<0) // Instucts to start TAP adapt usin…
34278 …_PATT_O_K2_E5 (0x1<<5) // Forces the positive dlev training pattern to be used
34280 …_PATT_O_K2_E5 (0x1<<6) // Forces the negative dlev training pattern to be used
34379 … (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 -…
34381 … (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34383 … (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34385 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34389 …0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / unde…
34392 … (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34394 … (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34396 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34398 … (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data pol…
34400 … (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34402 …Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34407 … (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. …
34409 …Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped…
34422 … (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2�b00: no bit st…
34427 …<0) // An internal FIFO is included to handle the communication between the external 64-bit data a…
34429 … (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to…
34431 … // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data wor…
34438 …ation calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
34440 …to the per lane transmit byte clock from PMA or its divided down version and this clock can be use…
34443 …per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmi…
34484 …IMIT_EN_O_K2_E5 (0x1<<0) // FE TxEq Co-efficient Limiting En…
34486 … (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to ge…
34488 … (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read poi…
34496 … (0x1<<0) // Mux select for data input to polbit_reg0 0:pma_l…
34498 …SKIP_CDR_GEN3_O_K2_E5 (0x1<<1) // To skip cdr calibration…
34500 …SKIP_CDR_GEN12_O_K2_E5 (0x1<<2) // To skip cdr calibration…
34506 … 0x0024ecUL //Access:RW DataWidth:0x8 // Delays the beacon_ena propagation to PMA
34508 …ED_COUNT_NUMBER_11_8_O_K2_E5 (0xf<<0) // Delays the beacon_ena propagation to PMA
34529 … (0x3<<0) // Override signal for txdetectrx input - bit 1 is override en…
34531 … (0x3<<2) // Override signal for txdetectrx output - bit 1 is override en…
34535 …NA_O_K2_E5 (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
34537 …O_K2_E5 (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
34548 …to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1'…
34557 …y between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0 R-platform requires 150…
34565 … (0x1<<0) // Lane Reference Clock Enable. 0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - …
34568 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34570 …ta pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 � Not in…
34621 … 0x002880UL //Access:RW DataWidth:0x8 // SKP symbol for PCIe Gen3 SKP OS ---8'hAA
34631 … 0x002898UL //Access:RW DataWidth:0x8 // 10-bit align symbol for …
34633 …_S0_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for …
34635 … 0x0028a0UL //Access:RW DataWidth:0x8 // 10-bit align symbol for …
34637 …_S1_LB_P_O_9_8_K2_E5 (0x3<<0) // 10-bit align symbol for …
34700 … (0x3<<0) // Static divider control for Lane GCFSM clock The only access to this divider. Not an…
34702 … 0x0028e0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 7-0
34703 … 0x0028e4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 15-8
34704 … 0x0028e8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 23-16
34705 … 0x0028ecUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 31-24
34706 … 0x0028f0UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 39-32
34707 … 0x0028f4UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 47-40
34708 … 0x0028f8UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 55-48
34709 … 0x0028fcUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 63-56
34710 … 0x002900UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 71-64
34711 … 0x002904UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 79-72
34712 … 0x002908UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 87-80
34713 … 0x00290cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 95-88
34714 … 0x002910UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 103-96
34715 … 0x002914UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 111-104
34716 … 0x002918UL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 119-112
34717 … 0x00291cUL //Access:RW DataWidth:0x8 // GCFSM Cycle Length Input bits 127-120
34720 …es depending on function number. Bits 15-7: Address of first command to run Bits: 6-0: Number of…
34789 …or MFSM state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity …
34790 …or MFSM state transition from P2 to P1 in non-PIPE mode. The MFSM waits for the analog cuircuity …
35203 …E1_TX_SLEW_SLD3F_2_0_K2_E5 (0x7<<2) // TX enable fastest slew rate set to 1.
35205 …E2_TX_SLEW_SLD3F_2_0_K2_E5 (0x7<<5) // TX enable fastest slew rate set to 1.
35208 …E3_TX_SLEW_SLD3F_2_0_K2_E5 (0x7<<0) // TX enable fastest slew rate set to 1.
35260 …O_K2_E5 (0x1<<6) // Brings the TxEq pre-cursor down to a programmabl…
35262 …_K2_E5 (0x1<<7) // Brings the TxEq pre-cursor down to a programmabl…
35276 …5 (0xf<<0) // Number of wait cycles for the CDR to lock [3:0] times 64
35278 …epeat of calibration for rate switch or electrical idle exit. Calibrations to be performed are sel…
35280 … (0x1<<6) // Set all DFE calibration values to mid-scale instead of u…
35282 … 0x002b5cUL //Access:RW DataWidth:0x8 // DFE block -continuous calibratio…
35284 …NT_LENGTH_O_14_8_K2_E5 (0x7f<<0) // DFE block -continuous calibratio…
35286 … 0x002b64UL //Access:RW DataWidth:0x8 // DFE block - ATT calibration cycl…
35287 … 0x002b68UL //Access:RW DataWidth:0x8 // DFE block - Boost calibration cy…
35288 … 0x002b6cUL //Access:RW DataWidth:0x8 // DFE block - TAP1 calibration cyc…
35289 … 0x002b70UL //Access:RW DataWidth:0x8 // DFE block - TAP2 calibration cyc…
35290 … 0x002b74UL //Access:RW DataWidth:0x8 // DFE block - TAP3 calibration cyc…
35291 … 0x002b78UL //Access:RW DataWidth:0x8 // DFE block - TAP4 calibration cyc…
35292 … 0x002b7cUL //Access:RW DataWidth:0x8 // DFE block - TAP5 calibration cyc…
35296 …CAL_O_6_0_K2_E5 (0x7f<<1) // Enables re-calibration for { Tap…
35305 …TE2_RECAL_O_6_0_K2_E5 (0x7f<<0) // Enables re-calibration for { Tap…
35336 …estbus select for comp_offset and tap_offset 1: Raw output from i_dfe_tap_dc_offset 0: Input to pma
35464 …E_I_3_0_K2_E5 (0xf<<0) // RXEQ calibration done status - per lane
35466 …DAPT_DONE_I_3_0_K2_E5 (0xf<<4) // TXEQ Adapt Done status - per lane
35475 …2_E5 (0x1f<<0) // Bit 4 - latency check control enable Bit 3:0 - l…
35968 … // Controls the number of clk cycles delay from data_en of p2s_rbuf to propagate to the idle_in o…
35973 …_I_2_0_K2_E5 (0x7<<0) // 1000Base-KX Mode status for CPU
36036 …X414_TXPRESET_COEFF_P0CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P0 C-1
36045 …X417_TXPRESET_COEFF_P1CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P1 C-1
36054 …X420_TXPRESET_COEFF_P2CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P2 C-1
36063 …X423_TXPRESET_COEFF_P3CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P3 C-1
36072 …X426_TXPRESET_COEFF_P4CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P4 C-1
36081 …X429_TXPRESET_COEFF_P5CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P5 C-1
36090 …X432_TXPRESET_COEFF_P6CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P6 C-1
36099 …X435_TXPRESET_COEFF_P7CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P7 C-1
36108 …X438_TXPRESET_COEFF_P8CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P8 C-1
36117 …X441_TXPRESET_COEFF_P9CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P9 C-1
36126 …444_TXPRESET_COEFF_P10CM1_O_K2_E5 (0x3f<<0) // txpreset_coeff P10 C-1
36355 …- no auto deassertion; 1 - auto deassertion); [1] rst_pswrd_auto_mode (0- no auto deassertion; 1 -…
36356 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36358 …-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific bloc…
36360 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36362 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36364 …-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers…
36366 …-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out…
36369 … (0x1<<0) // Signals an unknown address to the rf module.
36375 … (0x1<<0) // Signals an unknown address to the rf module.
36378 … (0x1<<0) // Signals an unknown address to the rf module.
36422 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36424 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36426 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36431 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36433 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36435 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36440 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36442 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36444 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36449 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36451 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36453 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36458 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36460 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36462 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36467 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36469 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36471 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36476 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36478 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36480 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36485 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36487 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36489 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36494 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36496 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36498 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36503 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36505 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36507 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36512 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36514 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36516 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36521 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36523 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36525 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36530 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36532 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36534 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36539 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36541 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36543 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36548 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36550 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36552 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36557 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36559 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36561 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36566 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36568 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36570 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36575 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36577 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36579 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36584 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36586 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36588 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36593 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36595 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36597 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36602 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36604 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36606 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36611 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36613 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36615 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36620 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36622 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36624 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36629 …MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path…
36631 … [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [25-24] Rsvd; [26] DORQ P…
36633 …] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL P…
36636 …0x008800UL //Access:RW DataWidth:0x1 // The System Kill enable: 0 - none; 1 - hard reset. Res…
36637 …to the AEU when a system kill occurred. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GP…
36638 …to the AEU when a system kill occurred. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_…
36639 …to the AEU when a system kill occurred. Mapped as follows: [0] General attn0; [1] General attn1; […
36640 …to the AEU when a system kill occurred. Mapped as follows: [0] General attn32; [1] General attn33;…
36641 …to the AEU when a system kill occurred. Mapped as follows: [0] SRC Parity error; [1] SRC HW interr…
36642 …to the AEU when a system kill occurred. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interr…
36643 …to the AEU when a system kill occurred. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw inte…
36644 …to the AEU when a system kill occurred. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] P…
36645 …to the AEU when a system kill occurred. Mapped as follows: [0] MCP Latched memory parity; [1] MCP …
36655 …to this register results with the clear of the latched signals; [0] one clears Latched MCP memory …
36657 …aWidth:0x10 // Write to this register results with the clear of the latched signals; [0] - clear…
36659 …- latches first attention number within attentions vector. The number is produced as the index of …
36660 … 0x008c00UL //Access:RW DataWidth:0x2 // Port mode. 0 - single port; 1 - 2 ports; 2 - 4 por…
36661 … Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 1x …
36662 …to phy_port_mode; if some of the ports are not used. This enables reduction of frequency on the co…
36663 …- disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port. Port…
36664 …IFOs should be bypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 - BRB…
36665 …rammed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and…
36667 …- Storms stall is disallowed; AEU unifier bit[7] output to MCP is disabled; 1 - All Storms are for…
36668 …c20UL //Access:RW DataWidth:0x17 // 23 bit GRC address where the scratch-pad of the MCP that i…
36669 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36670 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36671 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36672 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36673 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36674 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36675 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36676 …-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER…
36685 …8 // Write one for the appropriate bit will clear the appropriate event to the AEU (if the attn…
36686 …008c68UL //Access:R DataWidth:0x8 // The appropriate timer had reach to zero. [0] timer1; [1…
36701 …he counter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address …
36703 …- no auto deassertion; 1 - auto deassertion); [1] rst_umac_on_core_rst (0- no auto deassertion; 1 …
36704 …- is not reset on hard reset; 1 - is reset on hard reset); [1] rst_n_hard_misc_rbc_pcie (0 - is no…
36705 …-ignore; The order of the bits is: [0] rst_cgrc; [1] rst_mcp_n_reset_reg_hard_core; [2] rst_mcp_n_…
36707 …reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of …
36709 …quency (when programmed to 1) or is the same as main clock frequency (when programmed to 0). In E4…
36710 …ock size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it…
36711 …- source of privilege level, 0 - the source is external pin, 1 - the source are bits[2:1] of this …
36712 … // Privilege level as defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - full…
36713 …-disable to the NVM block is generated. '0' - PROTECT: This value protects the NVM from any writes…
36714 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36716 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36718 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36720 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36722 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36724 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36726 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36728 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36730 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36732 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36734 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36736 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36738 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36740 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36742 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36744 …-path clients and 32 resources. Each resource can be controlled by one client only. One in each bi…
36746 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
36748 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
36750 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
36752 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
36754 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
36756 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
36758 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
36760 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
36762 …reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of …
36764 … 0x009160UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
36765 … 0x009164UL //Access:RW DataWidth:0x8 // command to CPU BIST
36766 … 0x009168UL //Access:RW DataWidth:0x8 // address to CPU BIST
36770 … (0x1<<0) // Signals an unknown address to the rf module.
36772 … (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
36784 … (0x1<<0) // Signals an unknown address to the rf module.
36786 … (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
36791 … (0x1<<0) // Signals an unknown address to the rf module.
36793 … (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
36892 …state of the ptw_miscs_pcie_link_up signal which is driven by the PCIE core - a pulse at the begin…
36893 …ate of the ptw_miscs_pcie_hot_reset signal which is driven by the PCIE core - a pulse at the begin…
36895 … DataWidth:0x10 // Accounts for HOT RESET assertion when the chip is in un-prepared state. Is re…
36897 …s:RW DataWidth:0x1 // Set to 1 when main PLL lock indication is de-asserted when hard reset i…
36898 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36899 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36900 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36901 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36902 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36903 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36904 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36905 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36906 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36907 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36908 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36909 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36910 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36911 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36912 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36913 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36914 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36915 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36916 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36917 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36918 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36919 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36920 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36921 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36922 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36923 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36924 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36925 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36926 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36927 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36928 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36929 …- GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO …
36996 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
36997 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
36998 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
36999 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37000 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37001 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37002 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37003 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37004 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37005 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37006 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37007 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37008 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37009 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37010 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37011 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37012 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37013 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37014 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37015 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37016 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37017 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37018 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37019 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37020 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37021 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37022 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37023 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37024 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37025 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37026 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37027 …to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an inte…
37028 … //Access:RW DataWidth:0x20 // These bits enable the GPIO_INTs to signals event to the IGU/MCP…
37029 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
37031 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
37033 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
37035 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
37037 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
37039 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
37041 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
37043 …to address 1 will set a "request" to control all the resources which appropriate bit (in the write…
37045 …A interface to BSC_SDA0 IO. 01: connect SDA interface to BSC_SDA1 IO. 10: connect SDA interface to…
37046 …-assertion. If == 1, triggers chip core reset. If == 0, doesn't trigger chip core reset. Bit[1]: P…
37047 …to 1 to enable use of NIC magic packet detection to assert WAKE OOB. Reset on POR reset and PERST#…
37048 … 0, indicated PCIE EP controller is in reset, except for PMC module. Refer to PCIE EP controller d…
37049 …cess:RW DataWidth:0x1 // When 0, indicated PCIE PHY is in reset Refer to PCIE PHY user manual.
37050 …0x0096b8UL //Access:R DataWidth:0x1 // Chip core_rst_n status. 0 - asserted; 1 - de-asserted.
37051 …to 1. Bit 0 : LINK_HOLDOFF_SUCCESS When =1, indicates the PCIE link is successfully being held fr…
37052 …to a '1' to request that the PCIE link not begin training yet. Software should set this bit; and t…
37059 …to 1 will allow SW/FW to use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO c…
37060 …ly: spare RW register reset by core reset. Bit[0]: used for VCCMIN control to select 25MHz clock o…
37061 …- spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'b010 …
37063 … DataWidth:0x2 // 0-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be MISC_REGI…
37064 …aWidth:0x10 // Bypass to the FUNC_HIDE pin. Bit 0 - bypass select; Bits[15:1] - bypass value per…
37065 …x1 // This bit indicates that a Vmain powerdown event occurred. Write 0 to clear the event. Res…
37069 … // NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 - NIG1 debug vec…
37070 …to initiate MDIO transactions to access XGXS0 or the four external GPHYs. Drives misc_cnig_mux_4po…
37071 …1 // NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by N…
37072 …s:R DataWidth:0x2 // SEL_VAUX_B - Control to power switching logic. [0] - output value drive…
37074 …to 1, HiGig is supported on 40G and the nw mac clock frequency is higher than the main clock frequ…
37075 …to a PF pair i.e. bit 0 for global PFs 0 and 1; bit 1 for global PFs 2 and 3. If the bit is clear …
37077 …. Enables the values on MISC_REGISTERS_MDIO_SUBSCRIPTION.MDIO_SUBSCRIPTION to override the hardwar…
37078 …to configure the subscriptions of on-chip PHY devices and MAC ports to the four MDIO domains. It i…
37079 …1 // Set to 1 when pcie_hot_reset is asserted (Hot Reset / SBR / Link Down / Link Disable) and …
37081 …:0x1 // Debug only : parity mode to MCP. Setting this bit changes the parity checking on the me…
37082 …he chip to do an internal reset exactly like a power-up reset. There is not protection for this re…
37083 …e controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - unprepared_power_down_dete…
37084 …he controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - uprepared_power_down_dete…
37085 … 0x009744UL //Access:RW DataWidth:0x1 // Writing to this register result…
37086 … 0x009748UL //Access:RW DataWidth:0x1 // Writing to this register result…
37087 …-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bi…
37088 …0UL //Access:RW DataWidth:0x1 // [0]clock storm bypass: 0-select Storm SPLL clock; 1-select e…
37089 …:RW DataWidth:0x1 // Set by the MCP to remember if one or more of the drivers is/are loaded; …
37090 …:RW DataWidth:0x1 // Set by the MCP to remember if one or more of the drivers is/are loaded; …
37091 … DataWidth:0x1 // Set by the Driver to remember if one or more of the drivers is/are loaded; …
37092 … 0x009760UL //Access:R DataWidth:0x1 // 0 - VAUX is not present (external pin is 0); 1 …
37093 …-6] RESERVED (FLOAT: these IOs are outputs only). [5-4] CLR: When any of these bits is written as …
37096 … the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer t…
37097 …f the chip. This value starts at 0x00 for each all-layer tape-out and increments by one for each t…
37099 …hat the link is down and PCIE is prepared for operation off of VAUX. TBD: set to 0 in NM. Reserved.
37100 …ign has been strapped to support management only. The PCI power will always read as '0' in this st…
37101 …Width:0x1 // The status of the internal perst_n control (active low) that goes to the PCIE CORE.
37103 … 0x00978cUL //Access:RW DataWidth:0x10 // Accounts for Hard reset de-assertion. Is reset o…
37105 … 0x009794UL //Access:RW DataWidth:0x10 // Accounts for Core de-reset assertion. Is r…
37107 … 0x00979cUL //Access:RW DataWidth:0x10 // Accounts for PERST_B reset de-assertion. Is reset o…
37109 … DataWidth:0x10 // Accounts for PCI_RST_N assertion when the chip is in un-prepared state. Is re…
37110 … 0x0097a8UL //Access:RW DataWidth:0x10 // Accounts for PCI_RST_N de-assertion. Is reset o…
37111 …-prepared state, hard reset is asserted. When =0, when ptw_miscs_pcie_hot_reset is asserted (Hot R…
37113 …/Access:RW DataWidth:0x20 // Eco reserved. Global register. [31:30] - used to programm loopbac…
37118 … 0x0097c8UL //Access:RW DataWidth:0x11 // Indirect address. Used to addrerss a register …
37119 …ing from this fetches data from top_addr. Writing stores data to top_addr.
37120 …r-ride: When set, over-ride DAC code from AVS monitor with on from this register [20:11] VMgmt DAC…
37121 …- Per-TC packet available status; [10] - STORM FIFO; [9] - BTB SOP FIFO for engine 0; [8] - BTB S…
37122 …- STORM FIFO almost full; [10] - STORM FIFO full; [9] - BTB SOP FIFO full for engine 0; [8] - …
37123 …- Received packet from BTB IF0 of engine 0; [6] - Received packet from BTB IF0 of engine 1; [5] …
37124 …- storm_init_crd: Credits for the output STORM Packet interface. [3:2] - storm_pkt_dst: Select t…
37125 …-full Threshold. [29:25] - Btb_if0_fifo_almfull_thr: Almost-full threshold for BTB main traffic F…
37131 … (0x1<<0) // This bit will always read '1', as it is not possible to disable the dbu bloc…
37133 …ead '1' if a byte has been received with a framing error. It will continue to read as a '1' until …
37135 …his bit will read '1' of a receive overflow has occurred. It will continue to read as a '1' until …
37138 … (0x1<<0) // This bit will read '1' if there is a valid byte to read in dbu_rxdata. …
37140 … (0x1<<1) // This bit will read '1' if there is data pending to be transmitted in th…
37143 …When the bit is clear, the UART timing will be determined by the timing_select inputs to the block.
37145 … (0x1<<1) // When this bit is set, the debug state machine shall respond to received characters …
37155 …to transmit a single byte of data on the serial interface. Firmware should poll the txdata_occupie…
37157 … (0xff<<0) // Set the VF for which the registers need to be accessed
37159 … (0xff<<8) // Set the Port for which the registers need to be accessed
37167 …alises specific states and statuses. To initialise the state - write 1 into register; to enable wo…
37168 … enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all o…
37169 …t;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
37204 … (0x1<<0) // Signals an unknown address to the rf module.
37214 … (0x1<<0) // Signals an unknown address to the rf module.
37219 … (0x1<<0) // Signals an unknown address to the rf module.
37231 …DataWidth:0x4 // DMAE- PCI Request Interface initial credit. Write writes the initial value to …
37232 …404UL //Access:RW DataWidth:0x1 // Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X re…
37233 …408UL //Access:RW DataWidth:0x1 // 0-PCI type cache snoop protection is required;1-system isn…
37234 …00c40cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 initial value is all zeroes; if 1 - t…
37235 …// If 0 - the CRC-16 final calculation result isn't byte swapped; if 1 - the CRC-16 final calculat…
37236 …0c414UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16c initial value is all zeroes; if 1 - t…
37237 …c418UL //Access:RW DataWidth:0x1 // If 0 - the CRC-16 T10 initial value is all zeroes; if 1 -…
37238 …00c41cUL //Access:RW DataWidth:0x1 // If 0 - the CRC-32 initial value is all zeroes; if 1 - t…
37239 …// If 0 - the CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calculat…
37240 …0c424UL //Access:RW DataWidth:0x1 // If 0 - the CRC-32c initial value is all zeroes; if 1 - t…
37241 …/ If 0 - the CRC-32c final calculation result isn't byte swapped; if 1 - the CRC-32c final calcula…
37242 … DataWidth:0x1 // If 0 - the final checksum equal 0 won't be changed;if 1 - the final checksu…
37243 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37244 …st ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; …
37245 … 0x00c438UL //Access:RW DataWidth:0x1 // When set discards 1- or 2-Dword PCI transact…
37246 …Access:RW DataWidth:0x14 // GRC address in case 1- or 2-Dword PCI transaction is discardd due …
37248 …ering Tag Index (value of 0x1FF means no steering tag in which case steering tag will be set to 0).
37250 …- Bidirectional shared data structure; 01 - Device writes/reads then device reads/writes soon; 10 …
37255 …: 0 - VN Virtualized NIC (Used for VF access); 1 - PDA Physical Device Assignment (Assigned to VM-…
37257 … 0x00c500UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
37258 … 0x00c504UL //Access:RW DataWidth:0x8 // command to CPU BIST
37259 … 0x00c508UL //Access:RW DataWidth:0x8 // address to CPU BIST
37261 … 0x00c510UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
37262 … line) in the selected line (before shift).for selecting a line to output
37270 … //Access:RW DataWidth:0x20 // Commands memory. The address to command X; row Y is to calculat…
37272 …to client interfaces: Bits 0- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; …
37273 …to client interfaces for output to other engine: Bits 0- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; …
37275 … (0x1<<0) // Debug only: This bit is an enable to PCI output request i…
37277 … (0x1<<1) // Debug only: This bit is an enable to PCI output data inte…
37279 … (0x1<<2) // Debug only: This bit is an enable to NIG output data inte…
37281 …as follows: 0-NONE; 1-DoubleBwTx (DoubleBw the TX side); 2-DoubleBwRx (DoubleBw the RX side); 3-Cr…
37282 …dex for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37283 …dex for slot 1 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37284 …dex for slot 2 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37285 …dex for slot 3 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37286 …dex for slot 4 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37287 …dex for slot 5 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37288 …dex for slot 6 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37289 …dex for slot 7 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37290 …dex for slot 8 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37291 …dex for slot 9 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37292 …ex for slot 10 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37293 …ex for slot 11 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37294 …ex for slot 12 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37295 …ex for slot 13 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37296 …ex for slot 14 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37297 …ex for slot 15 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;…
37298 …number of cycles the calendar stays on the same slot before moving to the next slot to support low…
37299 …- 128b STORM (A and B) data is logged 1 - 64b STORM (A and B) data + 4 different (in general case)…
37300 …only: These bits indicate the target of the debug data: 0 - internal buffer; 1 - NIG; 2 - PCI.
37301 …-one shot (newest data is thrown) as follows: (a) When DBG_REGISTERS_DEBUG_TARGET =0 (internal buf…
37303 … (0x1<<0) // Signals an unknown address to the rf module.
37309 … (0x1<<0) // Signals an unknown address to the rf module.
37312 … (0x1<<0) // Signals an unknown address to the rf module.
37318 …inter for the internal buffer; The read pointer describes the next address to be read from the int…
37319 …rnal buffer; The write pointer describes the last address that was written to the internal buffer.…
37320 …GISTERS_DEBUG_TARGET =2 (PCI); The read pointer describes the next address to be read from the ext…
37322 …ess to write to the external buffer; TARGET_PACKET_SIZE chunks counter when DBG_REGISTERS_DEBUG_TA…
37333 …rget_packet_size data byte each); Relevant only when debug_target=1 (NIG) & full_mode=0 (one-shot).
37335 … DataWidth:0x5 // Debug only: This bit is a handle given to the PCI block to refer to this re…
37338 … the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must sta…
37340 …- no grants will be made to the storms when the internal buffer is almost full. When the buffer w…
37341 …be >= 12. Together with DBG_REG_BUFFER_THR_HIGH provides histerezis-like mechanism to set SEMI gra…
37342 …tes logical/physical address in PCI request as follows: (a) 1 - logical address; (b) 0 - physical…
37343 …frame from the input stream to internal buffer to be output to IFMUX interface. 0 - bits[31:0] 1 -…
37344 …// Debug only: together with DBG_REG_BUFFER_THR provides histerezis-like mechanism to set SEMI gra…
37345 …on is done as follows: bits 255:0 - data; bits 263:256 - frame; bits 271:264 - valid; bits 303:272…
37347 …to be compared with the vector {sop[1:0]; id[31:0]; valid[7:0];frame[7:0]; data[255:0]}; This vect…
37349 …to the DBG_REGISTERS_EXPECTED_PATTERN vector as follows: (a) 1 - bit is masked. This bit won't be…
37351 … pattern recognition feature is disabled/enabled as follows: (a) 1 - disabled; (b) 0 - enabled;.
37352 …nition feature as follows: (a) 1 - stop debug data storgae when the expected pattern is initially…
37353 …occurence as follows: (a) 1 - enable continuously data storage after/before first occurence of pat…
37354 …- trigger machine is off (all data will bypass the triggering machine); dbg_sem_trgr_evnt may be …
37355 …010550UL //Access:RW DataWidth:0x1 // (a) 0 - triggering interleaved messages is disabled. (b…
37356 …:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be triggere…
37357 …:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be triggere…
37358 …:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be triggere…
37359 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37360 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37361 …//Access:RW DataWidth:0x1 // (a) 1 - use both constraint set0 and constraint set1 in relevant…
37368 … of times that the referred constraints set should be met prior to recognition (moving to next sta…
37369 … of times that the referred constraints set should be met prior to recognition (moving to next sta…
37370 … of times that the referred constraints set should be met prior to recognition (moving to next sta…
37371 … of times that the referred constraints set should be met prior to recognition (moving to next sta…
37372 … of times that the referred constraints set should be met prior to recognition (moving to next sta…
37373 … of times that the referred constraints set should be met prior to recognition (moving to next sta…
37374 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37375 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37376 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37377 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37378 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37379 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37380 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37381 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37382 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37383 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37384 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37385 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37386 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37387 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37388 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37389 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37390 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37391 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37392 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37393 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37394 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37395 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37396 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37397 …// The data that need to be compared. The 32 bit vector is determined as follows: data[32*(trigger…
37398 … 0x0105fcUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37399 … 0x010600UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37400 … 0x010604UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37401 … 0x010608UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37402 … 0x01060cUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37403 … 0x010610UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37404 … 0x010614UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37405 … 0x010618UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37406 … 0x01061cUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37407 … 0x010620UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37408 … 0x010624UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37409 … 0x010628UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37410 … 0x01062cUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37411 … 0x010630UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37412 … 0x010634UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37413 … 0x010638UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37414 … 0x01063cUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37415 … 0x010640UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37416 … 0x010644UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37417 … 0x010648UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37418 … 0x01064cUL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37419 … 0x010650UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37420 … 0x010654UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37421 … 0x010658UL //Access:RW DataWidth:0x1 // The frame that need to be compared. The 1 b…
37446 … 0x0106bcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37447 … 0x0106c0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37448 … 0x0106c4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37449 … 0x0106c8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37450 … 0x0106ccUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37451 … 0x0106d0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37452 … 0x0106d4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37453 … 0x0106d8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37454 … 0x0106dcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37455 … 0x0106e0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37456 … 0x0106e4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37457 … 0x0106e8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37458 … 0x0106ecUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37459 … 0x0106f0UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37460 … 0x0106f4UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37461 … 0x0106f8UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37462 … 0x0106fcUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37463 … 0x010700UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37464 … 0x010704UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37465 … 0x010708UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37466 … 0x01070cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37467 … 0x010710UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37468 … 0x010714UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37469 … 0x010718UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37470 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37471 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37472 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37473 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37474 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37475 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37476 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37477 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37478 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37479 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37480 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37481 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37482 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37483 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37484 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37485 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37486 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37487 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37488 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37489 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37490 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37491 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37492 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37493 …nd trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c) 010…
37614 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37615 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37616 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37617 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37618 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37619 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37620 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37621 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37622 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37623 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37624 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37625 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37626 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37627 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37628 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37629 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37630 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37631 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37632 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37633 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37634 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37635 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37636 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37637 …s after start of message on data[32*(trigger_state_set_cnstr_offseti[2:0]+1)-1:32*trigger_state_se…
37686 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37687 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37688 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37689 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37690 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37691 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37692 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37693 …- regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)…
37694 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37695 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37696 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37697 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37698 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37699 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37700 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37701 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37702 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37703 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37704 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37705 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37706 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37707 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37708 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37709 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic com…
37710 … // (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use masking acc…
37711 … // (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use masking acc…
37712 … // (a) 1: use trigger_state_msg_lengthi to determine message boundary. (b) 0: use masking acc…
37713 … 0x010968UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37714 … 0x01096cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37715 … 0x010970UL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37718 …to the data that should be recorded for indirect value usage. If set of constraints appear more th…
37719 …to the data that should be recorded for indirect value usage. If set of constraints appear more th…
37720 …to the data that should be recorded for indirect value usage. If set of constraints appear more th…
37724 …d with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to tri…
37725 …d with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to tri…
37726 …d with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to tri…
37729 …to the data that should be recorded for indirect value usage. If set of constraints appear more th…
37730 …to the data that should be recorded for indirect value usage. If set of constraints appear more th…
37731 …to the data that should be recorded for indirect value usage. If set of constraints appear more th…
37735 …with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to tri…
37736 …with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to tri…
37737 …with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to tri…
37739 …- Filter off; in that case all data should be transmitted to the internal buffer without any filte…
37740 …:0] are used. Bit[3] should be set to 0. For STORM bit[3] designates what STORM should be triggere…
37741 …s:RW DataWidth:0x20 // The value that need to be compared with data[32*(filter_cnstr_offseti[2…
37742 …s:RW DataWidth:0x20 // The value that need to be compared with data[32*(filter_cnstr_offseti[2…
37743 …s:RW DataWidth:0x20 // The value that need to be compared with data[32*(filter_cnstr_offseti[2…
37744 …s:RW DataWidth:0x20 // The value that need to be compared with data[32*(filter_cnstr_offseti[2…
37745 … 0x0109e8UL //Access:RW DataWidth:0x1 // The value that need to be compared with fra…
37746 … 0x0109ecUL //Access:RW DataWidth:0x1 // The value that need to be compared with fra…
37747 … 0x0109f0UL //Access:RW DataWidth:0x1 // The value that need to be compared with fra…
37748 … 0x0109f4UL //Access:RW DataWidth:0x1 // The value that need to be compared with fra…
37753 … 0x010a08UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37754 … 0x010a0cUL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37755 … 0x010a10UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37756 … 0x010a14UL //Access:RW DataWidth:0x1 // (a) 1 - the frame is masked (not compared); (b) 0 …
37757 …L //Access:RW DataWidth:0x5 // The filtering is implemented according to the data on the firs…
37758 …L //Access:RW DataWidth:0x5 // The filtering is implemented according to the data on the firs…
37759 …L //Access:RW DataWidth:0x5 // The filtering is implemented according to the data on the firs…
37760 …L //Access:RW DataWidth:0x5 // The filtering is implemented according to the data on the firs…
37761 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37762 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37763 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37764 …ctual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 …
37789 …R filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering m…
37790 …R filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering m…
37791 …R filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering m…
37792 …R filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering m…
37793 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37794 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37795 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37796 …r_oprtni > 000 or 101) (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comp…
37797 …taWidth:0x1 // (a) 1: use filter_msg_length to determine message boundary. (b) 0: use the frame…
37798 … 0x010a7cUL //Access:RW DataWidth:0x8 // Message length-1 in terms of numbers of 128-bit cy…
37799 …en message is filtered). Note: (a) When filter_enable = 1 (Filter on prior to trigger_event) the m…
37800 …cess:RW DataWidth:0x8 // The message length-1 of the recorded part size in terms of numbers o…
37801 …to trigger event: (a) 00 - record from time=0; (b) 01 - record rcrd_on_window_pre_num_chunks chun…
37802 … (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_…
37803 …to the internal buffer prior to triggering event. NOTE: (1) applicable only when rcrd_on_window_p…
37805 … 0x010a98UL //Access:RW DataWidth:0x10 // 16-bit opaque FID for pc…
37814 …his can be used in Emulation when The driver identifies an error and write to the for triggerig pu…
37815 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37816 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37817 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37818 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37819 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37820 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37821 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37822 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37823 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37824 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
37825 …to trailer when HW block is selected: [2:0] - bits[31:0]; [5:3] - bits[63:32]; [8:6] - bits[…
37826 … for each STORM that will be added to trailer when STORM will be selected: B2:0 - TSEM; B5:3- MSEM…
37835 …0x4 // Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 M…
37836 … packet size to NIG or PXP target is in granularity of chunks. The allowed range is 1-48 that suit…
37837 … DataWidth:0x1 // When 1 enables inserting packet counter at the output to NIG between Ethernet…
37838 …ss:R DataWidth:0x10 // Packet counter value. Contains number of packets that were sent to NIG.
37840 …s timestamp_tick value. It may be reset from RBC or set to any init value. This counter starts to …
37843 …x7 // Timestamp valid enable. This register enables inserting timestamp to bits 31:0 when bit[0…
37844 …. When set enable stall output from DBG to SEM block as result of trigger event: 0 is TSEM; 1- MSE…
37845 … // Current state machine status of trigger block in dbg_trigger.v: states 0-2 are functional stat…
37846 …ock in dbg_trigger_state.v: : state 0 - NOT_HNDLR_MSG; state 1- FRST_HNDLR_MSG; state 2- SCND_HNDL…
37849 …- constraint 0 set0; B1 - constraint 1 set0; B2 - constraint 2 set0; B3 - constraint 3 set0; B4 - …
37851 … Debug only: These bits represent the total number of 128-bit cycles sent from the dbg block to ou…
37855 … status in trailer block : 0 - WAIT_FOR_NEW_LINE; 1- END_OF_CHUNK; 2 - SEND_ADDITIONAL_CHUNK; 3 - …
37857 … // Statistics. Match constraint status. B0 - constraint 0; B1 - constraint 1; B2 - constraint …
37858 … 0x010b94UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
37859 … 0x010b98UL //Access:RW DataWidth:0x8 // command to CPU BIST
37860 … 0x010b9cUL //Access:RW DataWidth:0x8 // address to CPU BIST
37863 …:0x1 // When set to 0 - only client which HW ID is defined in DBG_REGISTERS_FILTER_ID_NUM.FILTE…
37864 …ccess:RW DataWidth:0x1 // When 0 - SEMI core A is selected for all trigger/filter related act…
37873 …to Low and high again for the next command execution to start; [5:1]: Command: 0: Read; 1: OTP_Pro…
37876 …to sample READ data in burst mode; [1]: cmd_done: Command Done, This signal indicates the completi…
37878 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37879 … 0x02020cUL //Access:RW DataWidth:0x20 // Used to provide write data w…
37884 …b0010: 27Mhz 4'b0100: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 4. Global…
37887 …rmal operation is controlled by straps on the board. This bit allows it SW to override the setting…
37888 … 0x02021cUL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf setting …
37890 …y control 0: 27Mhz 1: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 1. Global…
37893 …rmal operation is controlled by straps on the board. This bit allows it SW to override the setting…
37894 …ss:RW DataWidth:0x1 // 0: divide core_pll clock by 2/4/8/16 according to postdiv setting (def…
37897 …Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario sho…
37899 …L ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct is set to 1
37908 … 0x020238UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): refer to postdiv…
37909 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37911 … 0x02023cUL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer to predi…
37949 …Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario sho…
37957 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
37960 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
37965 …er Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 0…
37966 … 0x020264UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
37967 … 0x020268UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf setting …
37968 … 0x020268UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
37970 … 0x02026cUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-2 000000…
37971 …ss:RW DataWidth:0x1 // 0: divide core_pll clock by 2/4/8/16 according to postdiv setting (def…
37973 … 0x020270UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-3 000000…
37976 … 0x020274UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-4 000000…
37977 …L ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct is set to 1
37979 … 0x020278UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-5 000000…
37982 … 0x02027cUL //Access:RW DataWidth:0x10 // Number to VCO clock to delay Channel…
37984 …Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario sho…
37985 … 0x020280UL //Access:RW DataWidth:0x10 // Number to VCO clock to delay Channel…
37986 … 0x020284UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): refer to postdiv…
37987 … 0x020284UL //Access:RW DataWidth:0x10 // Number to VCO clock to delay Channel…
37988 … 0x020288UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer to predi…
37989 … 0x020288UL //Access:RW DataWidth:0x10 // Number to VCO clock to delay Channel…
37991 … 0x02028cUL //Access:R DataWidth:0x4 // Delay for each channel 2-5 is completed.
38003 …to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndi…
38006 …to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndi…
38012 …tional path during fine phase acquisition mode. SW needs to use the following transformation to pr…
38019 … 0x0202b4UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf setting …
38023 …ss:RW DataWidth:0x1 // 0: divide core_pll clock by 2/4/8/16 according to postdiv setting (def…
38024 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38026 …-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= di…
38027 …L ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct is set to 1
38030 … 0x0202c8UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38032 … 0x0202ccUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38033 … 0x0202d0UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): refer to postdiv…
38035 … 0x0202d4UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer to predi…
38036 …to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndi…
38038 …to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndi…
38044 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38045 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38046 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38047 …tional path during fine phase acquisition mode. SW needs to use the following transformation to pr…
38048 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38049 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38050 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38052 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38053 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38054 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38062 …ccess:W DataWidth:0x1 // Setting this bit high will result in the HW to capture the frequenc…
38063 …ccess:W DataWidth:0x1 // Setting this bit high will result in the HW to capture the frequenc…
38064 …ccess:W DataWidth:0x1 // Setting this bit high will result in the HW to capture the frequenc…
38073 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38088 … 0x020304UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38089 … 0x0204b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38090 … 0x0202a8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38091 … 0x020308UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38092 … 0x020308UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38093 … 0x0204b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38094 … 0x0202acUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38095 … 0x02030cUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38097 … 0x0204bcUL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38098 … 0x0202b0UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38099 … 0x020310UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38100 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38101 … 0x0204c0UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38102 … 0x0202b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38103 … 0x020314UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38104 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38105 … 0x0204c4UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38106 … 0x0202b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38107 … 0x020318UL //Access:R DataWidth:0x20 // This is a 32-bit free running coun…
38108 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38109 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38110 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38111 … // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up
38117 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38118 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38119 …aWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would …
38120 … 0x020324UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL …
38121 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38122 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38123 … This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-ass…
38129 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38130 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38131 …//Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted
38133 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38134 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38135 …-> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone…
38148 … (0x1<<0) // Signals an unknown address to the rf module.
38150 …1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
38152 …5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
38154 …0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
38156 …1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to hi…
38174 …-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= d…
38208 … (0x1<<0) // Signals an unknown address to the rf module.
38210 …1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
38212 …5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
38214 …0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
38216 …1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to hi…
38234 … 0x020344UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 000000…
38238 … (0x1<<0) // Signals an unknown address to the rf module.
38240 …1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
38242 …5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
38244 …0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
38246 …1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to hi…
38264 … 0x020348UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 000000…
38268 …-bit compliance enable pins on the ballout. These bits are used to override the pins if needed. 2'…
38270 … (0x1<<4) // Set this bit to override the pins on…
38273 …- control of the tcam bist is from the IPC register tcam_bist_control and tcam_bist_num. 1 - contr…
38274 …- control of the tcam bist is from the IPC register tcam_bist_control and tcam_bist_num. 1 - contr…
38275 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38278 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38279 …am bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist…
38280 …am bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist…
38281 …-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be s…
38282 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38283 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38285 …- bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - re…
38286 …- bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - re…
38288 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38289 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38290 … 0x020364UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL …
38291 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38292 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38294 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38295 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38297 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38298 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38300 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38301 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38303 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38304 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38306 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38307 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38309 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38310 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38312 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38313 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38315 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38316 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38318 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38319 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38320 …ss:RW DataWidth:0x5 // MDIO PHY Address. The SERDES uses this address to determine whether or…
38321 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38322 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38324 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38325 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38327 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38328 …- bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should…
38329 … 0x020398UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38330 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38331 …ue. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divid…
38332 … 0x02039cUL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38356 …ss:RW DataWidth:0x5 // MDIO PHY Address. The SERDES uses this address to determine whether or…
38362 … 0x0203c4UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38363 …ess:RW DataWidth:0x6 // Sets the CTL# (# in [0..5]) I/Os of the PADS in non - scan/mbist modes
38365 … 0x0203c8UL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global …
38366 …cess:RW DataWidth:0x2 // Sets the SL# (# in [0..1]) I/Os of the PADS in non - scan/mbist modes
38368 … 0x0203ccUL //Access:R DataWidth:0x8 // PCIe lock signals. 0-unlocked; 1-locked. Global …
38372 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38373 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
38414 …ss:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value…
38422 …ss:RW DataWidth:0x1 // Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value…
38424 … 0: Normal Operation Mode 1: Powerdown the RESCAL block Transition from 1->0 to start calibration …
38426 …takes control of the RESCAL block manitpulates the pwrdn and reset signals to start its own calibr…
38427 …ataWidth:0x1 // Setting this bit starts the HW based calibration engine to recalibrate the resc…
38429 …to analog [10] inversion of vrefs to analog [9] wait time after increasing pon 1'b0: 8 refclk 1'b1…
38435 … On-chip Sheet Resistance 0000 -24% ~ -21% 0001 -21% ~ -18% 0010 -18% ~ -15% 0011 -15% ~ -12% 0100…
38455 …RW DataWidth:0x1 // Setting this bit to "1" will enable the phase shift logic betweent the th…
38456 …-> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO tran…
38457 …-> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the…
38458 …-> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency e…
38464 … 0x0204e8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38465 … 0x0204ecUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38466 … 0x0204f0UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38467 … 0x0204f4UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38468 … 0x0204f8UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38469 … 0x0204fcUL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38470 … 0x020500UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38471 … 0x020504UL //Access:R DataWidth:0x20 // These bits represent the 256-bits of the configura…
38481 …to be filled with a certain threshold bytes and then exit LPI. This allows for the system to not w…
38482 …mitter is IDLE, CPMU will wait for the sleep threshold to expire before setting the LPI request to…
38502 …0) // 0 : DORQ Event is not part of the equation to exit LPI. 1 : DORQ Event is part of the equati…
38504 …1) // 0 : NCSI Event is not part of the equation to exit LPI. 1 : NCSI Event is part of the equati…
38506 …// 0 : PCIe L1 exit is not part of the equation to exit LPI. 1 : PCIe L1 exit is part of the equat…
38508 … : pbf almost full is not part of the equation to exit LPI. 1 : pbf almost full is part of the equ…
38510 … : BMB almost full is not part of the equation to exit LPI. 1 : BMB almost full is part of the equ…
38516 …to "1" will allow software to force an LPI request on the interface. Clearing this bit will not au…
38517 … // Setting this bit to "1" will allow software to provide an early indication to exit LPI state. …
38524 … (0x1<<2) // Setting this bit forces the CPMU to force the device IDL…
38532 …01 : Forces the CPMU to override the OBFF state that was received from the CPU. The override state…
38538 … // Setting this bit to "1" will allow software to force an exit from the OBFF related stalls. HW…
38543 …to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the syste…
38544 …to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the syste…
38545 …to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the syste…
38546 …to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the syste…
38547 …:RW DataWidth:0x20 // This register sets the Sleep Threshold for entry to OBFF state. The reso…
38598 …:0x6 // This register sets the VOQ number for IGU request. This is used to distinguish between …
38599 … long timer threshold for the corresponding VOQ. This register correcponds to bits [31:0] of the V…
38600 … long timer threshold for the corresponding VOQ. This register correcponds to bits [33:32] of the …
38601 …to PCIe L1 is not enabled. 1 : Entry to PCIe L1 is enabled. This reflects the CPMU output and it i…
38631 …to "1" will allow software to force an L1 request on the interface. Clearing this bit will not aut…
38632 … // Setting this bit to "1" will allow software to provide an early indication to exit L1 state. H…
38633 … 0x03027cUL //Access:RW DataWidth:0x1 // 0 : Entry to PCIe LTR is not enabled. 1 : Entry to P…
38667 …to "1" will allow software to force an LTR request on the interface. Clearing this bit will not au…
38668 … // Setting this bit to "1" will allow software to provide an early indication to exit LTR state. …
38670 … (0x1<<0) // 0 : Shutdown Main Clock to Path 0 1 : Enable Main Clock to Path…
38672 … (0x1<<1) // 0 : Shutdown Main Clock to Path 1 1 : Enable Main Clock to Path…
38674 … (0x1<<2) // 0 : Shutdown Main Clock to Path 0 on the Network side 1 : Enable Main Clo…
38676 … (0x1<<3) // 0 : Shutdown Main Clock to Path 1 on the Network side 1 : Enable Main Clo…
38678 … (0x1<<4) // 0 : Shutdown Main Clock to Common Logic on the Network side 1 : Enable Main …
38680 … (0x1<<5) // 0 : Shutdown Main Clock to Common Logic on the Host side 1 : Enable Main C…
38682 … (0x1<<6) // 0 : Shutdown STORM Clock to Path 0 1 : Enable STORM Clock to Pat…
38684 … (0x1<<7) // 0 : Shutdown STORM Clock to Path 1 1 : Enable STORM Clock to Pat…
38686 … (0x1<<8) // 0 : Shutdown Network Clock to Path 0 1 : Enable Network Clock to Pa…
38688 … (0x1<<9) // 0 : Shutdown Network Clock to Path 1 1 : Enable Network Clock to Pa…
38690 … (0x1<<10) // 0 : Shutdown Network Clock to Common logic 1 : Enable Network Clock to…
38692 … (0x1<<11) // 0 : Shutdown Configuration Clock to PCIe Core 1 : Enable Configuration Clock t…
38694 … (0x1<<12) // 0 : Shutdown PCI Clock to Path 0 1 : Enable PCI clock to Path…
38696 … (0x1<<13) // 0 : Shutdown PCI Clock to Path 1 1 : Enable PCI clock to Path…
38698 … (0x1<<14) // 0 : Shutdown PCI Clock to Common logic on the host side 1 : Enable PCI cl…
38700 … (0x1<<15) // 0 : Shutdown all clocks to the Falcon based Port Macro 1 : Enable all clo…
38702 … (0x1<<16) // 0 : Shutdown all clocks to the Eagle based Port Macro 1 : Enable all cloc…
38704 … (0x1<<17) // 0 : Shutdown NWM clock to the NW MAC 1 : Enable NWM clock to th…
38706 … (0x1<<18) // 0 : Shutdown Main Clock to the BMB PD 1 : Enable Main Clock to th…
38708 … (0x1<<19) // 0 : Shutdown Network Clock to the BMB PD 1 : Enable Network Clock to …
38710 … (0x1<<20) // 0 : Shutdown Main Clock to the NW PD 1 : Enable Main Clock to th…
38712 … (0x1<<21) // 0 : Shutdown Main Clock to the NMC PD 1 : Enable Main Clock to th…
38714 … (0x1<<22) // 0 : Shutdown Network Clock to the NMC PD 1 : Enable Network Clock to …
38716 … (0x1<<23) // 0 : Shutdown AHB Clock to the NMC PD 1 : Enable AHB Clock to th…
38718 … (0x1<<24) // 0 : Shutdown Main Clock to the TOP 1 : Enable Main Clock to the…
38740 …ock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register …
38741 …ock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register …
38742 …ock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register …
38743 …ock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register …
38796 …0x0302c8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force …
38797 …ess:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indic…
38850 …0x0302d8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force …
38851 …ess:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indic…
38904 …0x0302e8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force …
38905 …ess:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indic…
38958 …0x0302f8UL //Access:RW DataWidth:0x1 // Setting this bit to "1" will allow software to force …
38959 …ess:W DataWidth:0x1 // Setting this bit to "1" will allow software to provide an early indic…
39233 … (0x1<<0) // Signals an unknown address to the rf module.
39239 … (0x1<<0) // Signals an unknown address to the rf module.
39242 … (0x1<<0) // Signals an unknown address to the rf module.
39259 … (0x1<<0) // Setting this bit to a '1' will result in all packets received from BMC to…
39261 …to a '1' will result in all packets received from BMC that meet the matching of Source MAC address…
39263 … (0x1<<2) // 0 -> Send all broadcast packets to the appropriate network port. 1 -> Se…
39265 … (0x1<<3) // 0 -> Send all multicast packets to the appropriate network port. 1 -> Se…
39267 … (0x1<<4) // 0 -> only MAC address is used for comparison to detect Host2BMC traffic. 1 -> MAC …
39269 …) // 0 -> Do not enable source MAC address learning for packets from Host to BMC. 1 -> Enable sour…
39271 … (0x1<<6) // 0 -> Entries in SA Learning Cache are valid even after they…
39273 … (0x1<<7) // Setting this bit to a '1' will result in…
39275 …Setting this bit to a '1' will result in XOFF to be sent out to BMC. Clearing this register after …
39277 … (0x1<<9) // Setting this bit to a '1' tells the HW t…
39279 … (0x1<<10) // 0 -> Select NCSI RMII interface as the MII port …
39281 … (0x1<<11) // 0 -> Select NCSI RMII interface as the Management Po…
39283 … (0x1<<12) // 1 -> When BMB asserts any full condition, drop all the packets 0 -> Dro…
39285 … (0x1<<13) // 1 -> When this bit is set, all pass through traffic will be directed to hos…
39288 …to MCP as these are NCSI control packets as defined in the spec. This register allows SW to progra…
39289 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39290 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39291 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39292 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39293 …to send a packet to that channel, it will use the MAC address as the Source MAC address in the pac…
39294 …to send a packet to that channel, it will use the MAC address as the Source MAC address in the pac…
39295 …to send a packet to that channel, it will use the MAC address as the Source MAC address in the pac…
39296 …to send a packet to that channel, it will use the MAC address as the Source MAC address in the pac…
39297 …to send a packet to that channel, it will use the MAC address as the Source MAC address in the pac…
39298 …to send a packet to that channel, it will use the MAC address as the Source MAC address in the pac…
39299 …to send a packet to that channel, it will use the MAC address as the Source MAC address in the pac…
39300 …to send a packet to that channel, it will use the MAC address as the Source MAC address in the pac…
39305 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39306 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39307 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39308 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39309 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39310 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39311 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39312 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39313 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39314 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39315 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39316 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39317 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39318 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39319 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39320 … is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Addr…
39369 …is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Addr…
39370 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39371 …is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Addr…
39372 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39373 …is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Addr…
39374 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39375 …is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Addr…
39376 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39377 …is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Addr…
39378 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39379 …is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Addr…
39380 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39381 …is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Addr…
39382 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39383 …is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Addr…
39384 …ed. Every time another packet is received on the same entry, the timer is re-started. When the tim…
39385 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39386 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39387 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39388 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39389 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39390 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39391 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39392 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39393 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39394 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39395 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39396 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39397 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39398 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39399 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39400 …ost to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at w…
39417 …Source Address Learning cache entries in seconds. When an entry is written to the cache, a timer i…
39420 … (0x1<<0) // Setting this bit to "1" will result in r…
39422 …// NCSI block has the capability to remove up-to six TAGs present in a packet. This field sets whi…
39424 …to configure how the inner vlan tag needs to be handled. Inner VLAN is always the 2nd tag in a pac…
39426 …ength to remove this header from the packet before sending it out to BMC. it is expected that once…
39434 … (0x1<<0) // Tells HW to set the INS_PROP_HEADER flag in the SOP descriptor f…
39436 … (0x1<<1) // Tells HW to set the INS_OUTER_TAG flag in the SOP descriptor fo…
39438 … HW to set the OVRRIDE_INNER_VLAN flag in the SOP descriptor for a BMC to Network packet if there …
39440 … (0x1<<3) // Tells HW to set the OVRRIDE_INNER_VLAN flag in the SOP descriptor…
39442 … (0x1<<4) // Tells HW to set the OVRRIDE_PRIORITY flag in the SOP descriptor …
39445 … (0x7<<0) // This field is used to set the ID of the cu…
39449 … (0x1<<4) // Setting this field to '1' causes the hardware arbitration scheme …
39451 … (0x1<<5) // Setting this field to '1' causes the hardware arbitration scheme to begin. Any …
39453 …to '1' the HW arbitration logic to function in bypass mode. This allows NCSI ports that don't have…
39455 … (0x1<<7) // Setting this field to '1' causes the NCSI port to cut la…
39457 … (0x1f<<8) // This field is a programmable inter-packet gap for when t…
39461 …to send XOFF/XON ordered sets on the arbiter interface. This feature is enabled by default and all…
39463 … (0x1<<15) // Toggle this bit to update this register…
39465 …mber of Ingress clock cycles that the arbitration master will wait before re-starting the arbitrat…
39470 … (0x1<<0) // Setting this bit will create an asychronous reset to the egress logic. Sh…
39472 … (0x1<<1) // Setting this bit will create an asychronous reset to the ingress logic. S…
39474 …448UL //Access:R DataWidth:0x20 // Event Counter: Counts the number of packets sent to Network
39475 …04044cUL //Access:R DataWidth:0x20 // Event Counter: Counts the number of packets sent to Host
39476 …x040450UL //Access:R DataWidth:0x20 // Event Counter: Counts the number of packets sent to mcp
39477 …x20 // Event Counter: Counts the number of packets that were dropped due to source Address misma…
39478 … DataWidth:0x20 // Event Counter: Counts the number of packets that were dropped due to BMB full.
39479 …45cUL //Access:RC DataWidth:0x20 // Event Counter: Counts the number of packets sent to Network
39480 …040460UL //Access:RC DataWidth:0x20 // Event Counter: Counts the number of packets sent to Host
39481 …x040464UL //Access:RC DataWidth:0x20 // Event Counter: Counts the number of packets sent to mcp
39482 …x20 // Event Counter: Counts the number of packets that were dropped due to source Address misma…
39483 … DataWidth:0x20 // Event Counter: Counts the number of packets that were dropped due to BMB full.
39484 …to be accumulated before starting a transfer to the BMC. this register is provided to prevent any …
39485 … 0x040474UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
39486 … line) in the selected line (before shift).for selecting a line to output
39496 … (0x1<<0) // Signals an unknown address to the rf module.
39502 … (0x1<<0) // Signals an unknown address to the rf module.
39505 … (0x1<<0) // Signals an unknown address to the rf module.
39507 … DataWidth:0x1 // Reset the protection override window memory. When set to 1, protection overri…
39510 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39511 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39513 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39514 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39516 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39517 …t latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
39519 …- VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s)…
39521 …to the FIFO is done based on the different trace FIFO configurtaions. If …
39522 …to the trace FIFO. The range can be from one master to all masters, all combinations. If = 1, the …
39523 …to the trace FIFO. The range can be all combinations. If = 1 the error is enabled, access with app…
39524 …to the trace FIFO. One or both types can be enabled. If = 1 the wr/rd access is enabled, wr/rd acc…
39525 …to the trace FIFO. The range is from one PF to all PFs, all combinations. If = 1 the PF is enabled…
39526 …CE_FIFO_VF for the accesses that are written to the trace FIFO. If = 0, accesses with all VFs are …
39527 …ten to the trace FIFO. Applicable only if GRC_REG_TRACE_FIFO_VF_SEL = 1. Value of all 1s is applic…
39528 …to the trace FIFO. The range is from one port to all ports, all combinations. If = 1 the port is e…
39529 …to the trace FIFO. The range is from one privilege to all privileges, all combinations. If = 1 the…
39530 …to the trace FIFO. The range is from one privilege override to all privilege overrides, all combin…
39531 …to the trace FIFO. Selects for each address bit if this bit is enforced. The register GRC_REG_TRAC…
39532 …to the trace FIFO. Selects the value for each address bit. The register GRC_REG_TRACE_FIFO_ADDRESS…
39534 … 0x0500a4UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
39535 … line) in the selected line (before shift).for selecting a line to output
39544 …upied in the dbgsyn clock synchronization FIFO, it does not enable writing to the fifo. This value…
39546 … (0x1<<0) // Signals an unknown address to the rf module.
39550 … Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any …
39568 … (0x1<<0) // Signals an unknown address to the rf module.
39572 … Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any …
39579 … (0x1<<0) // Signals an unknown address to the rf module.
39583 … Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any …
39596 …RW DataWidth:0x1 // Setting this bit enables a timer in the GRC block to timeout any access t…
39598 …TECTION_OVERRIDE_WINDOW memory. The number can be from 0 (no valid window) to 20 (20 valid windows…
39599 …to override the protection levels of a range of GRC addresses. There are 20 windows. Each valid wi…
39601 …x8 // Programmable field representing the minimum number of bits of IFG to enforce between fram…
39605 … (0x7<<2) // Set MAC speed. used to set the core mode of…
39611 …ansmit packets to PHY while in MAC local loopback; when set to '1'; otherwise transmit to PHY is d…
39613 … the PHY (remote loopback); when set to '1'; otherwise transmit to PHY is disabled (normal operat…
39615 … if ignore_tx_pause is not set. When set to '0' (Reset value); the MAC transmit function is disabl…
39617 …nable/Disable MAC receive path. When set to '0' (Reset value); the MAC receive function is disable…
39619 …hen the register bit ENA_EXT_CONFIG is set to '1'. When the Register bit ENA_EXT_CONFIG is set to …
39621 … (0x1<<4) // Enable/Disable MAC promiscuous operation. When asserted (Set to '1'); all frames are…
39623 …to '1'); then padding is removed from the received frame before it is transmitted to the user appl…
39625 …d to the user application. If disabled (Set to reset value '0') the CRC field is stripped from the…
39627 …orward Pause Frames. If enabled (Set to '1') pause frames are forwarded to the user application. I…
39629 …re Pause Frame Quanta. If enabled (Set to '1') received pause frames are ignored by the MAC. When …
39631 …abled (Set to '1') the MAC overwrites the source MAC address with the programmed MAC address in re…
39633 …to '1'; enables half duplex mode; when set to '0'; the MAC operates in full duplex mode. Ignored a…
39637 … this case; the RXFIFO_STAT[1] register bit is not operational (always set to 0). If cleared; disa…
39639 …X are disabled. Config registers are not affected by sw reset. Write a 0 to de-assert the sw reset.
39641 … (0x1<<14) // Corrupt Tx FCS; on underrun; when set to '1'; No FCS corruption when set to '0…
39643 … (0x1<<15) // Enable GMII/MII loopback when set to '1'; normal operation when set to '0'…
39645 …ansmit packets to PHY while in MAC local loopback; when set to '1'; otherwise transmit to PHY is d…
39647 …<<17) // If set; enables the SW programmed Tx pause capability config bits to overwrite the auto n…
39649 …<<18) // If set; enables the SW programmed Rx pause capability config bits to overwrite the auto n…
39651 … (0x1<<21) // If enabled; then CRS input to Unimac is ORed with …
39653 … Pins. When set to '0' (Reset value) the Core speed and Mode is programmed with the register bits …
39655 …able. When set to '1'; MAC Control frames with any Opcode other than 0x0001 are accepted and forwa…
39657 …gth Check Disable. When set to '0'; the Core checks the frame's payload length with the Frame Leng…
39659 …nable Line Loopback i.e. MAC FIFO side loopback; when set to '1'; normal operation when set to '0'…
39661 …to '1'; any frame received with an error is discarded in the Core and not forwarded to the Client …
39667 …-of-band egress flow control is enabled. When this bit is set and input pin ext_tx_flow_control is…
39671 …Access:RW DataWidth:0x20 // Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers t…
39672 …0 // Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 refers to Bit 1 of the MA…
39673 … //Access:RW DataWidth:0x10 // Defines a 16-Bit maximum frame length used by the MAC receive l…
39674 … DataWidth:0x10 // 16-Bit value; sets; in increment of 512 Ethernet bit times; the pause quanta …
39675 …the EFM preamble between 5 and 15 Bytes. When set to 0; 1; 2; 3 or 4; the Preamble EFM length is s…
39677 …se the receive MAC control to detect and act on PAUSE flow control frames. Clearing this bit cause…
39679 … (0x1<<4) // Tx Flow. Setting this bit will allow the transmit MAC control to send PAUSE flow cont…
39689 … (0x1<<5) // Link Status Indication. Set to '0'; when link_status input is low. Set t…
39708 …Width:0x3 // Set the transmit preamble excluding SFD to be programmable from min of 2 bytes to …
39709 …ack-to-Back packets. This is the IPG parameter used exclusively in Full-Duplex mode when two trans…
39710 …dth:0x10 // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
39712 …depends on EEE_en_strap input; which if tied to 1; defaults to enabled; otherwise if tied to 0; de…
39716 … (0x1<<5) // If enabled; UNIMAC will shut down TXCLK to PHY; when in LPI sta…
39720 … (0x1<<7) // When set to 1; enables LP_IDLE Prediction. When set t…
39722 …which condition to move to LPI state must be satisfied; at the end of which MAC transitions to LPI…
39723 …which condition to move to LPI state must be satisfied; at the end of which MAC transitions to LPI…
39724 …L //Access:RW DataWidth:0x10 // This field controls clock divider used to generate ~1us refere…
39726 … this register defines the number of IDLEs to be received by the UniMAC before allowing LP_IDLE to…
39727 …hich MAC must wait to go back to ACTIVE state from LPI state when it receives packet for transmiss…
39728 …hich MAC must wait to go back to ACTIVE state from LPI state when it receives packet for transmiss…
39737 … (0x7f<<16) // Non Back-to-Back Transmit IPG pa…
39739 … (0x7f<<24) // Non Back-to-Back Transmit IPG pa…
39742 … 0x051094UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
39743 … line) in the selected line (before shift).for selecting a line to output
39752 … (0x1<<0) // Signals an unknown address to the rf module.
39762 … (0x1<<0) // Signals an unknown address to the rf module.
39767 … (0x1<<0) // Signals an unknown address to the rf module.
39771 …to the Type/Length field of the Pause frames generated by the MAC and used to validate Pause frame…
39772 …ed into the opcode field of the Pause frames generated by the MAC and used to validate Pause frame…
39773 …opcode. Since PFC is not standardized yet; the opcode must be programmable to make sure that when …
39774 …he destination address field of the MAC generated pause frames and is used to compare against the …
39775 …DA for PPP. Since PPP is not standardized yet; the DA must be programmable to make sure that when …
39776 …he destination address field of the MAC generated pause frames and is used to compare against the …
39777 …DA for PPP. Since PPP is not standardized yet; the DA must be programmable to make sure that when …
39778 … DataWidth:0x20 // Pause frame Destination address. This field is used to compare against the …
39780 … DataWidth:0x10 // Pause frame Destination address. This field is used to compare against the …
39782 …<<0) // Set the bit 0 (Tx_Launch_en) logic 0; if the tx_launch function is to be disabled. If set;…
39784 … enables the CRC corruption on the transmitted packets. The options of how to corrupt; depends on …
39790 …ss:RW DataWidth:0x20 // This register contains the bits [31:0] in the 48-bit MAC address. The…
39792 …L_BB (0x1<<0) // Read-only field assertion …
39794 …TY_BB (0x1<<1) // Read-only field assertion …
39798 …s:RW DataWidth:0x10 // This register contains the bits [47:32] in the 48-bit MAC address. The…
39799 …ery read of this register will fetch out one timestamp value corresponding to the preceding seq_id…
39807 …ac_time_nresume. If rf_omac_time_nresume is set, the chip should continue to send Standard Pause …
39809 …to a priority that should be set in a Per Priority Pause frame. Bit 2 is priority 0 and so on. T…
39815 …- skipped (unsupported) 1 - stackvlan (unsupported) 2 - carrerr (on by default) 3 - codeerr (on by…
39816 … 0x051334UL //Access:RW DataWidth:0x1 // Flush enable bit to drop out all packets…
39817 … 0x051338UL //Access:RW DataWidth:0x8 // probe address bit 7 - U/L bit 6 - GMII/XMGII CLK…
39830 … (0x1<<0) // Enables the PPP-Tx functionality.
39832 … (0x1<<1) // Enables the PPP-Rx functionality.
39834 … (0x1<<2) // Instructs MAC to send Xon message to all classe…
39836 … (0x1<<4) // When set; MAC pass PFC frame to the system. Otherwis…
39838 …ise; PFC counters is in full function. Note: it is programming requirement to set this bit when PF…
39906 …2214UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39907 …2214UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39908 …2218UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39909 …2218UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39910 …221cUL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39911 …221cUL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39912 …2220UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39913 …2220UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39914 …2224UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39915 …2228UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39916 …222cUL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
39917 …2230UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next wri…
40022 … 0x052400UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
40023 … line) in the selected line (before shift).for selecting a line to output
40056 …ncy is more than that number, local edpm_en is de-asserted. It is than combined with edpm_en from …
40165 …_ENTER (0x1<<2) // Set to enter L1 state.
40167 … (0x1<<3) // Set to request entry to L23 state (…
40169 …ER_SEND_LTR1 (0x1<<4) // Set to send LTR1.
40171 …BB (0x1<<0) // Set to enter Root Controlle…
40173 …OW_GEN3_BB (0x1<<1) // Set to allow Gen3 mode.
40215 …hen host system sets OBFF Enable to 2'b11. Firmware must clear this bit when the host changes OBFF…
40217 …2_E5 (0x1<<2) // Set to 1 to indicate that the…
40219 … (0x1<<3) // Set to 1 to prevent incoming Request TLPs from forcing the O…
40258 … 0x054224UL //Access:RW DataWidth:0x20 // 32 bit value to be sent in LTR messa…
40259 … 0x054228UL //Access:RW DataWidth:0x20 // 32 bit value to be sent in LTR messa…
40268 …to hold the LTSSM in the Detect state until your application is ready for the link training to beg…
40270 …K2_E5 (0x1<<0) // When set to 0, HWInit controls a…
40272 … (0x1<<1) // When set to 1, HW delay asserting internal reset to allow FW …
40276 … (0x1<<0) // Indicates that the application logic is ready to have reference clock…
40278 … (0x1<<1) // Acknowledge from the PHY that it is ready to have reference clock…
40280 … (0x1<<2) // While in L1 enable AUX clock to switch from PCLK to free runni…
40283 … (0x1<<0) // Indicates to the PHY that MAC and application is ready …
40285 … // Clock Turnoff request. Allows your application clock generation module to turn off core_clk ba…
40294 …update the PTM Requester Context and Clock now. FW must clear this bit after setting this bit to 1.
40333 … (0x7f<<9) // Common event signal status bus used in RAS D.E.S. time based a…
40340 … (0xffff<<0) // State of selected internal signals in relation to electrical idle (EI)…
40342 …MSG_UNLOCK_K2_E5 (0x1<<16) // One-cycle pulse that indi…
40344 …TURNOFF_K2_E5 (0x1<<17) // One-clock-cycle pulse that i…
40349 …// Wake Up. Used by application logic to wake up the PMC state machine from a D1, D2 or D3 power s…
40357 …sed by firmware due to a bug filed in CQ85027. Indicates that your application must stop generatin…
40375 … (0xffff<<16) // When high a functions ability to generate INTx messag…
40377 … Controls the start/end of time based analysis. You must only set the pins to the required value f…
40380 … //Access:R DataWidth:0x20 // Common debug signal bus that is used in RAS D.E.S. silicon debug
40381 … //Access:R DataWidth:0x20 // Common debug signal bus that is used in RAS D.E.S. silicon debug
40382 … //Access:R DataWidth:0xb // Common debug signal bus that is used in RAS D.E.S. silicon debug
40383 …L //Access:R DataWidth:0x20 // Lane0 debug signal bus that is used in RAS D.E.S. silicon debug
40384 …L //Access:R DataWidth:0x20 // Lane0 debug signal bus that is used in RAS D.E.S. silicon debug
40385 …L //Access:R DataWidth:0xe // Lane0 debug signal bus that is used in RAS D.E.S. silicon debug
40386 …L //Access:R DataWidth:0x20 // Lane1 debug signal bus that is used in RAS D.E.S. silicon debug
40387 …L //Access:R DataWidth:0x20 // Lane1 debug signal bus that is used in RAS D.E.S. silicon debug
40388 …L //Access:R DataWidth:0xe // Lane1 debug signal bus that is used in RAS D.E.S. silicon debug
40389 …L //Access:R DataWidth:0x20 // Lane2 debug signal bus that is used in RAS D.E.S. silicon debug
40390 …L //Access:R DataWidth:0x20 // Lane2 debug signal bus that is used in RAS D.E.S. silicon debug
40391 …L //Access:R DataWidth:0xe // Lane2 debug signal bus that is used in RAS D.E.S. silicon debug
40392 …L //Access:R DataWidth:0x20 // Lane3 debug signal bus that is used in RAS D.E.S. silicon debug
40393 …L //Access:R DataWidth:0x20 // Lane3 debug signal bus that is used in RAS D.E.S. silicon debug
40394 …L //Access:R DataWidth:0xe // Lane3 debug signal bus that is used in RAS D.E.S. silicon debug
40395 …L //Access:R DataWidth:0x20 // Lane4 debug signal bus that is used in RAS D.E.S. silicon debug
40396 …L //Access:R DataWidth:0x20 // Lane4 debug signal bus that is used in RAS D.E.S. silicon debug
40397 …L //Access:R DataWidth:0xe // Lane4 debug signal bus that is used in RAS D.E.S. silicon debug
40398 …L //Access:R DataWidth:0x20 // Lane5 debug signal bus that is used in RAS D.E.S. silicon debug
40399 …L //Access:R DataWidth:0x20 // Lane5 debug signal bus that is used in RAS D.E.S. silicon debug
40400 …L //Access:R DataWidth:0xe // Lane5 debug signal bus that is used in RAS D.E.S. silicon debug
40401 …L //Access:R DataWidth:0x20 // Lane6 debug signal bus that is used in RAS D.E.S. silicon debug
40402 …L //Access:R DataWidth:0x20 // Lane6 debug signal bus that is used in RAS D.E.S. silicon debug
40403 …L //Access:R DataWidth:0xe // Lane6 debug signal bus that is used in RAS D.E.S. silicon debug
40404 …L //Access:R DataWidth:0x20 // Lane7 debug signal bus that is used in RAS D.E.S. silicon debug
40405 …L //Access:R DataWidth:0x20 // Lane7 debug signal bus that is used in RAS D.E.S. silicon debug
40406 …L //Access:R DataWidth:0xe // Lane7 debug signal bus that is used in RAS D.E.S. silicon debug
40407 …8UL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon debu…
40408 …cUL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon debu…
40409 …0UL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon debu…
40410 …4UL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon debu…
40411 …8UL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon debu…
40412 …cUL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon debu…
40413 …0UL //Access:R DataWidth:0x20 // VC0 debug signal bus that is used in RAS D.E.S. silicon debu…
40414 …4UL //Access:R DataWidth:0x10 // VC0 debug signal bus that is used in RAS D.E.S. silicon debu…
40415 … 0x054328UL //Access:R DataWidth:0x5 // pm_dev_num[4:0]- Device number
40416 … 0x05432cUL //Access:R DataWidth:0x8 // pm_bus_num[7:0]- Bus Number
40417 …// SNPS core input bus that can optionally be used to read PHY status. The phy_cfg_status bus maps…
40418 … be used for additional PHY control purposes. The cfg_phy_control bus maps to the PHY Control regi…
40429 … 0x054360UL //Access:RW DataWidth:0x14 // Sampling interval * pclk, 2ns to 2ms.
40430 … 0 or 1, trigger on first occurrence. If greater than 1, wait until counter value match to trigger.
40431 …UL //Access:RW DataWidth:0x18 // If greater than 0, delay trigger count value * pclk, 0 to 32ms
40449 … 0x0543b0UL //Access:RW DataWidth:0x1 // Need to write on init to start MSIX …
40450 … 0x0543b4UL //Access:RC DataWidth:0x1 // Is set to 1 if at least 1 MSIX…
40452 … (0x1<<0) // Signals an unknown address to the rf module.
40472 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40478 … (0x1<<13) // Non-Fatal Error Message s…
40484 … (0x1<<16) // Vendor-Defined Message recei…
40522 … (0x1<<0) // Signals an unknown address to the rf module.
40542 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40548 …E5 (0x1<<13) // Non-Fatal Error Message s…
40554 … (0x1<<16) // Vendor-Defined Message recei…
40557 … (0x1<<0) // Signals an unknown address to the rf module.
40577 … (0x1<<10) // Do not use -- keep mask bit set to 1.
40583 …_E5 (0x1<<13) // Non-Fatal Error Message s…
40589 … (0x1<<16) // Vendor-Defined Message recei…
40602 … 0x0547e8UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
40603 … line) in the selected line (before shift).for selecting a line to output
40608 …_E5 (0x1<<0) // Power-on reset occurred.
40618 …_2_K2_E5 (0x1<<5) // Non-sticky register reset…
40640 …(0x1<<16) // Soft power-on reset occurred. NOTE: This bit is unreliable for indication of a soft p…
40650 …2_K2_E5 (0x1<<21) // Soft non-sticky register reset…
40718 …alises specific states and statuses. To initialise the state - write 1 into register; to enable wo…
40719 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
40721 … (0x1<<0) // Signals an unknown address to the rf module.
40737 … (0x1<<8) // CFC load request FIFO under-run
40741 …to: a) Non-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or …
40771 … (0x1<<0) // Signals an unknown address to the rf module.
40787 …RR (0x1<<8) // CFC load request FIFO under-run
40791 …to: a) Non-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or …
40796 … (0x1<<0) // Signals an unknown address to the rf module.
40812 …ERR (0x1<<8) // CFC load request FIFO under-run
40816 …to: a) Non-first payload QWord (offset other than 0) arives on IEDPM buffer which is free or …
40862 …:0x14 // The offset in units of 4KB from the start of the doorbell space to the start of region …
40863 …:0x14 // The offset in units of 4KB from the start of the doorbell space to the start of region …
40864 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40865 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40866 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40867 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40868 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40869 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40870 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40871 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40872 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40873 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40874 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40875 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40876 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40877 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40878 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40879 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
40880 …2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 me…
40881 …2 // LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 me…
40907 … 0x1004f4UL //Access:RW DataWidth:0x2 // AGG command value in PWM non-DPM mode.
40910 …t this PF belongs to. In 2 port mode it is equal to 0 for all PF-s. In 4 port mode, it is equal to…
40915 …ccess:RW DataWidth:0x1 // Enable DPM doorbells for all this PF child VF-s. In case not set th…
40925 … 0x100800UL //Access:RW DataWidth:0x8 // The CCFC regions to be loaded on XCM doo…
40926 … 0x100804UL //Access:RW DataWidth:0x8 // The CCFC regions to be loaded on XCM doo…
40927 … 0x100808UL //Access:RW DataWidth:0x8 // The CCFC regions to be loaded on TCM doo…
40928 … 0x10080cUL //Access:RW DataWidth:0x8 // The CCFC regions to be loaded on UCM doo…
40929 … 0x100810UL //Access:RW DataWidth:0x1 // If set then CCFC mini-cache is enabled.
40931 …his threshold and first DPM doorbell appears it is truncated to one entry and aborted; non-first d…
40932 …reshold and first DPM doorbell appears it is truncated to one entry and DpmAbort flag is set; non-…
40937 …ess:RW DataWidth:0xc // Timeout (measured in main clock cycles) for DPM operation to complete.
40942 …th:0x10 // Tag 1 Ethertype used for packet generation in RoCE EDPM mode. Default is set to SVLAN.
40943 …th:0x10 // Tag 2 Ethertype used for packet generation in RoCE EDPM mode. Default is set to CVLAN.
40944 …dth:0x10 // Tag 3 Ethertype used for packet generation in RoCE EDPM mode. Default is set to TTAG.
40945 …Width:0x10 // Tag 4 Ethertype used for packet generation in RoCE EDPM mode. Default is set to CN.
40946 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40947 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40948 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40949 …ion in RDMA EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - …
40952 …L //Access:RW DataWidth:0x20 // Enable bit per each RoCE Opcode 5 LSB-s. N-th bit set means co…
40953 … If 0 - the RoCE CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calcu…
40964 …/Access:RW DataWidth:0x8 // Size in Words of header extracted by PBF and sent to PSTORM in L2.
40965 …ccess:RW DataWidth:0x8 // Offset in Words of header extracted by PBF and sent to PSTORM in L2.
40969 … 0x100918UL //Access:RW DataWidth:0x2 // TPH Hint value in case of non-inline L2 EDPM.
40970 … 0x10091cUL //Access:RW DataWidth:0x3 // ATC attribute value of non-inline L2 EDPM.
40971 … 0x100920UL //Access:RW DataWidth:0x5 // Start offset to read PCM STORM conte…
40972 … 0x100924UL //Access:RW DataWidth:0xe // Maximum non-inline L2 EDPM PktSiz…
40973 …UL //Access:RW DataWidth:0x8 // The maximum number of WORD-s which the PBF may add to the L2 …
40974 … 0x10092cUL //Access:RW DataWidth:0x1 // Set to 1 if IP over NGE hea…
40975 … 0x100930UL //Access:RW DataWidth:0x1 // Set to 1 if Ethernet over N…
40980 …DataWidth:0xb // Counter of DORQ FIFO entries used by corresponding PF or any of its child VF-s.
40982 … number of DORQ FIFO entries used by corresponding PF or any of its child VF-s. This is a per PF c…
40984 …set, PF doorbell with corresponding PF is silently dropped at the entrance to DORQ FIFO. This is a…
40985 …et, VF doorbell with corresponding VF, is silently dropped at the entrance to DORQ FIFO. This is a…
40988 …h:0x1 // If set, DORQ enters freeze mode on the first doorbell drop due to DORQ FIFO overflow. …
40991 …x1 // If set, DORQ enters auto drop mode on the first doorbell drop due to DORQ FIFO overflow. …
40992 …scard mode is active and all doorbells are dropped at the entrance to DORQ FIFO. De-asserted when…
40994 …UL //Access:RW DataWidth:0x8 // Size in bytes of the PXP transactions to be counted in the px…
40995 …dth:0x20 // Accounts for any non-DPM doorbell or first DPM doorbell, which are not silently drop…
40996 …R DataWidth:0x20 // Incremented for each message sent to any one of CMs. Will rollover to 0 w…
41001 …:R DataWidth:0x5 // Debug only: read from DORQ FIFO: number of reads to next information uni…
41002 …r of dropped doorbells. See db_drop_reason for drop reason. Will rollover to 0 when incremented a…
41003 …0 // Stores the details of the first dropped doorbell after logging was re-armed by db_drop_deta…
41004 …-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell…
41005 …-armed by db_drop_details_rel. The following details of the transaction will be recorded: bits[15:…
41007 …to db_drop_details_rel. 0 - Size of the data is not equal to 4 or to a multiple of 8 bytes; 1 - 2 …
41008 …of aborted doorbells. See dpm_abort_reason for abort reason. Will rollover to 0 when incremented a…
41009 …rst aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel…
41010 …rst aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel…
41011 …rst aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel…
41012 …rst aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel…
41013 …to db_abort_details_rel. The following details of the transaction will be recorded: 0 - DPM doorbe…
41015 …to db_abort_details_rel. 0 - DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0…
41027 …to early abort. Only first DPM doorbells, which are silently dropped or early aborted will be cons…
41028 … pop will be considered and specifically only doorbell that is aborted due to DPM global start con…
41029 …The selected size can be a number which is a power of 2 which is between 4 to 256. It is reset on …
41032 …ue of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Re…
41034 …-cache was used. 36 - CDU Validation Error; 35 - CFC Load Cancel; 34 - CFC Load Error; 33 - CFC LC…
41039 …Width:0x1 // comment="Selects IEDPM payload endianity. 0 - little endian (lsB first); 1 - big e…
41040 … 0x100ac0UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
41041 … 0x100ac4UL //Access:RW DataWidth:0x8 // command to CPU BIST
41042 … 0x100ac8UL //Access:RW DataWidth:0x8 // address to CPU BIST
41044 … 0x100ad0UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
41045 … line) in the selected line (before shift).for selecting a line to output
41053 …to DPM Table. Fields mapping is: [198:195] - DPM FSM state [194:192] - DbAggValSel [191:190] - DbA…
41056 … 0x101000UL //Access:RW DataWidth:0x20 // 1) Debug read access to WQE buffer. 2) Initi…
41058 … // 1) Debug read access to WQE buffer. 2) Initialization write access: write all the addresses mo…
41060 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
41061 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
41062 … 0x102808UL //Access:RW DataWidth:0x4 // Maps range 0 to connection type.
41063 … 0x10280cUL //Access:RW DataWidth:0x4 // Maps range 1 to connection type.
41064 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
41065 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
41066 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
41067 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
41068 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
41069 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
41070 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
41071 …Width:0xc // The value in the register, when multiplied by 16, is equal to the maximum ICID plu…
41072 … 0x102830UL //Access:RW DataWidth:0x4 // Maps range 2 to connection type. Thi…
41073 … 0x102834UL //Access:RW DataWidth:0x4 // Maps range 3 to connection type. Thi…
41074 … 0x102838UL //Access:RW DataWidth:0x4 // Maps range 4 to connection type. Thi…
41075 … 0x10283cUL //Access:RW DataWidth:0x4 // Maps range 5 to connection type. Thi…
41076 … 0x102840UL //Access:RW DataWidth:0x4 // Mas range 2 to connection type. Thi…
41077 … 0x102844UL //Access:RW DataWidth:0x4 // Mas range 3 to connection type. Thi…
41078 … 0x102848UL //Access:RW DataWidth:0x4 // Mas range 4 to connection type. Thi…
41079 … 0x10284cUL //Access:RW DataWidth:0x4 // Mas range 5 to connection type. Thi…
41087 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41088 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41089 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41090 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41091 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41092 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41093 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41094 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41095 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41096 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41097 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41098 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41099 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41100 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41101 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41102 …AGG_TYPE will be used as AggDecType in XCM message. Bit[0] - for legacy DPM doorbell, bit[1] - for…
41191 …070cUL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41192 …29a8UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41193 …0710UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41194 …29acUL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41195 …0714UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41196 …29b0UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41197 …0718UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41198 …29b4UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41199 …071cUL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41200 …29b8UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41201 …0720UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41202 …29bcUL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41203 …0724UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41204 …29c0UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41205 …0728UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41206 …29c4UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41207 …29c8UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41208 …29ccUL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41209 …29d0UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41210 …29d4UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41211 …29d8UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41212 …29dcUL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41213 …29e0UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41214 …29e4UL //Access:RW DataWidth:0x4 // The size of the AGG context to be loaded to the XSTORM in…
41360 … 0x102b6cUL //Access:RW DataWidth:0x20 // Used to set TCP RTC. Debug o…
41364 …If 0 - the iWARP CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calcu…
41365 … //Access:RW DataWidth:0x20 // Enable bit per each iWARP Opcode 5 LSB-s. N-th bit set means co…
41374 … DataWidth:0x4 // Enable special flag indications to affect RDMA RoCE EDPM. Enables when set t…
41375 … DataWidth:0x4 // Enable special flag indications to affect RDMA iWARP EDPM. Enables when set t…
41376 …:RW DataWidth:0x4 // Enable special flag indications to affect L2 EDPM. Enables when set to 1.
41380 …e to db_abort_details_rel. The following details of the transaction will be recorded: Doorbell DPM…
41381 …orted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel…
41382 …orted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel…
41383 …orted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel…
41384 …orted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel…
41385 …to db_abort_details_rel. The following details of the transaction will be recorded: 0 - First DPM …
41387 …to db_abort_details_rel. 0 - First DPM doorbell does not match DPM global start conditions at CFC …
41388 …-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: IEDPM…
41389 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41390 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41391 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41392 … Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_d…
41394 …to iedpm_drop_details_rel. 4 - First QWord (offset 0) arives on IEDPM buffer which is not free; 3 …
41406 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in case of QM by…
41407 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in case of QM by…
41408 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in case of QM by…
41409 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41410 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41411 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41412 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41413 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41414 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41415 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41416 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41417 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41418 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41419 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41420 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41421 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41422 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41423 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41424 …cess:RW DataWidth:0x2 // The value of affinity type in CM header sent to XCM in RDMA (RoCE or…
41425 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41426 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41427 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41428 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41429 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41430 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41431 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41432 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41433 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41434 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41435 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41436 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41437 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41438 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41439 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41440 …ess:RW DataWidth:0x1 // The value of exclusive flag in CM header sent to XCM in RDMA (RoCE or…
41441 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41442 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41443 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41444 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41445 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41446 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41447 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41448 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41449 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41450 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41451 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41452 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41453 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41454 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41455 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41456 …ss:RW DataWidth:0x3 // The value of source affinity in CM header sent to XCM in RDMA (RoCE or…
41459 … 0x108000UL //Access:R DataWidth:0x20 // Debug only: Read access to DQ FIFO.
41461 …- mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and …
41463 …1<<0) // If enabled the IGU forwards write/read requests to the TPH interface. 1 - enabled; 0 - di…
41465 … (0x1<<1) // If enabled the IGU allows to VF to send cleanup commands on the int ack address. 1 …
41467 …the IGU allows bypass mode of the rate limiter when the system is empty. 1 - enabled; 0 - disabled.
41469 …DataWidth:0x2 // PXP req credit. The max number of outstanding messages to the PXP request. The…
41470 … 0x180060UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST …
41472 …sed to select the BIST status word to read following the completion of a BIST test. Also used to s…
41473 … 0x18006cUL //Access:R DataWidth:0x20 // Provides read-only access to the BIST stat…
41478 … (0x1<<0) // Signals an unknown address to the rf module.
41480 … (0x1<<1) // Debug FIFO error. Write to full FIFO or read fr…
41486 … (0x1<<4) // VFID bit is set and the command is to attention bit set/cl…
41490 … (0x1<<6) // Prod / Cons update command to invalid SB index.
41498 … (0x1<<10) // Update producer command to attention producer.
41524 … (0x1<<0) // Signals an unknown address to the rf module.
41526 … (0x1<<1) // Debug FIFO error. Write to full FIFO or read fr…
41532 … (0x1<<4) // VFID bit is set and the command is to attention bit set/cl…
41536 … (0x1<<6) // Prod / Cons update command to invalid SB index.
41544 … (0x1<<10) // Update producer command to attention producer.
41547 … (0x1<<0) // Signals an unknown address to the rf module.
41549 … (0x1<<1) // Debug FIFO error. Write to full FIFO or read fr…
41555 … (0x1<<4) // VFID bit is set and the command is to attention bit set/cl…
41559 … (0x1<<6) // Prod / Cons update command to invalid SB index.
41567 … (0x1<<10) // Update producer command to attention producer.
41761 …r of MSI/MSIX/ATTN messages sent for the PF: address 0 - number of MSI/MSIX messages; address 1 - …
41771 …Debug: count the number of PXP requests sent on behalf of a specific MSI/MSI-X vector on the SB in…
41785 … 0x180600UL //Access:RW DataWidth:0x14 // IPS statistics - number of messages s…
41787 …- function enable; b1 - MSI/MSIX enable; b2 - INT enable; b3 - attention enable; b4 - single ISR m…
41788 …h:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enabl…
41816 …th:0x1 // PF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41818 …th:0x1 // VF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.
41822 …n bit condition monitoring; each bit that is set will lock a change from 0 to 1 in the correspondi…
41823 …n bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the correspondi…
41826 …ctor is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabled. …
41827 …to the command_reg_ctrl was a read command, this register holds the 32LSB read value. If address i…
41828 …to the command_reg_ctrl was a read command, this register holds the 32MSB read value. If address i…
41829 …- function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved; [31] command type - …
41830 … 0x18084cUL //Access:RW DataWidth:0x1 // Enable to collect data in the …
41831 … DataWidth:0x20 // Address 0 - MSI address low (two Lsbit are zero). Address 1 - MSI address hig…
41834 …scrubbing is enabled, the match address of the hit response is used to perform a two-cycle …
41836 … read of the entire CAM will be started (or re-started). This will e…
41838 … 0x180864UL //Access:RW DataWidth:0x1 // Enable the RL statistic. 0 - disabled; 1 - enabled.
41868 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41869 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41870 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41871 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41872 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41873 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41874 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41875 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41876 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41877 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41878 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41879 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41880 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41881 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41882 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41883 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41884 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41885 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41886 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41887 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41888 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41889 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41890 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41891 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41892 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41893 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41894 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41895 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41896 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41897 …th:0x9 // The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.
41898 … // Writing the absolute SB index to the register will clear the appropriate vector in the MSIX t…
41899 …t before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod u…
41901 …t before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod u…
41902 …t before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod u…
41903 …ss:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is accordi…
41905 …ss:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is accordi…
41906 …ss:RW DataWidth:0x20 // SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is accordi…
41907 …ster. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (funct…
41909 …ster. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (funct…
41910 …ster. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (funct…
41911 …d - sets the max value that the rate_counter can reach; [19:10] tick_interval - define the max int…
41913 …- receives the tick_interval value when reaching zero; or when writing to the tick_interval. The t…
41923 …er - incremented by one when Tick_value reaches zero and decremented whenever a message from that …
41924 … 0x18120cUL //Access:W DataWidth:0x1 // Writing 1 to this register will c…
41925 … 0x181210UL //Access:W DataWidth:0x1 // Writing 1 to this register will c…
41926 …to the required configuration and it should keep one of the bits that are set in the previous writ…
41927 …Tph field for attention message. Bits 8:0 - steering tag; bits 12:9 - reserved; bits 14:13 - st hi…
41928 …miter group enable status bit for groups 0-31. For each bit: 0 - the rate limiter of the group is …
41929 …iter group enable status bit for groups 32-63. For each bit: 0 - the rate limiter of the group is …
41930 …/ Rate Limiter group credit status bit for groups 0-31. For each bit: 0 - the group has no credit.…
41931 … Rate Limiter group credit status bit for groups 32-63. For each bit: 0 - the group has no credit.…
41932 …imiter group pending status bit for groups 0-31. For each bit: 0 - there are no pending SB in that…
41933 …miter group pending status bit for groups 32-63. For each bit: 0 - there are no pending SB in that…
41934 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port0.
41935 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port1.
41936 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port2.
41937 …tention signal status. Reflects the current value of the attention signals from the MISC-AEU port3.
41938 … 0x181510UL //Access:R DataWidth:0x10 // Debug: messages that wait to be sent; but were no…
41939 …L //Access:R DataWidth:0x5 // Debug: [4] - attention write done message is pending (0-no pen…
41940 …518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 -…
41941 …0x18151cUL //Access:R DataWidth:0x10 // Debug: Interrupt status (active high). BB: PF0 to PF7.
41942 …to the command_debug value. If command_debug is clear it holds the first 64 error commands (comman…
41966 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 0; [7:0] = VF number; if PF - [8…
41968 …tion is collected for FID specified in debug_record_mask_fid_num according to debug_record_mask_fi…
41970 …on is collected for FID equal to debug_record_mask_fid_num. if set the debug information is collec…
41975 …1<<4) // Debug: if set the debug information is collected for source equal to debug_record_mask_so…
41978 …to be collected. The fields: Bit [0] - MSIX read/write; Bit [1] - PBA read/write; Bit [2] - Produc…
41980 … the debug information is collected for the marked commands only according to debug_record_mask_cm…
41984 … 0x181578UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
41985 … line) in the selected line (before shift).for selecting a line to output
41993 … DataWidth:0x18 // Producers only. Address 0-511 match to the mapping memory. Address 512-227:…
41997 …W DataWidth:0x18 // Consumers only. Address 0-511 match to the mapping memory. Address 512-227…
42001 …- valid. [8:1] - vector number (0-128 for PF; 0-63 for VF). [17:9] - FID (if VF: [17] = 0; [16:9] …
42005 …x61 // [63:0] - MSIX message address (bit [1:0] are always zero); [95:64] - MSIX message data; […
42010 … (0x1<<0) // Signals an unknown address to the rf module.
42022 … (0x1<<6) // The FSM arrived to an invalid line.
42024 … (0x1<<8) // Write to full FIFO or read f…
42026 … (0x1<<9) // Write to full FIFO or read f…
42028 … (0x1<<10) // Write to full FIFO or read f…
42030 … (0x1<<7) // Write to full FIFO or read f…
42033 … (0x1<<0) // Signals an unknown address to the rf module.
42045 … (0x1<<6) // The FSM arrived to an invalid line.
42047 … (0x1<<8) // Write to full FIFO or read f…
42049 … (0x1<<9) // Write to full FIFO or read f…
42051 … (0x1<<10) // Write to full FIFO or read f…
42053 … (0x1<<7) // Write to full FIFO or read f…
42056 … (0x1<<0) // Signals an unknown address to the rf module.
42068 … (0x1<<6) // The FSM arrived to an invalid line.
42070 … (0x1<<8) // Write to full FIFO or read f…
42072 … (0x1<<9) // Write to full FIFO or read f…
42074 … (0x1<<10) // Write to full FIFO or read f…
42076 … (0x1<<7) // Write to full FIFO or read f…
42222 … of Protocol Index per Status Block. Value can be even numbers only from 2 to 32. numbers above 12…
42234 … (0x1<<13) // The value of the Pad to Cache Line field in …
42242 … (0x1<<14) // The value of the Pad to Cache Line field in …
42245 … number of outstanding write requests without receiving write done. Values 1-128. Zero is not a va…
42246 …to each bit will reset the whole memory. When the memory reset finished the appropriate bit will b…
42247 …to this register will perform cleanup on the written SB number. [8:0] - SB absolute index; [9] - C…
42249 …p. bits 5:4 Timer expiration priority. Priority values are from 0 (highest priority) to 2 (lowest).
42251 … 0x1c0600UL //Access:RW DataWidth:0x1 // Indicate the size of the CQE. 0 - 32B; 1 - 64B.
42252 …W DataWidth:0x2 // Indicate the size of the AGG unit. 0 - 64B; 1 - 128B; 2 - 256B; 3 - illega…
42253 … 0x1c0608UL //Access:RW DataWidth:0x1 // Flush all command - will flush all the C…
42255 …to TIME WAIT state) and TIME WAIT state (will move to CLEAN). In case this configuration should be…
42256 …to the required configuration and it should keep one of the bits that are set in the previous writ…
42258 … //Access:RW DataWidth:0xa // Threshold in ticks for indicating far timeout to the MISC block.
42260 … 0x1c0780UL //Access:R DataWidth:0x20 // Rx timers status. 0 - inactive 1 - active.
42262 … 0x1c0800UL //Access:R DataWidth:0x20 // Tx timers status. 0 - inactive 1 - active.
42266 … 0x1c0980UL //Access:R DataWidth:0x1 // Debug: IGU-CAU request interface…
42267 … 0x1c0984UL //Access:R DataWidth:0x1 // Debug: IGU-CAU command interface…
42269 … (0x1ff<<0) // Statistic: SB index to collect statistics o…
42274 … (0x1f<<0) // Statistic: protocol number to collect statistics o…
42279 … (0xf<<0) // Statistic: client index to collect statistics o…
42284 … (0xff<<0) // Statistic: Line number of FSM 0 to collect statistics o…
42289 … (0xff<<0) // Statistic: Line number of FSM 1 to collect statistics o…
42293 …r command type. One bit for each timer command type: [0] - rewind; [1] - clear; [2] - rewind to sh…
42294 …er of times that SB was generated (written) for the selected SB (according to stat_ctrl_sb_select_…
42295 …imer was rewind for the selected SB (according to stat_ctrl_sb_select_idx) and timer command (acco…
42296 …imer was rewind for the selected SB (according to stat_ctrl_sb_select_idx) and timer command (acco…
42297 …of times that the timer has expired for FSM0 of the selected SB (according to stat_ctrl_sb_select_…
42298 …of times that the timer has expired for FSM1 of the selected SB (according to stat_ctrl_sb_select_…
42299 …lected SB (according to stat_ctrl_sb_select_idx); selected PI (according to stat_ctrl_protocol_num…
42300 …ducer update commands for the selected PI (according to stat_ctrl_protocol_num) and SB (according …
42301 …0 // The number of incoming commands from the selected client (according to stat_ctrl_client_idx…
42304 …0x1c0ba8UL //Access:RW DataWidth:0x20 // The number of CQE messages that where sent to the PXP.
42311 …- FIFO empty; 1 - FIFO not empty. [0] - PXP command FIFO; [1] - reserved; [2] - timers expiration …
42312 …to the CAU from the PXP: [20:18] - error typ (1- read request; 2 - reserved; 3 - sb_index >= CAU_N…
42313 …to an invalid line: [3:0] - source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6…
42314 … // Debug; [9] if set data valid; [8] previous FSM_sel; [7:4] - previous state; [3:0] - previous…
42315 …th:0x1 // Debug: If set a parity occurd and the CAU assert discard flag to the IGU from now on …
42316 …h:0x19 // comment="Debug: [15:0] The PF that caused the error- one bit per PF; [24:16] - SB inde…
42317 … DataWidth:0x1 // Debug: write only. Writing to this register will copy the aggregation unit st…
42318 …of unit [i] when there was writing to agg_units_state_read_en register. (i =0-15). 0 - free; 1 - d…
42319 …f unit [i] when there was writing to agg_units_state_read_en register. (i = 16-31). 0 - free; 1 - …
42320 …f unit [i] when there was writing to agg_units_state_read_en register. (i = 32-47). 0 - free; 1 - …
42321 …f unit [i] when there was writing to agg_units_state_read_en register. (i = 48-63). 0 - free; 1 - …
42334 … (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 1; [7:0] = VF number; if PF - [8…
42338 … be collected for FID equal to debug_record_mask_fid_num. if set he debug information will be coll…
42343 … // Debug: if set the debug information will be collected for source equal to debug_record_mask_so…
42346 … (0x7<<0) // Debug: command type for the debug. [0] - PI producer update; [1] - cleanup; [2] - …
42348 …debug information will be collected for the marked commands only according to debug_record_mask_cm…
42350 …1c0e00UL //Access:R DataWidth:0x8 // Debug: the number of request that were sent to the IGU.
42357 … 0x1c0ea8UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
42358 … line) in the selected line (before shift).for selecting a line to output
42365 … 0x1c0f0cUL //Access:R DataWidth:0x5 // Debug: FSM state for debug.Idle state value are 0-2
42367 … 0x1c2000UL //Access:WB_R DataWidth:0x80 // Debug: Provides read-only access of the CQ…
42369 … 0x1c2200UL //Access:WB_R DataWidth:0x35 // Debug: Provides read-only access of the IG…
42371 … 0x1c2300UL //Access:WB_R DataWidth:0x62 // Debug: Provides read-only access of the PX…
42373 …2400UL //Access:WB_R DataWidth:0x84 // Debug: Provides read-only access of the PXP write-data FI…
42375 … and PI relative number of each aggregation unit. [0] - valid; [9:1] - absolute SB index; [14:10] …
42377 …to the truth table are the address of the RAM and the outputs is the data in the RAM. The bits [7:…
42379 …-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid…
42387 …ry.[15:0] - protocol producer; [22:16] - PiTimeSet (This value determines the TimeSet that the PI …
42394 …- address; [71:64] - valid slots; [84:72] - FID ([13:9] - PF number (in case of VF the parent PF);…
42396 …h:0x18 // The SB timers. For each SB there are two timers: [11:0] - RX timer; [23:12] - TX timer.
42400 … 0x1f0000UL //Access:RW DataWidth:0x1 // Soft reset - reset all FSM.
42401 … 0x1f0004UL //Access:W DataWidth:0x1 // Any write to this register triggers MAC-VLAN Ca…
42403 … 0x1f000cUL //Access:RW DataWidth:0x1 // When set to 1 the cam hit parity…
42404 … 0x1f0010UL //Access:RW DataWidth:0x1 // When set to 1 the cam miss parit…
42406 … (0x1<<0) // Signals an unknown address to the rf module.
42408 … (0x1<<1) // Load Request Mini-cache validation error
42416 … (0x1<<0) // Signals an unknown address to the rf module.
42418 … (0x1<<1) // Load Request Mini-cache validation error
42421 … (0x1<<0) // Signals an unknown address to the rf module.
42423 … (0x1<<1) // Load Request Mini-cache validation error
42430 … 0x1f0140UL //Access:RW DataWidth:0x8 // The increment value to send in the TCFC loa…
42432 …0168UL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a PF packet, task-…
42433 …016cUL //Access:RW DataWidth:0x10 // Per-PF: If OX_ID exceeds this value on a VF packet, task-…
42434 …0170UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a PF packet, task-…
42435 …0174UL //Access:RW DataWidth:0x10 // Per-PF: If RX_ID exceeds this value on a VF packet, task-…
42441 … 0x1f018cUL //Access:RW DataWidth:0x4 // Connection type to be used in RoCE load…
42442 … 0x1f0190UL //Access:RW DataWidth:0x1 // Per-PF: If set, override …
42443 … 0x1f0194UL //Access:RW DataWidth:0x20 // Per-opcode requester/responder bit to be u…
42444 … 0x1f0198UL //Access:RW DataWidth:0x1 // Per-PF: If set, a load re…
42445 … 0x1f019cUL //Access:RW DataWidth:0x1 // If set, CFC load mini-cache is enabled.
42446 … 0x1f01a0UL //Access:RW DataWidth:0x1 // 0-search response initiator type,1-Excha…
42447 … 0x1f01a4UL //Access:RW DataWidth:0x1 // 0-Exchange Context field in the fcoe search req is z…
42803 … 0x1f0400UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42804 … 0x1f0404UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42805 … 0x1f0408UL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42806 … 0x1f040cUL //Access:RW DataWidth:0x1 // Per-PF: Flag enabling sea…
42807 … 0x1f0410UL //Access:RW DataWidth:0x1 // Enables sending messages to CFC on received firs…
42838 … 0x1f041cUL //Access:RW DataWidth:0x1 // Per-PF: If set, search re…
42839 … 0x1f0420UL //Access:RW DataWidth:0x1 // Per-PF: Enables VF_ID (if it exists) to be …
42840 … 0x1f0424UL //Access:RW DataWidth:0x1 // Per-PF: Enables load request for RoCE pkts to …
42842 … 0x1f042cUL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42843 … 0x1f0430UL //Access:RW DataWidth:0x11 // Per-PF: Max value for tem…
42844 … 0x1f0434UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow …
42845 … 0x1f0438UL //Access:RW DataWidth:0x1 // Per-PF: Enables openflow search for non-IP …
42846 … 0x1f043cUL //Access:RW DataWidth:0x1 // Per-PF: If this field is 1, Over-IPv4-prot…
42888 … // Per-PF: Indicates whether to include the Inner VLAN in the search for each protocol. 0 - TC…
42889 … // Per-PF: Indicates whether to include the Outer TAG in the search for each protocol. 0 - TCP…
42890 …-PF: Indicates whether to include Tenant ID (if it exists) in the search for each encapsulation ty…
42891 … in the search request to be 0 if the ID matches the default value. 0 - L2 GRE, 1 - IP GRE, 2 - V…
42892 …d Ethernet over GRE packet. A zero in this register will mask the corresponding tenant ID bit to 0.
42893 …ulated IP over GRE packet.. A zero in this register will mask the corresponding tenant ID bit to 0.
42894 …encapsulated VXLAN packet.. A zero in this register will mask the corresponding tenant ID bit to 0.
42895 …ant ID exists in the encapsulated T-tag packet.. A zero in this register will mask the correspondi…
42899 …ccess:RW DataWidth:0x20 // If the Tenant ID exists in the encapsulated T-Tag packet and does n…
42900 …ataWidth:0x3 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. The T-tag bit of …
42901 …e encapsulated nge packet.. A zero in this register will mask the corresponding tenant ID bit to 0.
42902 …e encapsulated nge packet.. A zero in this register will mask the corresponding tenant ID bit to 0.
42905 …DataWidth:0x1 // MAC port arbitration guarantees fairness at byte-level (0) or packet-level (1).
42906 … DataWidth:0x1 // Main/LB arbitration guarantees fairness at byte-level (0) or packet-level (1).
42907 … 0x1f0508UL //Access:RW DataWidth:0xa // Initial header size to read from the BRB fo…
42909 … 0x1f0510UL //Access:RW DataWidth:0x8 // Size of inter-packet gap and FCS us…
42910 …to client ID (client IDs are defined in *_arb_priority_client): 0-TC0 traffic; 1-TC1 traffic; 2-T…
42911 …to WFQ credit blocking. The bits are mapped according to client ID (client IDs are defined in *_a…
42912 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
42913 …to be assigned to each priority of the strict priority arbiter. Priority 0 is the highest priorit…
42914 …to be assigned to each priority of the strict priority arbiter. Priority 0 is the highest priorit…
42915 …to have the round-robin arbiter stays on the winning input instead of moving to the next one. Bit…
42916 … 0x1f052cUL //Access:RW DataWidth:0x1 // Enables pseudo-random round robin ar…
42917 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 0 is allowed to reach.
42918 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 0 when it is tim…
42919 …0x1f0538UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42920 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 1 is allowed to reach.
42921 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 1 when it is tim…
42922 …0x1f0544UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42923 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 2 is allowed to reach.
42924 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 2 when it is tim…
42925 …0x1f0550UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42926 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 3 is allowed to reach.
42927 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 3 when it is tim…
42928 …0x1f055cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42929 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 4 is allowed to reach.
42930 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 4 when it is tim…
42931 …0x1f0568UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42932 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 5 is allowed to reach.
42933 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 5 when it is tim…
42934 …0x1f0574UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42935 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 6 is allowed to reach.
42936 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 6 when it is tim…
42937 …0x1f0580UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42938 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 7 is allowed to reach.
42939 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 7 when it is tim…
42940 …0x1f058cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42941 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 8 is allowed to reach.
42942 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 8 when it is tim…
42943 …0x1f0598UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42944 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for main traff…
42945 …0 // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 0 w…
42946 …0x1f05a4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42947 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for loopback t…
42948 … // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 0…
42949 …0x1f05b0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42950 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for main traff…
42951 …0 // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 1 w…
42952 …0x1f05bcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42953 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for loopback t…
42954 … // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 1…
42955 …0x1f05c8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42956 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for main traff…
42957 …0 // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 2 w…
42958 …0x1f05d4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42959 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for loopback t…
42960 … // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 2…
42961 …0x1f05e0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42962 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for main traff…
42963 …0 // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 3 w…
42964 …0x1f05ecUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42965 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for loopback t…
42966 … // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 3…
42967 …0x1f05f8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42968 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for main traff…
42969 …0 // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 4 w…
42970 …0x1f0604UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42971 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for loopback t…
42972 … // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 4…
42973 …0x1f0610UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42974 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for main traff…
42975 …0 // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 5 w…
42976 …0x1f061cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42977 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for loopback t…
42978 … // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 5…
42979 …0x1f0628UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42980 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for main traff…
42981 …0 // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 6 w…
42982 …0x1f0634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42983 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for loopback t…
42984 … // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 6…
42985 …0x1f0640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42986 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for main traff…
42987 …0 // Specify the weight (in bytes) to be added to the credit register for main traffic on TC 7 w…
42988 …0x1f064cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42989 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for loopback t…
42990 … // Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 7…
42991 …0x1f0658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
42992 …idth:0x20 // Specify the upper bound that the credit register is allowed to reach for each port …
42993 …th:0x20 // Specify the weight (in bytes) to be added to the credit register for each port when i…
42994 …0x1f0664UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in the cred…
42995 …-port: Size of the proprietary header for this port (in 4B increments). If proprietary header is d…
43003 … 0x1f0720UL //Access:RW DataWidth:0x8 // Value used to designate TCP in the…
43004 … 0x1f0724UL //Access:RW DataWidth:0x8 // Value used to designate UDP in the…
43005 … 0x1f0728UL //Access:RW DataWidth:0x8 // Value used to designate SCTP in th…
43006 … 0x1f072cUL //Access:RW DataWidth:0x8 // Value used to designate ICMP in th…
43007 …ataWidth:0x6 // Per-port: Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - V…
43008 … 0x1f0734UL //Access:RW DataWidth:0x8 // Value used to designate GRE in the…
43009 … 0x1f0738UL //Access:RW DataWidth:0x10 // Dest port value used to designate a VXLAN he…
43010 … 0x1f073cUL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43011 … 0x1f0740UL //Access:RW DataWidth:0x10 // Per-PF: Base value used i…
43026 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
43027 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
43028 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
43029 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
43030 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
43031 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
43032 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
43033 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
43034 …r-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
43035 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. Applica…
43036 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. Applica…
43037 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. Applica…
43038 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. Applica…
43039 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. Applica…
43040 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. Applica…
43041 … // Per-port: Bit-map indicating which headers must appear in the packet on this port. Applicab…
43044 …. A zero in this register will cause the corresponding bit to not be included in t…
43045 …. A zero in this register will cause the corresponding bit to not be included in t…
43046 … 0x1f07ccUL //Access:RW DataWidth:0x20 // Per-PF/Per-port: Destination …
43047 … 0x1f07d0UL //Access:RW DataWidth:0x10 // Per-PF/Per-port: Destination …
43048 … 0x1f07d4UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43049 … 0x1f07d8UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43050 … 0x1f07dcUL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43051 … 0x1f07e0UL //Access:RW DataWidth:0x20 // Per-PF: Destination IP address match value - …
43052 … 0x1f07e4UL //Access:RW DataWidth:0x2 // Per-PF: Destination IP address match value - …
43053 … 0x1f07e8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43054 … 0x1f07ecUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43055 … 0x1f07f0UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43056 … 0x1f07f4UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43057 … 0x1f07f8UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43058 … 0x1f07fcUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43059 … 0x1f0800UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43060 … 0x1f0804UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43061 … 0x1f0808UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43062 … 0x1f080cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43063 … 0x1f0810UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43064 … 0x1f0814UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43065 … 0x1f0818UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43066 … 0x1f081cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43067 … 0x1f0820UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43068 … 0x1f0824UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43069 … 0x1f0828UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43070 … 0x1f082cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43071 … 0x1f0830UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43072 … 0x1f0834UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43073 … 0x1f0838UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43074 … 0x1f083cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43075 … 0x1f0840UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43076 … 0x1f0844UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43077 … 0x1f0848UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43078 … 0x1f084cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43079 … 0x1f0850UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43080 … 0x1f0854UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43081 … 0x1f0858UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43082 … 0x1f085cUL //Access:RW DataWidth:0x10 // Per-port: Source address …
43083 … 0x1f0860UL //Access:RW DataWidth:0x20 // Per-port: Source address …
43084 … 0x1f0864UL //Access:RW DataWidth:0x10 // Per-port: Source address …
43086 … 0x1f086cUL //Access:RW DataWidth:0x10 // Dest port value used to designate a NGE head…
43087 … 0x1f0870UL //Access:RW DataWidth:0x10 // Dest port value used to designate a RROCE he…
43088 … 0x1f0874UL //Access:RW DataWidth:0x1 // Per-port: Flag enabling …
43089 … 0x1f0878UL //Access:RW DataWidth:0x1 // Per-port: Flag to compare the value of nge versio…
43093 …ets. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43095 … (0x3<<18) // Affinity type to be used in the CM he…
43098 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43100 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43102 … (0x3<<18) // Affinity type to be used in the CM he…
43104 … (0x1<<20) // en_l2_ma to be used in storm con…
43106 … (0x3<<21) // l2_ma_config to be used in storm con…
43108 … (0x1<<23) // inc_sn to be used in storm con…
43111 … (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
43113 …ch in the mac-vlan cache. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg;…
43115 …E5 (0x3<<18) // Affinity type to be used in the CM he…
43117 …E5 (0x1<<20) // en_l2_ma to be used in storm con…
43119 …E5 (0x3<<21) // l2_ma_config to be used in storm con…
43121 …E5 (0x1<<23) // inc_sn to be used in storm con…
43126 …che. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43128 … (0x3<<18) // Affinity type to be used in the CM he…
43130 … (0x1<<20) // en_l2_ma to be used in storm con…
43132 … (0x3<<21) // l2_ma_config to be used in storm con…
43134 … (0x1<<23) // inc_sn to be used in storm con…
43139 … L2. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43141 … (0x3<<18) // Affinity type to be used in the CM he…
43146 …ets. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43148 … (0x3<<18) // Affinity type to be used in the CM he…
43150 … (0x1<<20) // en_l2_ma to be used in storm con…
43152 … (0x3<<21) // l2_ma_config to be used in storm con…
43154 … (0x1<<23) // inc_sn to be used in storm con…
43156 …ket. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43157 … 0x1f093cUL //Access:RW DataWidth:0x4 // Connection type for no-match packets.
43158 … 0x1f0940UL //Access:RW DataWidth:0x4 // Per-port: PFID for no-match packet…
43159 … 0x1f0944UL //Access:RW DataWidth:0x1 // Per-PF: If set, the PFID may be overridden for n…
43160 … 0x1f0948UL //Access:RW DataWidth:0x20 // Per-PF: CID for no-match packets.
43161 … 0x1f094cUL //Access:RW DataWidth:0x9 // Per-PF: LCID for no-match packets.
43169 … 0x1f096cUL //Access:RW DataWidth:0x1 // Per-PF: If set, and PF cl…
43170 …r to use the dest MAC address of the first (0) or encapsulated (1) header in the output message fo…
43171 … to use the source MAC address of the first (0) or encapsulated (1) header in the output message f…
43172 …ther to use the 8021q tag of the first (0) or encapsulated (1) header in the output message for ea…
43173 …-PF: Indicates whether to include Tenant ID (if it exists) in the MAC VLAN Cache entry for each en…
43174 …to build the MAC-VLAN Cache Flexible Field. If two blocks are used, this block is used for the up…
43175 …to build the MAC-VLAN Cache Flexible Field. This block is only used if the number of bytes in mac…
43176 …to bitmask the flexible field formed from the building block information in mac_vlan_flex_upper an…
43177 …to bitmask the flexible field formed from the building block information in mac_vlan_flex_upper an…
43178 … 0x1f09d0UL //Access:RW DataWidth:0x1 // Per-PF: If set, the SACK …
43179 …-FCoE packets. This allows Over-L2-Raw Part2 to be available on non-RoCE packets. The RoCE specifi…
43180 … 0x1f09d8UL //Access:RW DataWidth:0x20 // Per-PF: Mask used in RDMA…
43189 … 0x1f09fcUL //Access:RW DataWidth:0x1 // Per-PF: Enables SYN cooki…
43190 … 0x1f0a00UL //Access:RW DataWidth:0x1 // Per-PF: If set, enables i…
43191 …1 // Per-PF: If set, 4B for Ethernet CRC is included in Packet Length for Statistics field. For…
43192 …-PF: For each bit set, the length of the corresponding tag in the inner header will be subtracted …
43193 …-PF: For each bit set, the length of the corresponding tag in the first header will be subtracted …
43194 … 0x1f0a10UL //Access:RW DataWidth:0x1 // Per-Port: If set and clas…
43195 … 0x1f0a14UL //Access:RW DataWidth:0x8 // Per-Port: If classificati…
43196 … 0x1f0a18UL //Access:RW DataWidth:0x9 // Per-Port: If classificati…
43197 … 0x1f0a1cUL //Access:RW DataWidth:0x20 // Per-PF: This value is passed to the per-PF …
43198 … 0x1f0a20UL //Access:RW DataWidth:0x2 // Per-Port: This value goes…
43199 …:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 0. In 4-port mode, on…
43200 …0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 0. In 4-port mode, only …
43201 …:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 1. In 4-port mode, on…
43202 …0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 1. In 4-port mode, only …
43203 …:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 2. In 4-port mode, on…
43204 …0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 2. In 4-port mode, only …
43205 …:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 3. In 4-port mode, on…
43206 …0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 3. In 4-port mode, only …
43207 …:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 4. In 4-port mode, on…
43208 …0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 4. In 4-port mode, only …
43209 …:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 5. In 4-port mode, on…
43210 …0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 5. In 4-port mode, only …
43211 …:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 6. In 4-port mode, on…
43212 …0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 6. In 4-port mode, only …
43213 …:0x18 // (per-port) Number of messages sent to TCM on the main port for TC 7. In 4-port mode, on…
43214 …0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 7. In 4-port mode, only …
43215 …0x18 // (per-port) Number of messages sent to TCM on the LB port for TC 8. In 4-port mode, only …
43216 …0x1f0a68UL //Access:RW DataWidth:0x3 // bit 0 - ignore for VXLAN, bit 1 - ignore for NGE, bit…
43232 …f the number of packets that have been selected to be processed but have not yet resulted in a mes…
43233 …-port): Packet available status of the main and loopback queues of each traffic class, before bein…
43234 …dth:0x18 // Debug only (per-port): STORM backpressure status (blocked priorities) Each set bit r…
43235 …cUL //Access:R DataWidth:0x1 // Debug only: BRB has asserted Stop Parsing indication to PRS.
43236 …ue of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Re…
43238 …f0b68UL //Access:R DataWidth:0xd // Debug only: In the case of a mini-cache LCID validation…
43239 … 0x1f0b6cUL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
43240 … line) in the selected line (before shift).for selecting a line to output
43248 … 0x1f0bb0UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
43249 … 0x1f0bb0UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
43250 … line) in the selected line (before shift).for selecting a line to output
43251 … line) in the selected line (before shift).for selecting a line to output
43266 …to a FIFO containing information from the last 32 pkts sent to TCM: Reserved - 127:66, Parsing and…
43268 … 0x1f0e00UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
43269 … line) in the selected line (before shift).for selecting a line to output
43277 …ss:RW DataWidth:0x8 // The initial credit in the packet start message to the ptld interface. …
43278 …th:0x8 // The initial credit in the packet start message to the TCM interface (message to STORM…
43279 …/Access:RW DataWidth:0x8 // The initial credit for the search message to the CCFC interface. …
43280 …/Access:RW DataWidth:0x2 // The initial credit for the search message to the TCFC interface. …
43291 …e counter in the BRB Interface Unit that keeps track of the number of SOP requests sent to the BRB.
43292 …e counter in the BRB Interface Unit that keeps track of the number of EOP requests sent to the BRB.
43293 …ss:RW DataWidth:0x8 // The initial credit in the packet start message to the RGFS interface. …
43300 … 0x1f0f80UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST …
43302 …sed to select the BIST status word to read following the completion of a BIST test. Also used to s…
43303 … 0x1f0f8cUL //Access:R DataWidth:0x20 // Provides read-only access to the BIST stat…
43307 …to set the values of the GFT profile mask ram. line #31 must be configured before enabling the GFT…
43309 …to set the values of the GFT profile cam: 0 �valid, zero at reset 1-14 data 14-11 PF ID (3bit BB 4…
43324 …W DataWidth:0x1 // used to build the priority field in the GFT used frame fields inner header…
43325 …W DataWidth:0x1 // used to build the priority field in the GFT used frame fields tunnel heade…
43326 … 0x1f11bcUL //Access:RW DataWidth:0x1 // Per-PF: Enables gft searc…
43327 … 0x1f11c0UL //Access:RW DataWidth:0x1 // Per-PF: Enables gft search for non-IP pac…
43328 …type for gft, if the connection type returned in the search response equal to this value, use the …
43332 …pe . Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43334 … (0x3<<18) // Affinity type to be used in the CM he…
43336 … 0x1f11ccUL //Access:RW DataWidth:0x1 // When set to 1 the gft cam hit pa…
43337 … 0x1f11d0UL //Access:RW DataWidth:0x1 // When set to 1 the gft cam miss p…
43338 …0x1f1400UL //Access:RW DataWidth:0x1 // compare the GRE version field to the gre_version regi…
43339 …0x1f1404UL //Access:RW DataWidth:0x3 // compare the GRE version field to gre_version register…
43340 … 0x1f1408UL //Access:RW DataWidth:0x14 // mpls_ipv4_label to be compared Vs the l…
43341 … 0x1f140cUL //Access:RW DataWidth:0x14 // mpls_ipv6_label to be compared Vs the l…
43342 …1f1410UL //Access:RW DataWidth:0x1 // mpls_ipv6_label/mpls_ipv4_label to be compared Vs the l…
43453 … 0x1f0144UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43454 … 0x1f158cUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43455 … 0x1f0148UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43456 … 0x1f1590UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43457 … 0x1f014cUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43458 … 0x1f1594UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43459 … 0x1f0150UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43460 … 0x1f1598UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43461 … 0x1f0154UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43462 … 0x1f159cUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43463 … 0x1f0158UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43464 … 0x1f15a0UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43465 … 0x1f015cUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43466 … 0x1f15a4UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43467 … 0x1f0160UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43468 … 0x1f15a8UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43469 … 0x1f15acUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43470 … 0x1f15b0UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43471 … 0x1f15b4UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43472 … 0x1f15b8UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43473 … 0x1f15bcUL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43474 … 0x1f15c0UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43475 … 0x1f15c4UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43476 … 0x1f15c8UL //Access:RW DataWidth:0x8 // The increment value to send in the CCFC loa…
43481 …e 0. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43483 … (0x3<<18) // Affinity type to be used in the CM he…
43489 …e 1. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43491 … (0x3<<18) // Affinity type to be used in the CM he…
43497 …e 2. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43499 … (0x3<<18) // Affinity type to be used in the CM he…
43505 …e 3. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43507 … (0x3<<18) // Affinity type to be used in the CM he…
43513 …e 4. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43515 … (0x3<<18) // Affinity type to be used in the CM he…
43521 …e 5. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43523 … (0x3<<18) // Affinity type to be used in the CM he…
43529 …e 6. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43531 … (0x3<<18) // Affinity type to be used in the CM he…
43537 …e 7. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43539 … (0x3<<18) // Affinity type to be used in the CM he…
43544 …e 8. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43546 … (0x3<<18) // Affinity type to be used in the CM he…
43551 …e 9. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43553 … (0x3<<18) // Affinity type to be used in the CM he…
43558 … 10. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43560 … (0x3<<18) // Affinity type to be used in the CM he…
43565 … 11. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43567 … (0x3<<18) // Affinity type to be used in the CM he…
43572 … 12. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43574 … (0x3<<18) // Affinity type to be used in the CM he…
43579 … 13. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43581 … (0x3<<18) // Affinity type to be used in the CM he…
43586 … 14. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43588 … (0x3<<18) // Affinity type to be used in the CM he…
43593 … 15. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43595 … (0x3<<18) // Affinity type to be used in the CM he…
43597 … list of building blocks in TSTORM message for connection type 0. Unused blocks must be set to 0xf.
43598 …ed list of building blocks in PTLD message for connection type 0. Unused blocks must be set to 0xf.
43599 … list of building blocks in TSTORM message for connection type 0. Unused blocks must be set to 0xf.
43600 …ed list of building blocks in PTLD message for connection type 0. Unused blocks must be set to 0xf.
43601 … list of building blocks in TSTORM message for connection type 1. Unused blocks must be set to 0xf.
43602 …ed list of building blocks in PTLD message for connection type 1. Unused blocks must be set to 0xf.
43603 … list of building blocks in TSTORM message for connection type 1. Unused blocks must be set to 0xf.
43604 …ed list of building blocks in PTLD message for connection type 1. Unused blocks must be set to 0xf.
43605 … list of building blocks in TSTORM message for connection type 2. Unused blocks must be set to 0xf.
43606 …ed list of building blocks in PTLD message for connection type 2. Unused blocks must be set to 0xf.
43607 … list of building blocks in TSTORM message for connection type 2. Unused blocks must be set to 0xf.
43608 …ed list of building blocks in PTLD message for connection type 2. Unused blocks must be set to 0xf.
43609 … list of building blocks in TSTORM message for connection type 3. Unused blocks must be set to 0xf.
43610 …ed list of building blocks in PTLD message for connection type 3. Unused blocks must be set to 0xf.
43611 … list of building blocks in TSTORM message for connection type 3. Unused blocks must be set to 0xf.
43612 …ed list of building blocks in PTLD message for connection type 3. Unused blocks must be set to 0xf.
43613 … list of building blocks in TSTORM message for connection type 4. Unused blocks must be set to 0xf.
43614 …ed list of building blocks in PTLD message for connection type 4. Unused blocks must be set to 0xf.
43615 … list of building blocks in TSTORM message for connection type 4. Unused blocks must be set to 0xf.
43616 …ed list of building blocks in PTLD message for connection type 4. Unused blocks must be set to 0xf.
43617 … list of building blocks in TSTORM message for connection type 5. Unused blocks must be set to 0xf.
43618 …ed list of building blocks in PTLD message for connection type 5. Unused blocks must be set to 0xf.
43619 … list of building blocks in TSTORM message for connection type 5. Unused blocks must be set to 0xf.
43620 …ed list of building blocks in PTLD message for connection type 5. Unused blocks must be set to 0xf.
43621 … list of building blocks in TSTORM message for connection type 6. Unused blocks must be set to 0xf.
43622 …ed list of building blocks in PTLD message for connection type 6. Unused blocks must be set to 0xf.
43623 … list of building blocks in TSTORM message for connection type 6. Unused blocks must be set to 0xf.
43624 …ed list of building blocks in PTLD message for connection type 6. Unused blocks must be set to 0xf.
43625 … list of building blocks in TSTORM message for connection type 7. Unused blocks must be set to 0xf.
43626 …ed list of building blocks in PTLD message for connection type 7. Unused blocks must be set to 0xf.
43627 … list of building blocks in TSTORM message for connection type 7. Unused blocks must be set to 0xf.
43628 …ed list of building blocks in PTLD message for connection type 7. Unused blocks must be set to 0xf.
43629 …ed list of building blocks in PTLD message for connection type 8. Unused blocks must be set to 0xf.
43630 …ed list of building blocks in PTLD message for connection type 8. Unused blocks must be set to 0xf.
43631 …ed list of building blocks in PTLD message for connection type 9. Unused blocks must be set to 0xf.
43632 …ed list of building blocks in PTLD message for connection type 9. Unused blocks must be set to 0xf.
43633 …d list of building blocks in PTLD message for connection type 10. Unused blocks must be set to 0xf.
43634 …d list of building blocks in PTLD message for connection type 10. Unused blocks must be set to 0xf.
43635 …d list of building blocks in PTLD message for connection type 11. Unused blocks must be set to 0xf.
43636 …d list of building blocks in PTLD message for connection type 11. Unused blocks must be set to 0xf.
43637 …d list of building blocks in PTLD message for connection type 12. Unused blocks must be set to 0xf.
43638 …d list of building blocks in PTLD message for connection type 12. Unused blocks must be set to 0xf.
43639 …d list of building blocks in PTLD message for connection type 13. Unused blocks must be set to 0xf.
43640 …d list of building blocks in PTLD message for connection type 13. Unused blocks must be set to 0xf.
43641 …d list of building blocks in PTLD message for connection type 14. Unused blocks must be set to 0xf.
43642 …d list of building blocks in PTLD message for connection type 14. Unused blocks must be set to 0xf.
43643 …d list of building blocks in PTLD message for connection type 15. Unused blocks must be set to 0xf.
43644 …d list of building blocks in PTLD message for connection type 15. Unused blocks must be set to 0xf.
43648 …der. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43650 … (0x3<<18) // Affinity type to be used in the CM he…
43652 … (0x1<<20) // en_l2_ma to be used in storm con…
43654 … (0x3<<21) // l2_ma_config to be used in storm con…
43656 … (0x1<<23) // inc_sn to be used in storm con…
43661 …der. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43663 … (0x3<<18) // Affinity type to be used in the CM he…
43665 … (0x1<<20) // en_l2_ma to be used in storm con…
43667 … (0x3<<21) // l2_ma_config to be used in storm con…
43669 … (0x1<<23) // inc_sn to be used in storm con…
43674 …der. Used in packet start message to TCM. 9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6…
43676 … (0x3<<18) // Affinity type to be used in the CM he…
43678 … (0x1<<20) // en_l2_ma to be used in storm con…
43680 … (0x3<<21) // l2_ma_config to be used in storm con…
43682 … (0x1<<23) // inc_sn to be used in storm con…
43685 … 0x1f169cUL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on TCP 4 tuple. 0- p…
43686 … 0x1f16a0UL //Access:RW DataWidth:0x1 // 1- perform L2 CRC hash on UDP 4 tuple. 0- p…
43706 …urst mode enabled. Set this bits to have the main round-robin arbiter stays on the winning input …
43707 … 0x1f16f4UL //Access:RW DataWidth:0x1 // enable event_id to be set as ipv6_ext_e…
43713 … Local loopback from TX to RX. This loopback is on the line side after clock domain crossing - fro…
43715 …Local loopback from TX to RX. This loopback is on the core side before clock domain crossing - fro…
43717 …emote loopback from RX to TX. This loopback is on the line side before clock domain crossing - fro…
43719 …Remote loopback from RX to TX. This loopback is on the core side after clock domain crossing - fro…
43723 … (0x1<<7) // Enables SOP; SOM & Sequence alignment to 8 byte boundaries; a…
43725 …ing either of the local loopback modes; the transmit packets are also sent to the TX Warpcore inte…
43727 …ng either of the remote loopback modes; the received packets are also sent to the RX Port interfac…
43729 … (0x1<<10) // Resets the RS layer functionality - fault handling.
43731 …ide the one column idle/sequence ordered set check before SOP in XGMII mode - effectively supporti…
43733 …tware. If set; indicates that link is active. When this transitions from 0 to 1; EEE FSM waits for…
43735 … (0x1<<13) // This is the link status mux select signal to choose between link …
43751 … (0x1<<3) // Don't force the first byte of a packet to be /Start.
43753 … (0x1<<4) // Enable XMAC to pad runt packets on …
43755 … (0x7f<<5) // If padding is enabled; packets less than this size are padded to get to this size.
43761 …wer 8 bits of throt_denom register. Number of bytes to transmite before adding txThrotNumer bytes …
43764 …per 8 bits of throt_denom register. Number of bytes to transmite before adding txThrotNumer bytes …
43768 …packet; before starting transmission of the packet on the line side; helps to prevent underflow is…
43773 … (0x1<<0) // Mac Control packets are passed to the system.
43775 … (0x1<<1) // True to allow any non-Idle character to star…
43779 …the MAC checks for IEEE Ethernet format premable - K.SOP + 5 '55' premable bytes + 'D5' SFD charac…
43783 …1) // If set; the minimum receive packet size is reduced to 18 bytes from the default 33 bytes - S…
43785 … (0x1<<12) // If set; the MAC parses the frame from K.SOP onwards to look for the SFD cha…
43787 … bits of rx_sa register. SA recognized for MAC control packets in addition to the standard 0x0180C…
43788 … bits of rx_sa register. SA recognized for MAC control packets in addition to the standard 0x0180C…
43801 …to disable enable processing of LSS message type: Local Fault. When clear and a local fault LSS me…
43803 …to disable processing of LSS message type: Remote Fault. When clear and a remote fault LSS message…
43805 …<<2) // If set; the TX faults inputs are used to send out fault sequences - else receive faults ar…
43807 …to disable processing of LSS message type: Link Interruption. When clear and a Link Interruption L…
43825 … (0x1<<0) // A rising edge on this register bit (0->1); clears the stick…
43827 … (0x1<<1) // A rising edge on this register bit (0->1); clears the stick…
43829 … (0x1<<2) // A rising edge on this register bit (0->1); clears the stick…
43832 …0xffff<<0) // This field is Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-…
43840 … (0x1<<19) // Send PAUSE frames to the system side.
43842 …0x1<<20) // If set; the recive pause is used to stop the frame transmission in the GMII convertor …
43844 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43846 …use_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
43848 … (0xffff<<0) // Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-…
43850 …xffff<<16) // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
43853 … (0x1<<0) // Enable automatic re-send of PFC packet af…
43855 … (0x1<<1) // Instructs the MAC to send XON for all Cla…
43857 … (0x1<<2) // Set to pass RX PFC frame to core I/F.
43859 … (0x1<<3) // Set to enable incrementing …
43876 … (0x1<<3) // When set and llfc_in_ipg_only =0; GXPORT operates in cut-through mode.
43878 … (0x1<<4) // This bit if set to 1; disables the crc …
43892 …ICAL_BB (0xff<<0) // Value used to decode dw0_byte1 of …
43894 …CAL_BB (0xf<<8) // Value used to decode dw1_byte0 of …
43896 …ICAL_BB (0xff<<12) // Value used to decode dw0_byte1 of …
43898 …CAL_BB (0xf<<20) // Value used to decode dw1_byte0 of …
43931 … (0x1<<0) // A rising edge on this register bit (0->1); clears the stick…
43933 … (0x1<<1) // A rising edge on this register bit (0->1); clears the stick…
43935 … (0x1<<2) // A rising edge on this register bit (0->1); clears the stick…
43937 … (0x1<<3) // A rising edge on this register bit (0->1); clears the stick…
43939 … (0x1<<4) // A rising edge on this register bit (0->1); clears the stick…
43941 … (0x1<<5) // A rising edge on this register bit (0->1); clears the stick…
43943 … (0x1<<6) // A rising edge on this register bit (0->1); clears the stick…
43955 … (0x1<<1) // If set; EEE FSM can go to EMPTY state even whe…
43957 … (0x1<<2) // If set; EEE FSM can go to EMPTY state even whe…
43959 … (0x1<<3) // If set; EEE FSM can go to EMPTY state even whe…
43961 … is the duration for which condition to move to LPI state must be satisfied; at the end of which M…
43963 … (0xffff<<0) // This is the duration for which MAC must wait to go back to ACTIVE state f…
43965 … (0xffff<<16) // This field controls clock divider used to generate ~1us refere…
43967 …us becomes active before transitioning to ACTIVE state. This is in terms of micro seconds. Default…
43969 …his register defines the number of IDLEs to be received by GMII interface before allowing LP_IDLE …
43971 … (0x1<<16) // When set to 1; enables LP_IDLE Prediction. When set t…
43973 … (0x1<<17) // When set to 1; GMII interface will shut down TXCLK to…
43982 … 32 bits of macsec_prog_tx_crc register. Programmable CRC value to corrupt the Tx CRC to be used i…
43984 … 32 bits of macsec_prog_tx_crc register. Programmable CRC value to corrupt the Tx CRC to be used i…
43985 … 0x210130UL //Access:RW DataWidth:0x10 // XMAC IP Version ID - corresponds to RTL/DV label.
44005 … (0x3<<1) // 00: Map to NWM port 0 01: Map to NWM port 1 10: Map to NWM por…
44007 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44009 … datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
44017 …bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is int…
44019 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44025 … (0x3<<1) // 00: Map to NWM port 0 01: Map to NWM port 1 10: Map to NWM por…
44027 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44029 … datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
44037 …bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is int…
44039 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44041 …x25 SERDES connects to Engine 0 and 4x10 SERDES connects to Engine 1 1 : 4x25 SERDES connects to E…
44045 … (0x3<<1) // 00: Map to NWM port 0 01: Map to NWM port 1 10: Map to NWM por…
44047 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44049 … datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
44057 …bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is int…
44059 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44064 … (0x1<<1) // Setting this bit to 1 tells the interfac…
44068 …xt 64 bit register will be at addr+1. This register allows HW to automatically increment to a prog…
44070 … (0xff<<8) // Byte Count of the transaction. Limit to 32bytes.
44077 … (0x3<<1) // 00: Map to NWM port 0 01: Map to NWM port 1 10: Map to NWM por…
44079 … (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
44081 … datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
44089 …bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is int…
44091 …bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels,…
44101 …1<<0) // This regiseter enables loopback mode (used for debug) 0 - loopback inactive 1 - loopback …
44107 … (0x1<<0) // Set to 1 for masking invlai…
44109 … (0x1<<1) // Set to 1 for masking crc er…
44111 … (0x1<<2) // Set to 1 for masking decodi…
44113 …5 (0x1<<3) // Set to 1 for masking fifo o…
44115 … (0x1<<4) // Set to 1 for masking remote…
44117 … (0x1<<5) // Set to 1 for masking vlan t…
44119 …T_K2_E5 (0x1<<6) // Set to 1 for masking vlan t…
44121 …2_E5 (0x1<<7) // Set to 1 for masking vlan e…
44123 …rite Data. This should be the last item written for a transaction. Writing to this register will k…
44126 … (0x1<<0) // Signals an unknown address to the rf module.
44180 … (0x1<<1) // Setting this bit to 1 tells the interfac…
44184 …xt 64 bit register will be at addr+1. This register allows HW to automatically increment to a prog…
44186 … (0xff<<8) // Byte Count of the transaction. Limit to 32bytes.
44192 … (0x1<<0) // Signals an unknown address to the rf module.
44225 … (0x1<<0) // Signals an unknown address to the rf module.
44250 …is register is used to set the value of NWM lpi_indicate default value. The lpi value will be over…
44251 …rite Data. This should be the last item written for a transaction. Writing to this register will k…
44268 … (0x1<<12) // This bit is set to enable the use of th…
44270 …n + off) for Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field is reset to …
44272 … 0x218240UL //Access:RW DataWidth:0x8 // This register enable to read and write the c…
44274 … // Led mode: 0 -> MAC; 1-3 -> PHY1; 4 -> MAC2; 5-7 -> PHY4; 8 -> MAC3; 9 -…
44275 …-> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused A …
44276 …-> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused A …
44277 …-> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused A …
44280 …de [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> un…
44281 … 0x218254UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
44283 …to Network Port 0, PF1 to NW1 and so on. However, there are cases when the PF and NW conenctions a…
44285 …Port 1 to the corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1…
44287 …Port 2 to the corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1…
44289 …Port 2 to the corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1…
44291 … line) in the selected line (before shift).for selecting a line to output
44292 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44294 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44296 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44298 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44299 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44300 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44301 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44302 …taWidth:0x8 // LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] ->…
44303 …h:0x1 // When set, PMIF block uses values in following registers to configure NIG - PM interface
44304 …/ These bits are used to set which NIG Ports are used with the PM4x10. A 1'b0 in these bits indica…
44307 …its are used to define which NIG port is assigned to each PMEG Port. [1:0] -- PMEG Port 0 [3:2] --…
44308 …its are used to define which NIG port is assigned to each PMFC Port. [1:0] -- PMFC Port 0 [3:2] --…
44309 …to set the number of active ports on PMEG. The value in this register is added to the PMEG Port ID…
44310 …to set the number of active ports on PMFC. The value in this register is added to the PMFC Port ID…
44311 …s. When this threshold is reached, the backpressure signal will be sent to NIG to stop transmittin…
44312 …the Threshold level for Tx Credits from the 4x10 PM. Data will not be sent to the PM unless the cu…
44313 …the Threshold level for Tx Credits from the 1x40 PM. Data will not be sent to the PM unless the cu…
44314 …r bits from the PMFC Rx FIFO (bit [4]) and the NIG Tx FIFOs (bits [3:0]). To clear these bits, th…
44363 …ter value represent the number of FIFO entries before almost full indication is transferred to NIG.
44364 …0UL //Access:RW DataWidth:0x6 // Per Eagle port credit RD/WR: Writing to this register will i…
44366 …UL //Access:RW DataWidth:0x6 // Per Falcon port credit RD/WR: Writing to this register will i…
44368 … 0x218320UL //Access:RW DataWidth:0x1 // This register is used to set the value of cni…
44369 … 0x218324UL //Access:RW DataWidth:0x1 // This register is used to set the value of cni…
44370 …is register is used to set the value of PMFC lpi_indicate default value. The lpi value will be ove…
44371 …is register is used to set the value of PMEG lpi_indicate default value. The lpi value will be ove…
44374 …to CRC correctness. Note: this mode can be active only for PMFC ports 0,2 and should be used for 1…
44375 …ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 C…
44376 …pted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - por…
44377 …pted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - por…
44378 … 0x230000UL //Access:RW DataWidth:0x1 // Used to disable the PRM from…
44379 … 0x230004UL //Access:RW DataWidth:0x1 // Enables data to be received on the B…
44380 … 0x230008UL //Access:RW DataWidth:0x1 // Enables the BRB full output to be asserted by the P…
44381 …0cUL //Access:RW DataWidth:0x1 // Enables the PXP request acknowledge to be received by the P…
44382 … 0x230010UL //Access:RW DataWidth:0x1 // Used to disable all PRM bloc…
44383 … 0x230014UL //Access:RW DataWidth:0x1 // Used to disable all PRM bloc…
44385 … (0x1<<0) // Signals an unknown address to the rf module.
44399 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44401 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44403 … (0x1<<7) // End of packet error on M-Storm command interfa…
44405 … (0x1<<8) // End of packet error on U-Storm command interfa…
44431 … (0x1<<0) // Signals an unknown address to the rf module.
44445 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44447 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44449 … (0x1<<7) // End of packet error on M-Storm command interfa…
44451 … (0x1<<8) // End of packet error on U-Storm command interfa…
44454 … (0x1<<0) // Signals an unknown address to the rf module.
44468 … (0x1<<9) // FIFO overflow/underflow error on M-Storm command interfa…
44470 … (0x1<<10) // FIFO overflow/underflow error on U-Storm command interfa…
44472 … (0x1<<7) // End of packet error on M-Storm command interfa…
44474 … (0x1<<8) // End of packet error on U-Storm command interfa…
44604 …0210UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
44605 …0210UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
44606 …0214UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
44607 …0214UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
44608 …0218UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
44609 …0218UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
44668 …ble seven configurable L2 tags to remove, where the direct register index corresponds with the tag…
44670 … 0x230420UL //Access:RW DataWidth:0x10 // Provides the value of the 16-bit pad that will be …
44671 …/ When set, this bit enables the pad insertion logic to use BRB debug field from the PRM command t…
44672 … 0x230428UL //Access:RW DataWidth:0x3 // Initial credit to be used on the PXP r…
44673 …cess:RW DataWidth:0x7 // Initial credit to be used on the RDIF command interface for regular …
44674 …itial credit to be used on the RDIF command interface for pass-through requests. This value define…
44678 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
44679 …th:0x9 // Defines the number of occupied entries required in the PXP read-response FIFO before …
44680 … DataWidth:0x20 // Statistics counter provides a count of the number of M-Storm comands that ha…
44681 … DataWidth:0x20 // Statistics counter provides a count of the number of U-Storm comands that ha…
44705 … 0x2306a8UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
44706 … line) in the selected line (before shift).for selecting a line to output
44710 … 0x232000UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the M-Storm comma…
44712 … 0x232400UL //Access:WB_R DataWidth:0x80 // Provides read-only access of the U-Storm comma…
44714 … 0x232800UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the BR…
44716 … 0x232c00UL //Access:R DataWidth:0x7 // Provides read-only access of the BR…
44718 … 0x233000UL //Access:WB_R DataWidth:0x2c // Provides read-only access of the ta…
44720 … 0x233400UL //Access:R DataWidth:0x11 // Provides read-only access of the pa…
44722 … 0x233600UL //Access:R DataWidth:0xb // Provides read-only access of the PB…
44724 … 0x233800UL //Access:WB_R DataWidth:0x100 // Provides read-only access of the PR…
44726 … 0x233c00UL //Access:R DataWidth:0x8 // Provides read-only access of the PXP write-done re…
44728 …to the PRM completion message queue. Intended for test/debug purposes. When the RBC read is done a…
44732 … (0xff<<0) // Number of Concurrent Processes (State Machines); Values can be 1 to 25.
44734 … (0xff<<8) // The maximum allowed HOP to search.
44751 … (0x1<<0) // Signals an unknown address to the rf module.
44754 … (0x1<<0) // Signals an unknown address to the rf module.
44757 … (0x1<<0) // Signals an unknown address to the rf module.
44773 … 0x238480UL //Access:RW DataWidth:0x10 // Per-PF Bitmask for inclus…
44774 … 0x238484UL //Access:RW DataWidth:0x8 // Per-StringType Bitmask fo…
44775 … this bit is set. This bit is cleared when any IF Stat Counter is read to ensure coherency. …
44798 …ss:RW DataWidth:0x5 // The number of hash bits used for the search (h); Values can be 8 to 24.
44801 … 0x238700UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
44802 … line) in the selected line (before shift).for selecting a line to output
44812 …ss:RW DataWidth:0x1 // Write to this register will initialize all rows of RSS memory to zeros…
44828 … (0x1<<0) // Signals an unknown address to the rf module.
44862 … (0x1<<2) // Number of cycles in CM message to TM loader is 63.
44918 … (0x1<<0) // Signals an unknown address to the rf module.
44952 … (0x1<<2) // Number of cycles in CM message to TM loader is 63.
44963 … (0x1<<0) // Signals an unknown address to the rf module.
44997 … (0x1<<2) // Number of cycles in CM message to TM loader is 63.
45069 …c04UL //Access:RW DataWidth:0x6 // Number of credits on RSS interface to TMLD. Maximal suppor…
45070 …RAM bit enable. It will be used for write operation from RBC. If it equals to 1 then rss_ram_data …
45072 …to this register will generate read or write transaction to RSS memory. Write data in this registe…
45074 …to RSS indirection memory. If bits 12:10 are 0 then bits 6:0 is addr to RSS CID table. If bits 12:…
45076 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45077 … // Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP…
45078 …0x20 // Debug register. FIFO empty status: {b15:8 - inp_fifo_counter; b7:6- cmd_fifo_couter; b5:…
45079 …ster. State of each state machine {b15:12 - calc_cur_state; b11:8 - main_cur_state;b7:4 - msg_cur_…
45081 … 0x238c4cUL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
45082 … line) in the selected line (before shift).for selecting a line to output
45090 … 0x238c88UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
45091 … 0x238c8cUL //Access:RW DataWidth:0x8 // command to CPU BIST
45092 … 0x238c90UL //Access:RW DataWidth:0x8 // address to CPU BIST
45189 … (0x1<<0) // Signals an unknown address to the rf module.
45227 … (0x1<<0) // Signals an unknown address to the rf module.
45246 … (0x1<<0) // Signals an unknown address to the rf module.
45268 … (0x1<<0) // Indicates if to switch the CRC resul…
45270 … (0x1<<1) // Indicates if to ignore the input err…
45276 …machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
45310 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the instruction…
45311 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the lower 32 bi…
45312 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the upper 32 bi…
45313 …debug register. This register provides the number of data bytes remaining to be read from DB at t…
45319 … 0x23c728UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
45320 … line) in the selected line (before shift).for selecting a line to output
45324 … 0x23e000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
45328 …s:RW DataWidth:0x1 // Driver should write 1 to this register in order to signal the PSWRQ blo…
45329 …ion is done. Driver should check this register is 1 some time after writing 1 to rbc_done register.
45330 …0x240008UL //Access:RW DataWidth:0x1 // MCP writes '1' to this bit to indicate PSWRQ to initi…
45331 …x4 // Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-51…
45332 … // Page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45333 …4 // Page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45334 …4 // Page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45335 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45336 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45337 … // Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45338 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45339 … // Page size in L2P table for dbg module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
45346 … 0x240048UL //Access:RW DataWidth:0xe // First memory address base for cdu-connection in ILT.
45347 … 0x24004cUL //Access:RW DataWidth:0xe // Last memory address base for cdu-connection in ILT.
45348 … 0x240050UL //Access:RW DataWidth:0xe // First memory address base for cdu-task in ILT.
45349 … 0x240054UL //Access:RW DataWidth:0xe // Last memory address base for cdu-task in ILT.
45373 … 0x2400b4UL //Access:RW DataWidth:0x8 // First VF assigned to this PF. Used for IL…
45377 … 0x240100UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
45378 … line) in the selected line (before shift).for selecting a line to output
45385 … (0x1<<0) // Signals an unknown address to the rf module.
45387 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45391 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45393 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45395 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45397 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45403 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45405 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45407 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45409 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45411 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45413 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45419 … (0x1<<17) // Client issue request to a VQID which is not mapped to it
45459 … (0x1<<0) // Signals an unknown address to the rf module.
45461 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45465 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45467 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45469 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45471 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45477 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45479 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45481 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45483 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45485 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45487 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45493 … (0x1<<17) // Client issue request to a VQID which is not mapped to it
45496 … (0x1<<0) // Signals an unknown address to the rf module.
45498 … (0x1<<1) // Overflow in l2p input fifo - removed in E4.
45502 … (0x1<<3) // Overflow of phy addr fifo - removed in E4.
45504 … (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4.
45506 … (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4.
45508 …tten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5.
45514 … (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5.
45516 … (0x1<<10) // Underflwoing the treq fifo - removed in E5.
45518 … (0x1<<11) // Overflwoing the treq fifo - removed in E5.
45520 … (0x1<<12) // Underflwoing the icpl fifo - removed in E5.
45522 … (0x1<<13) // Overflwoing the icpl fifo - removed in E5.
45524 … (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5.
45530 … (0x1<<17) // Client issue request to a VQID which is not mapped to it
45577 …0210UL //Access:W DataWidth:0xe // Register to generate up to two ECC errors on the next wri…
45578 …0210UL //Access:W DataWidth:0xe // Register to generate up to two ECC errors on the next wri…
45596 …0214UL //Access:W DataWidth:0xe // Register to generate up to two ECC errors on the next wri…
45634 …W DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010:…
45635 …RW DataWidth:0x3 // Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010:…
45638 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45639 …n a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B…
45640 … DataWidth:0x3 // This number indicates how many entries are guaranteed to usdm in the queues.
45641 …W DataWidth:0x3 // This number indicates how many entries are guaranteed to prm in the queues.
45642 … DataWidth:0x3 // This number indicates how many entries are guaranteed to tsdm in the queues.
45643 … DataWidth:0x3 // This number indicates how many entries are guaranteed to xsdm in the queues.
45644 …W DataWidth:0x3 // This number indicates how many entries are guaranteed to rwh in the queues.
45645 … DataWidth:0x3 // This number indicates how many entries are guaranteed to cduwr in the queues.
45646 … DataWidth:0x3 // This number indicates how many entries are guaranteed to cdurd in the queues.
45647 …W DataWidth:0x7 // This number indicates how many entries are guaranteed to pbf in the queues.
45648 …RW DataWidth:0x3 // This number indicates how many entries are guaranteed to qm in the queues.
45649 …RW DataWidth:0x3 // This number indicates how many entries are guaranteed to tm in the queues.
45650 …W DataWidth:0x3 // This number indicates how many entries are guaranteed to src in the queues.
45651 … DataWidth:0x3 // This number indicates how many entries are guaranteed to debug in the queues.
45652 …RW DataWidth:0x2 // This number indicates how many entries are guaranteed to hc in the queues.
45653 …DataWidth:0x8 // Initial value of global counter; This value MUST be 256 - sum of all clients t…
45765 … 0x24058cUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ0 read requests.
45766 … 0x24058cUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ0 write requests.
45768 … (0x3ff<<0) // Bandwidth addition to VQ1 read requests.
45770 … (0x3ff<<10) // Bandwidth addition to VQ1 write requests.
45773 … (0x3ff<<0) // Bandwidth addition to VQ2 read requests.
45775 … (0x3ff<<10) // Bandwidth addition to VQ2 write requests.
45778 … (0x3ff<<0) // Bandwidth addition to VQ3 read requests.
45780 … (0x3ff<<10) // Bandwidth addition to VQ3 write requests.
45782 … 0x24059cUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ4 read requests.
45783 … 0x24059cUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ4 read requests.
45784 … 0x2405a0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ5 read requests.
45785 … 0x2405a0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ5 read requests.
45787 … (0x3ff<<0) // Bandwidth addition to VQ6 read requests.
45789 … (0x3ff<<10) // Bandwidth addition to VQ6 write requests.
45792 … (0x3ff<<0) // Bandwidth addition to VQ7 read requests.
45794 … (0x3ff<<10) // Bandwidth addition to VQ7 write requests.
45797 … (0x3ff<<0) // Bandwidth addition to VQ8 read requests.
45799 … (0x3ff<<10) // Bandwidth addition to VQ8 write requests.
45802 … (0x3ff<<0) // Bandwidth addition to VQ9 read requests.
45804 … (0x3ff<<10) // Bandwidth addition to VQ9 write requests.
45807 … (0x3ff<<0) // Bandwidth addition to VQ10 read requests.
45809 … (0x3ff<<10) // Bandwidth addition to VQ10 write requests.
45812 … (0x3ff<<0) // Bandwidth addition to VQ11 read requests.
45814 … (0x3ff<<10) // Bandwidth addition to VQ11 write requests.
45816 … 0x2405bcUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ12 read requests.
45817 … 0x2405bcUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ12 read requests.
45818 … 0x2405c0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ13 read requests.
45819 … 0x2405c0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ13 read requests.
45821 … (0x3ff<<0) // Bandwidth addition to VQ14 read requests.
45823 … (0x3ff<<10) // Bandwidth addition to VQ14 write requests.
45825 … 0x2405c8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ15 read requests.
45826 … 0x2405c8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ15 read requests.
45827 … 0x2405ccUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ16 read requests.
45828 … 0x2405ccUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ16 read requests.
45829 … 0x2405d0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ17 read requests.
45830 … 0x2405d0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ17 read requests.
45831 … 0x2405d4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ18 read requests.
45832 … 0x2405d4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ18 read requests.
45833 … 0x2405d8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ19 read requests.
45834 … 0x2405d8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ19 read requests.
45836 … (0x3ff<<0) // Bandwidth addition to VQ20 read requests.
45838 … (0x3ff<<10) // Bandwidth addition to VQ20 write requests.
45840 … 0x2405dcUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ20 read requests.
45841 … 0x2405e0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ21 write requests.
45842 … 0x2405e0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ21 write requests.
45843 … 0x2405e4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ22 read requests.
45844 … 0x2405e4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ22 read requests.
45845 … 0x2405e8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ23 read requests.
45846 … 0x2405e8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ23 read requests.
45847 … 0x2405ecUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ24 read requests.
45848 … 0x2405ecUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ24 read requests.
45850 … (0x3ff<<0) // Bandwidth addition to VQ25 read requests.
45852 … (0x3ff<<10) // Bandwidth addition to VQ25 write requests.
45854 … 0x2405f0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ25 read requests.
45855 … 0x2405f4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ26 read requests.
45856 … 0x2405f4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ26 read requests.
45857 … 0x2405f8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ27 read requests.
45858 … 0x2405f8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ27 read requests.
45860 … (0x3ff<<0) // Bandwidth addition to VQ28 read requests.
45862 … (0x3ff<<10) // Bandwidth addition to VQ28 write requests.
45864 … 0x240600UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ29 write requests.
45865 … 0x240600UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ29 write requests.
45866 … 0x240604UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ30 write requests.
45867 … 0x240604UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ30 write requests.
45869 … (0x3ff<<0) // Bandwidth addition to VQ31 read requests.
45871 … (0x3ff<<10) // Bandwidth addition to VQ31 write requests.
46001 … 0x2406a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ5 Read- currently not used.
46104 … (0xf<<0) // Indicates the number of credits for read sub-requests in th reques…
46106 … (0x1f<<4) // Indicates the number of credits for write sub-requests in th reques…
46111 … 0x240724UL //Access:RW DataWidth:0x5 // Sets which vq head pointer to see out of queues 0-31.
46112 … 0x240728UL //Access:RW DataWidth:0x5 // Sets which vq tail pointer to see out of queues 0-31.
46140 … 0x240798UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ TREQ read request…
46141 … 0x24079cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound to VQ TREQ read request…
46142 … 0x2407a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L to VQ TREQ read request…
46143 … 0x2407a4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ ICPL write reques…
46144 … 0x2407a8UL //Access:RW DataWidth:0x9 // Bandwidth upper bound to VQ ICPL write reques…
46145 … 0x2407acUL //Access:RW DataWidth:0x9 // Bandwidth Typical L to VQ ICPL write reques…
46146 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46147 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46148 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46149 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46150 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46151 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46152 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46153 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46154 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46155 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46156 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46157 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46158 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46159 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46160 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46161 …- SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). W…
46162 …ss:RW DataWidth:0x2 // ATC enable values per PF as follows: b0 - PF enable; b1 - VF enable; P…
46163 …ues of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ;…
46164 …to the GLUE with the at_valid=1 indication (see atc_code in PSWRQ-PGLUE interface for more details…
46166 … 0x240800UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46167 …-s that are enabled (i.e. can be chosen by the GARB) in close the gates scenario; VQ32 = TREQ; VQ3…
46168 … 0x240808UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46169 …Q-s that are enabled (i.e. can be chosen by the GARB) in stall mem scenario; VQ32 = TREQ; VQ33 = I…
46170 … 0x240810UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i…
46171 …-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ33 = IC…
46175 …- assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail …
46176 …hoq ram; the write data represents the address which is the vqid; in order to read from the hoq ra…
46178 …- data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 data_rd2 and data_r…
46182 … //Access:R DataWidth:0x20 // FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 clien…
46183 …0844UL //Access:R DataWidth:0x20 // The total number of WR SR-s that were sent to the PGLUE. …
46184 …0848UL //Access:R DataWidth:0x20 // The total number of RD SR-s that were sent to the PGLUE. …
46185 …24084cUL //Access:R DataWidth:0x20 // The number of PBF RD SR-s that were sent to the PGLUE. …
46186 …x240850UL //Access:R DataWidth:0x20 // The number of USDM-DP WR SR-s that were sent to the PG…
46187 …0x240854UL //Access:R DataWidth:0x20 // The number of TREQ SR-s that were sent to the PGLUE. …
46188 …0x240858UL //Access:R DataWidth:0x20 // The number of ICPL SR-s that were sent to the PGLUE. …
46189 …20 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46190 …9 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46191 …20 // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46192 …c // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46193 …0x20 // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46194 …0xc // The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_statu…
46195 …:0x20 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46196 …:0x9 // The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_…
46197 …de. 0 - manual window: counting is manually being initiated & stopped by the user through GRC. 1 -…
46199 …he beginning of counting. NOTE: beginning of counting is determined according to Sr_cnt_start_mode.
46200 …en working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - stop counting. 1 - start count…
46201 … write command to this reg (any value) will reset the SR counters & the global window counter. In …
46202 …ow counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start counting up…
46205 …atus of the SR count mechanism: 0 - idle: ready to start new counting. 1 - ongoing: counting is cu…
46206 … 0x2408a0UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46207 … 0x2408a4UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46208 … 0x2408a8UL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46209 …dth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client …
46210 … 0x2408b0UL //Access:R DataWidth:0x9 // bit 8-0: srid.
46211 … 0x2408b4UL //Access:R DataWidth:0x20 // SR address - 32 lsb.
46212 … 0x2408b8UL //Access:R DataWidth:0x20 // SR address - 32 msb.
46213 … 0x2408bcUL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b…
46214 … DataWidth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15…
46215 … 0x2408c4UL //Access:R DataWidth:0xa // b1-0: atc code; b2: wdone type; b4-3: endianity; …
46216 … DataWidth:0x3 // This number indicates how many entries are guaranteed to msdm in the queues.
46217 … DataWidth:0x3 // This number indicates how many entries are guaranteed to ysdm in the queues.
46218 … DataWidth:0x3 // This number indicates how many entries are guaranteed to psdm in the queues.
46219 … DataWidth:0x3 // This number indicates how many entries are guaranteed to muld in the queues.
46220 …W DataWidth:0x3 // This number indicates how many entries are guaranteed to ptu in the queues.
46226 …W DataWidth:0x3 // This number indicates how many entries are guaranteed to m2p in the queues.
46237 … DataWidth:0x3 // This number indicates how many entries are guaranteed to xyld in the queues.
46243 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46244 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46245 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46246 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46247 …x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuratio…
46248 …//Access:RW DataWidth:0x1 // Debug only. Writing this register from 0 to 1 enables the roundt…
46255 …ss:RW DataWidth:0x2 // In case this register is set, requests belongs to VFs/PF with logic ad…
46258 …l2p_vf_err or rq_elt_addr interrupt. [12:0] - Length in bytes. [16:13] - PFID. [17] - VF_VALID. …
46259 …- Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. [22] - w_nr - 0 - read; 1 - write.[27:23]VQID. …
46260 … 0x240938UL //Access:W DataWidth:0x1 // Writing to this register clears…
46261 …:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be big…
46263 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46264 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46265 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46266 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46267 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46268 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46269 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46270 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46271 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46272 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46273 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46274 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46275 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46276 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46277 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46278 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46279 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46280 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46281 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46282 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46283 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46284 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46285 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46286 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46287 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46288 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46289 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46290 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46291 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46294 …allocated for this vq. Field and register name used to be rd. need to update reset value for phase…
46295 …Width:0x9 // Debug only: The SR counter - number of unused sub request ids. Field and register …
46328 …idth:0xa // Debug only: The blocks counter - number of unused block ids. Field and register nam…
46391 … 0x240b44UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46392 … 0x240b48UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46393 … 0x240b4cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46394 … 0x240b50UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46395 … 0x240b54UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46396 … 0x240b58UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46397 … 0x240b5cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46398 … 0x240b60UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46399 … 0x240b64UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46400 … 0x240b68UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46401 … 0x240b6cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46402 … 0x240b70UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46403 … 0x240b74UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46404 … 0x240b78UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46405 … 0x240b7cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46406 … 0x240b80UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46407 … 0x240b84UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46408 … 0x240b88UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46409 … 0x240b8cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46410 … 0x240b90UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46411 … 0x240b94UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46412 … 0x240b98UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46413 … 0x240b9cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46414 … 0x240ba0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46415 … 0x240ba4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46416 … 0x240ba8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46417 … 0x240bacUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46418 … 0x240bb0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46419 … 0x240bb4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46420 … 0x240bb8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46421 … 0x240bbcUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46422 … 0x240bc0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be …
46429 …reater or equal to Li are chosen. 0 indicates that clients with BWC greater or equal to 0 can be c…
46430 …to strict priority: 0 - the VQ is not associated with any strict priority (i.e. the VQ is associat…
46431 …to strict priority: 0 - the VQ is not associated with any strict priority (i.e. the VQ is associat…
46432 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46433 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46434 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46435 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46436 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46437 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46438 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46439 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46440 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46441 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46442 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46443 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46444 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46445 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46446 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46447 …to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated wi…
46448 …-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be s…
46449 …-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sen…
46450 …nable to submit a write request when eop arrived. This can be a workaround for possible bugs in th…
46451 …-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head …
46452 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46453 …-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_…
46454 … 0x240c40UL //Access:R DataWidth:0xe // For debug and Idle-check use. The value …
46455 …:0x6 // Will be used for OOO clients deadlock prevention. indicating if to submit the first SR …
46456 …to the PGLUE (i.e. sent to the PGLUE and did not receive write done for them from the PGLUE). Upon…
46491 …to this VQ. Map TSDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped…
46492 …to this VQ. Map MSDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped…
46493 …to this VQ. Map USDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped…
46494 …to this VQ. Map XSDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped…
46495 …to this VQ. Map YSDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped…
46496 …to this VQ. Map PSDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped…
46497 …to this VQ. Map M2P to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped …
46513 … // Page size in L2P table for tgsrc module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46514 … // Page size in L2P table for RGSRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M…
46552 …h:0x35 // Internal lookup table for logical to physical address translation. Re-instantiated in …
46558 … 0x280020UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
46559 … line) in the selected line (before shift).for selecting a line to output
46567 … (0x1<<0) // Signals an unknown address to the rf module.
46661 … (0x1<<0) // Signals an unknown address to the rf module.
46708 … (0x1<<0) // Signals an unknown address to the rf module.
46772 …to the incrementing client IDs of write clients: 0 - TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM;…
46773 …to the incrementing client IDs of write clients: 0 - TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM;…
46774 … 0x29a084UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
46775 … line) in the selected line (before shift).for selecting a line to output
46788 … (0x1<<0) // Signals an unknown address to the rf module.
46866 … (0x1<<0) // Signals an unknown address to the rf module.
46905 … (0x1<<0) // Signals an unknown address to the rf module.
46948 …- client ID. [7:5] - (sum1[5:3] + 1) or (sum1[5:4] + 1) according to the definition in the spec. […
46949 … 0x29b04cUL //Access:W DataWidth:0x1 // Writing to this register clears…
46956 …0x29b068UL //Access:RW DataWidth:0x7 // If Number of entries in the PRM-secondary internal fi…
46957 … 0x29b06cUL //Access:R DataWidth:0x7 // Current internal PRM-secondary fill level …
46958 … 0x29b070UL //Access:R DataWidth:0x7 // Maximum internal PRM-secondary fill level …
46960 … (0x1<<0) // Signals an unknown address to the rf module.
46996 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47050 … (0x1<<0) // Signals an unknown address to the rf module.
47086 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47095 … (0x1<<0) // Signals an unknown address to the rf module.
47131 … the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the…
47645 …b240UL //Access:W DataWidth:0x16 // Register to generate up to two ECC errors on the next wri…
47646 …b250UL //Access:W DataWidth:0x16 // Register to generate up to two ECC errors on the next wri…
47647 …b254UL //Access:W DataWidth:0x16 // Register to generate up to two ECC errors on the next wri…
47674 … 0x29c040UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
47675 … line) in the selected line (before shift).for selecting a line to output
47684 …ndicates if full is asserted by the client. The clients order is according to the incrementing cli…
47685 …ull was asserted since reset by the client. The clients order is according to the incrementing cli…
47687 … (0x1<<0) // Signals an unknown address to the rf module.
47701 … (0x1<<0) // Signals an unknown address to the rf module.
47708 … (0x1<<0) // Signals an unknown address to the rf module.
47717 …s:RW DataWidth:0x1 // Driver should write 1 to this register in order to signal the PSWRD blo…
47718 …n is done. Driver should check this register is 1 some time after writing 1 to start_init register.
47719 …ue is the one expected in idle check except for the Timers VQ (VQ3). This register is for VQs 0-23.
47723 …tern that should override the data in case of an error. Duplicated 4 times to create 64 bit data. …
47725 …to override the data to the client in case of an error and use the error pattern. 0 indicates not …
47727 …to override the data to the client in case of an error only in the last request cycle. 0 indicates…
47729 …uest with error on receive side: [15:0] - Echo ID. [28:16] - sub-request length minus 1. [29] - fi…
47730 …ils of first request with error on receive side: [4:0] - VQ ID. [9:5] - client ID. [10] - valid - …
47731 … 0x29d070UL //Access:W DataWidth:0x1 // Writing to this register clears…
47737 …e is the one expected in idle check except for the Timers VQ (VQ3). This register is for VQs 24-31.
47763 …chronization FIFO; it asserts the 'almost full' bit. This number is common to all clock synchroniz…
47764 … de-asserts the 'almost full' bit. This is the almost full low configuration for all clients excep…
47766 …ization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for C…
47768 …ization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for P…
47770 …ization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for P…
47771 … from the FIFO towards the delivery module. The clients order is according to the incrementing cli…
47772 … 0x29d144UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47773 … 0x29d148UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47774 … 0x29d14cUL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47775 … 0x29d150UL //Access:R DataWidth:0x20 // Per-client maximum sync F…
47779 … 0x29d160UL //Access:R DataWidth:0x8 // Per-client maximum sync F…
47781 … (0x1<<0) // Signals an unknown address to the rf module.
47803 … (0x1<<0) // Signals an unknown address to the rf module.
47814 … (0x1<<0) // Signals an unknown address to the rf module.
47967 …d22cUL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47968 …d220UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47969 …d220UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47970 …d230UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47971 …d224UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47972 …d224UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47973 …d234UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47974 …d228UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47975 …d228UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47976 …d238UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47977 …d22cUL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47978 …d230UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47979 …d234UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
47980 …d238UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next wri…
48111 … 0x29d400UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
48112 … line) in the selected line (before shift).for selecting a line to output
48120 … 0x29d460UL //Access:RW DataWidth:0x1 // When '1'; inputs to the PSWRD block are …
48121 …er of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed. Shou…
48122 …st be bigger than 6. Normally should not be changed. Should have identical value to rq_blk_num_cfg.
48123 …TC entry ID' interface from PSWRQ is ignored and 'ATC RCPL Done' interface to ATC is not generated…
48124 …to the PBF and the data for the next request is already in the Tetris buffer. 0 - The delivery por…
48125 …to this client; this register determines the number of additional requests to deliver to the clien…
48126 …/ When finishing delivering a request to this client; this register determines the number of addit…
48127 …/ When finishing delivering a request to this client; this register determines the number of addit…
48128 …/ When finishing delivering a request to this client; this register determines the number of addit…
48129 …/ When finishing delivering a request to this client; this register determines the number of addit…
48130 …/ When finishing delivering a request to this client; this register determines the number of addit…
48131 …/ When finishing delivering a request to this client; this register determines the number of addit…
48132 …/ When finishing delivering a request to this client; this register determines the number of addit…
48133 …/ When finishing delivering a request to this client; this register determines the number of addit…
48134 …/ When finishing delivering a request to this client; this register determines the number of addit…
48135 …/ When finishing delivering a request to this client; this register determines the number of addit…
48136 …/ When finishing delivering a request to this client; this register determines the number of addit…
48137 …/ When finishing delivering a request to this client; this register determines the number of addit…
48138 …/ When finishing delivering a request to this client; this register determines the number of addit…
48139 …/ When finishing delivering a request to this client; this register determines the number of addit…
48140 …/ When finishing delivering a request to this client; this register determines the number of addit…
48141 …/ When finishing delivering a request to this client; this register determines the number of addit…
48146 …ot enable writing to the fifo. This value is based on implementation and should not be changed. Th…
48148 … 0x29e058UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
48149 … line) in the selected line (before shift).for selecting a line to output
48158 … (0x1<<0) // Signals an unknown address to the rf module.
48180 … (0x1<<0) // Signals an unknown address to the rf module.
48191 … (0x1<<0) // Signals an unknown address to the rf module.
48205 …er should check the value of this register is 1 some time after it wrote 1 to zone_perm_table_init.
48206 …0UL //Access:RW DataWidth:0x1 // When 1; new internal writes arriving to the block are discar…
48207 …ss:RW DataWidth:0x1 // When 1; doorbells are discarded and not passed to doorbell queue block…
48208 …//Access:RW DataWidth:0x1 // When 1; p2m are discarded and not passed to p2m queue block. Sho…
48209 …HST is discarding inputs from this client. Each bit should update accoring to 'hst_discard_interna…
48210 …means this PSWHST is discarding doorbells. This bit should update accoring to 'hst_discard_doorbel…
48211 …: '1' means this PSWHST is discarding p2m. This bit should update accoring to 'hst_discard_p2m' re…
48212 …ter-engine indicating if the engine is idle. Idle means the engine is not sending request (and the…
48213 …to a disabled VF; the format is [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 T…
48214 … 0x2a0060UL //Access:R DataWidth:0x1 // 1 - An error request is …
48215 … 0x2a0064UL //Access:R DataWidth:0x20 // The address of the first access to a disabled VF.
48216 …- RSV [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM…
48217 …idth:0x7 // The data of the first incorrect access. the format is: [6:0] - length in DWs. The d…
48218 … 0x2a0070UL //Access:R DataWidth:0x1 // 1 - An incorrect access …
48220 … 0x2a0078UL //Access:R DataWidth:0x1 // 1- permission violation…
48222 … // Number of credits for source SDM in internal write interface (common to all SDMs except USDM…
48226 …te source that consumed more than its allowed credits. the format is: [3:0] - client (0 TSDM; 1 MS…
48227 … 0x2a0094UL //Access:R DataWidth:0x1 // 1 - A source credit viol…
48228 …dth:0x2 // Number of credits for destination SDM in target write interface (common to all SDMs).
48232 … 0x2a00a8UL //Access:RW DataWidth:0x1e // Number of cycles to wait before entering…
48233 … 0x2a00acUL //Access:R DataWidth:0x1 // 1 - PSWHST is in drain m…
48234 … 0x2a00b0UL //Access:W DataWidth:0x1 // Writing 1 to this register indicates PSWHST to exi…
48235 …- length in DWs; [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - cli…
48236 …ess:R DataWidth:0x1 // 1 - An hst timeout data is logged. The valid bit is reset when exitin…
48238 …interface. PSWHST issues an attention if more credits are consumed. Added in BB-B0 due to pipeline.
48241 …W DataWidth:0x6 // Maximum write transaction data in DWs that is sent to SDMs and IGU. Write …
48253 … 0x2a0100UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
48254 … line) in the selected line (before shift).for selecting a line to output
48262 …ients. '1' means this client is waiting for the arbiter. Each entry refers to a different source a…
48265 … (0x1<<0) // Signals an unknown address to the rf module.
48283 … (0x1<<9) // Indicates there was an access to a disabled VF when c…
48287 … (0x1<<11) // Indicates there was an access to any of the clients …
48339 … (0x1<<0) // Signals an unknown address to the rf module.
48357 … (0x1<<9) // Indicates there was an access to a disabled VF when c…
48361 … (0x1<<11) // Indicates there was an access to any of the clients …
48376 … (0x1<<0) // Signals an unknown address to the rf module.
48394 … (0x1<<9) // Indicates there was an access to a disabled VF when c…
48398 … (0x1<<11) // Indicates there was an access to any of the clients …
48451 …und interrupts memory. E4 entry structure: [15:0] - CompParams. [23:16] - EventID. [24] - T. [28:2…
48453 … 0x2a0800UL //Access:RW DataWidth:0x9 // Indirect access to the permission table…
48457 …0x2a8000UL //Access:W DataWidth:0x1 // Writing 1 to this register signals the PGLUE block to…
48458 …Driver should make sure the corresponding bit is 1 some time after writing to start_init_inb_int_m…
48459 …riting 1 to this register signals the PGLUE block to start initializing PTT and GTT. Offsets shoul…
48460 …lization is done. MCP should make sure this bit is 1 some time after writing to start_init_ptt_gtt.
48461 … // Writing 1 to this register signals the PGLUE block to start calculating the start address of…
48462 …Driver should make sure the corresponding bit is 1 some time after writing to start_init_zone_a. B…
48464 … (0x1<<0) // Signals an unknown address to the rf module.
48466 … (0x1<<1) // Target RW or completion not according to PCIe core spec. See …
48482 … indicating a failure to exit Rx_L0s correctly. If this occurs "too frequently", this means that …
48486 … (0x1<<11) // Indicates Read/Write accesses to the admin window tha…
48490 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48504 … (0x1<<20) // Read was blocked due to master_en.
48506 … (0x1<<21) // Write was blocked due to master_en.
48562 … (0x1<<0) // Signals an unknown address to the rf module.
48564 … (0x1<<1) // Target RW or completion not according to PCIe core spec. See …
48580 … indicating a failure to exit Rx_L0s correctly. If this occurs "too frequently", this means that …
48584 … (0x1<<11) // Indicates Read/Write accesses to the admin window tha…
48588 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48602 … (0x1<<20) // Read was blocked due to master_en.
48604 … (0x1<<21) // Write was blocked due to master_en.
48611 … (0x1<<0) // Signals an unknown address to the rf module.
48613 … (0x1<<1) // Target RW or completion not according to PCIe core spec. See …
48629 … indicating a failure to exit Rx_L0s correctly. If this occurs "too frequently", this means that …
48633 … (0x1<<11) // Indicates Read/Write accesses to the admin window tha…
48637 … (0x1<<13) // Indicates an illegal address event - address smaller than…
48651 … (0x1<<20) // Read was blocked due to master_en.
48653 … (0x1<<21) // Write was blocked due to master_en.
48774 … 0x2a8400UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
48775 … line) in the selected line (before shift).for selecting a line to output
48783 …- for Atomic Op / MRD handling of NPH credits. 0 - Can send both if there is one NPH credit and th…
48785 …upied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value…
48787 … (0x1<<0) // 0 - Debug bus is not output to RBCN_e0. 1 - Debug bus is…
48789 … (0x1<<1) // 0 - Debug bus is not output to RBCN_e1. 1 - Debug bus is…
48806 … (0x1<<9) // This bit give strict priority to read over write on the PGL read-writ…
48809 …er_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that currently a write request is bloc…
48810 …er_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that currently a read request is block…
48820 …- Target memory read arrived with a correctable error. Bit 1 - Target memory read arrived with an …
48821 … in the PCIe dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value…
48822 … synchronization FIFO is enabled and frame, valid, data are output from it to the debug block. Whe…
48824 …ebug only. Used to disable an E2 optimization of having less dead cycles between adjacent write re…
48826 … (0x1<<1) // Debug only. Used to disable an E2 optimization of sending two pending reques…
48828 … (0x1<<2) // Debug only. Used to disable an E2 optimization of sending two pending write req…
48830 … 0x2a84bcUL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
48831 … 0x2a84c0UL //Access:RW DataWidth:0x8 // command to CPU BIST
48832 … 0x2a84c4UL //Access:RW DataWidth:0x8 // address to CPU BIST
48835 …- PCIe checksum is generated towards PCIe core. 1 - PCIe checksum is not generated towards PCIe co…
48836 … 0x2a84d4UL //Access:RW DataWidth:0x20 // A bit per VQ that indicates the TC to use.
48839 …:0x5 // Pseudo VF target mode configuration that controls the size of each pseudo-VF in the BAR.
48841 … // Enable PF to accesss DORQ via BAR0: 0-disable access; 1-enable access if BAR0 size is 128K; 2…
48842 … 0x2a84ecUL //Access:RW DataWidth:0x9 // VSC fields: bit 0 - enable VSC; bits 1-8 - VSC reser…
48846 … (0x1<<7) // Debug only: disable inputs to pgl.
48852 …pied in the cssnoop clock synchronization FIFO; it does not enable writing to the fifo. This value…
48853 …riting to the fifo. This value is based on implementation and should not be changed. In AH, due to…
48854 …ied in the TXW data clock synchronization FIFO; it does not enable writing to the fifo. This value…
48855 …d in the TXR header clock synchronization FIFO; it does not enable writing to the fifo. This value…
48858 …-PF region. Addresses 0x0 - 0x5c: 12 per-PF PF windows. Each PF window contains two 32-bit values.…
48860 …region. 0x0 - 0x3c8 (0x200 - 0x5c8) - 243 global windows. Each entry is the 12-bit window offset.…
48862 …ister on which config space A attention is generated. Note that this register is in 128-byte units.
48863 …ting in address cfg_space_a_address generates an attention. If bit N is set - a CSSNOOP cycle with…
48864 …ister on which config space B attention is generated. Note that this register is in 128-byte units.
48865 …ting in address cfg_space_b_address generates an attention. If bit N is set - a CSSNOOP cycle with…
48866 … PF generates config space A attention. Set by PXP. Reset by MCP writing 1 to icfg_space_a_request…
48867 …to a bit in this register in order to clear the corresponding bit in cfg_space_a_request register.…
48868 … PF generates config space B attention. Set by PXP. Reset by MCP writing 1 to icfg_space_b_request…
48869 …to a bit in this register in order to clear the corresponding bit in cfg_space_b_request register.…
48870 …y bits for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. …
48871 … bits for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. …
48872 … bits for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. …
48873 … bits for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set.…
48874 …bits for VFs 128 to 159. Each bit indicates that the FLR register of the corresponding VF was set.…
48875 …bits for VFs 160 to 191. Each bit indicates that the FLR register of the corresponding VF was set.…
48876 …bits for VFs 192 to 223. Each bit indicates that the FLR register of the corresponding VF was set.…
48877 …bits for VFs 224 to 255. Each bit indicates that the FLR register of the corresponding VF was set.…
48878 …gister of the corresponding PF was set. Set by PXP. Reset by MCP writing 1 to flr_request_pf_31_0_…
48879 …LR request attention dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in o…
48880 …R request attention dirty bits clear for VFs 32 to 63. MCP writes 1 to a bit in this register in o…
48881 …R request attention dirty bits clear for VFs 64 to 95. MCP writes 1 to a bit in this register in o…
48882 … request attention dirty bits clear for VFs 96 to 127. MCP writes 1 to a bit in this register in o…
48883 …request attention dirty bits clear for VFs 128 to 159. MCP writes 1 to a bit in this register in o…
48884 …request attention dirty bits clear for VFs 160 to 191. MCP writes 1 to a bit in this register in o…
48885 …request attention dirty bits clear for VFs 192 to 223. MCP writes 1 to a bit in this register in o…
48886 …request attention dirty bits clear for VFs 224 to 255. MCP writes 1 to a bit in this register in o…
48887 …est attention dirty bits clear for all PFs. MCP writes 1 to a bit in this register in order to cl…
48891 …ABLED_REQUEST (0x1<<1) // Debug only: When 1 SR-IOV disbaled request …
48893 …register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP wr…
48894 … SR IOV disabled attention dirty bits clear. MCP writes 1 to a bit in this register in order to cl…
48895 …0x2aa074UL //Access:R DataWidth:0x20 // Shadow BME register for VFs 0 to 31. Each bit indicat…
48896 …x2aa078UL //Access:R DataWidth:0x20 // Shadow BME register for VFs 32 to 63. Each bit indicat…
48897 …x2aa07cUL //Access:R DataWidth:0x20 // Shadow BME register for VFs 64 to 95. Each bit indicat…
48898 …x2aa080UL //Access:R DataWidth:0x20 // Shadow BME register for VFs 96 to 127. Each bit indica…
48899 …2aa084UL //Access:R DataWidth:0x20 // Shadow BME register for VFs 128 to 159. Each bit indica…
48900 …2aa088UL //Access:R DataWidth:0x20 // Shadow BME register for VFs 160 to 191. Each bit indica…
48901 …2aa08cUL //Access:R DataWidth:0x20 // Shadow BME register for VFs 192 to 223. Each bit indica…
48902 …2aa090UL //Access:R DataWidth:0x20 // Shadow BME register for VFs 224 to 255. Each bit indica…
48904 …to 31. MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_ena…
48905 …to 63. MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_ena…
48906 …to 95. MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_ena…
48907 …to 127. MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_en…
48908 …to 159. MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_en…
48909 …to 191. MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_en…
48910 …to 223. MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_en…
48911 …to 255. MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_en…
48912 …- Shadow bits clear for PFs 0 to 31. MCP writes 1 to a bit in this register in order to reset the…
48913 …cUL //Access:R DataWidth:0x20 // Shadow ats_enable register for VFs 0 to 31. Each bit indicat…
48914 …UL //Access:R DataWidth:0x20 // Shadow ats_enable register for VFs 32 to 63. Each bit indicat…
48915 …UL //Access:R DataWidth:0x20 // Shadow ats_enable register for VFs 64 to 95. Each bit indicat…
48916 …UL //Access:R DataWidth:0x20 // Shadow ats_enable register for VFs 96 to 127. Each bit indica…
48917 …L //Access:R DataWidth:0x20 // Shadow ats_enable register for VFs 128 to 159. Each bit indica…
48918 …L //Access:R DataWidth:0x20 // Shadow ats_enable register for VFs 160 to 191. Each bit indica…
48919 …L //Access:R DataWidth:0x20 // Shadow ats_enable register for VFs 192 to 223. Each bit indica…
48920 …L //Access:R DataWidth:0x20 // Shadow ats_enable register for VFs 224 to 255. Each bit indica…
48922 …th:0x10 // Shadow vf_enable register for all PFs. Each bit indicates if SR-IOV for the correspon…
48924 …0e8UL //Access:R DataWidth:0x20 // Shadow ido bits register for PFs 0 to 15. [15:0] : Each bi…
48925 …ed for that function with Unsupported Request error. Setting this register to 1 disables this auto…
48926 …- Reserved. Bit 1 - Reserved. Bit 2 - Reserved. Bit 3 - Reserved. Bit 4 - Completion with Configur…
48927 …Fs 0 to 31. Each bit indicates that there was a completion with uncorrectable error for the corre…
48928 …s 32 to 63. Each bit indicates that there was a completion with uncorrectable error for the corre…
48929 …s 64 to 95. Each bit indicates that there was a completion with uncorrectable error for the corre…
48930 … 96 to 127. Each bit indicates that there was a completion with uncorrectable error for the corre…
48931 …128 to 159. Each bit indicates that there was a completion with uncorrectable error for the corre…
48932 …160 to 191. Each bit indicates that there was a completion with uncorrectable error for the corre…
48933 …192 to 223. Each bit indicates that there was a completion with uncorrectable error for the corre…
48934 …224 to 255. Each bit indicates that there was a completion with uncorrectable error for the corre…
48935 …Fs 0 to 7. Each bit indicates that there was a completion with uncorrectable error for the corres…
48936 …to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error…
48937 …to 63. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error…
48938 …to 95. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error…
48939 …to 127. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_erro…
48940 …to 159. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_erro…
48941 …to 191. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_erro…
48942 …to 223. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_erro…
48943 …to 255. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_erro…
48944 …to 7. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_reque…
48945 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48946 …- PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of …
48947 …//Access:R DataWidth:0x20 // Address [31:0] of first write request not submitted due to error.
48948 …/Access:R DataWidth:0x20 // Address [63:32] of first write request not submitted due to error.
48949 …rite request not submitted due to error. [4:0] VQID. [17:5] - Length in bytes. [19] - VF_VALID. [2…
48950 …to error. [15:0] Request ID. [20:16] client ID. [24:21] - Error type - [21] - Indicates was_error …
48951 … //Access:R DataWidth:0x20 // Address [31:0] of first read request not submitted due to error.
48952 …//Access:R DataWidth:0x20 // Address [63:32] of first read request not submitted due to error.
48953 …to error. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [18:6] - Lengt…
48954 …to error. [15:0] Request ID. [20:16] client ID. [24:21] - Error type - [21] - Indicates was_error …
48955 …- PFID. [11:4] - VFID. [12] - VF_VALID. [17:13] - ITAG Index. [21:18] - Error type - [18] - Indic…
48956 …68UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-VF for master and tar…
48957 …6cUL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for master transac…
48958 …70UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target write t…
48959 …74UL //Access:RW DataWidth:0x1 // Internal FID_enable configuration per-PF for target read tr…
48960 …L //Access:R DataWidth:0x20 // A global view of internal_vfid_enable register for VFs 0 to 31.
48961 … //Access:R DataWidth:0x20 // A global view of internal_vfid_enable register for VFs 32 to 63.
48962 … //Access:R DataWidth:0x20 // A global view of internal_vfid_enable register for VFs 64 to 95.
48963 …//Access:R DataWidth:0x20 // A global view of internal_vfid_enable register for VFs 96 to 127.
48964 …/Access:R DataWidth:0x20 // A global view of internal_vfid_enable register for VFs 128 to 159.
48965 …/Access:R DataWidth:0x20 // A global view of internal_vfid_enable register for VFs 224 to 191.
48966 …/Access:R DataWidth:0x20 // A global view of internal_vfid_enable register for VFs 192 to 223.
48967 …/Access:R DataWidth:0x20 // A global view of internal_vfid_enable register for VFs 224 to 255.
48968 …pfid_enable registers for target flow. Bits [15:0] - internal_pfid_enable_target_write; Bits [31:1…
48969 … global view of internal_pfid_enable registers for master flow. Bits [15:0] - internal_pfid_enable…
49000 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49001 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49002 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49003 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49004 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49005 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49006 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49007 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49008 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49009 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49010 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49011 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49012 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49013 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49014 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49015 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49016 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49017 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49018 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49019 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49020 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49021 …-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabl…
49022 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49023 …// Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-st…
49024 … 0x2aa318UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49025 … 0x2aa31cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49026 … 0x2aa320UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49027 … 0x2aa324UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49028 … 0x2aa328UL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49029 … 0x2aa32cUL //Access:RW DataWidth:0x1 // 0 - Zone A PF has NumQueues queues. 1 - Zo…
49030 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49031 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49032 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49033 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49034 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49035 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49036 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49037 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49038 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49039 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49040 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49041 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49042 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49043 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49044 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49045 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49046 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49047 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49048 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49049 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49050 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49051 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49052 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49053 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49054 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49055 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49056 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49057 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49058 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49059 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49060 …- GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base). 0 m…
49061 …- Function offset. This fields allows different functions to access GRC locations in distance 2^Fu…
49062 …R0. [12:0] Address in DWs (bits [14:2] of byte address). [14:13] BAR. [22:15] VFID. [26:23] - PFID.
49063 …st with length violation (too many DWs) accessing BAR0. [5:0] - Length in DWs. [6] valid - indica…
49064 …ermission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. [23:16] VFID. [27:24] - PFID. [28…
49065 …to each bit in this register clears a corresponding error details register and enables logging new…
49067 … 0x2aa3c4UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates t…
49068 … 0x2aa3c8UL //Access:RW DataWidth:0x1 // Bit 0 - when set indicates t…
49069 … 0x2aa3ccUL //Access:RW DataWidth:0x1 // 1 - Do not discard IGU m…
49070 …- Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value i…
49071 …pletion is considered erroneous. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [17:13] - OTB EntryI…
49072 …- Unsupported Request or Completer Abort on User RX Interface. 1 - Reception of a poisoned TLP on …
49073 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49074 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49075 …- Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation S…
49076 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49077 …//Access:RW DataWidth:0x5 // Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_res…
49079 …ress for configuration access to PCIE config address 0x88. any write to this PCIE address will cau…
49080 …ress for configuration access to PCIE config address 0x8c. any write to this PCIE address will ca…
49081 …ress for configuration access to PCIE config address 0x90. any write to this PCIE address will ca…
49082 …ress for configuration access to PCIE config address 0x94. any write to this PCIE address will ca…
49083 …/Access:R DataWidth:0x19 // The address to be read from expansion rom (address is in bytes ac…
49085 …L //Access:R DataWidth:0x2 // The size in dwords to be read from expansion rom (according to…
49086 …tion is sent to the pcie core. When the expansion rom request contains more than one dword this re…
49094 …to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TS…
49096 …to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TS…
49098 …to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TS…
49100 …to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TS…
49102 …to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TS…
49104 …to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TS…
49106 …to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TS…
49108 …to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TS…
49110 …-only register reflects the value of the corresponding 'PF trusted' config bit on the external con…
49113 …. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFI…
49114 …- PGLUE will submit the request with TPH info. PXP will take care of aligning it correctly when se…
49115 …to the admin window that have a length bigger than 1DW or first byte enable != 0xf . [9:0] Address…
49116 …- original PFID. [7:4] Pretend PFID. [15:8] Pretend VFID. [16] Pretend vf_valid. [20:17] Pretend r…
49118 …- Work with external BAR0 mechanism as defined in E4 spec. 1 - Disable external BAR0 mechanism. Ac…
49125 …ataWidth:0x1 // FID channel enable configuration per-VF. Controls Target read/write access to …
49126 …if the PF to VF channel is enabled for that SDM. One bit per SDM. Bit 0 - TSDM. Bit 1 - MSDM. Bit …
49127 …aWidth:0x3 // Window size for VF to PF channel. 0 - NA; 1 - 8B; 2 - 16B; 3 - 32B; 4 - 64B; 5 - …
49128 …588UL //Access:RW DataWidth:0x6 // Defines the start offset of the VF to PF window within VF …
49130 … (0x1<<0) // Decision bit for PF master requests when BME is cleared: 0 - block; 1 - discard.
49132 …(0x1<<1) // Decision bit for PF master requests when fid_enable is cleared: 0 - block; 1 - discard.
49134 … (0x1<<2) // Decision bit for PF master requests when was_error is set: 0 - block; 1 - discard.
49136 … (0x1<<3) // Decision bit for VF master requests when BME is cleared: 0 - block; 1 - discard.
49138 …(0x1<<4) // Decision bit for VF master requests when fid_enable is cleared: 0 - block; 1 - discard.
49140 … (0x1<<5) // Decision bit for VF master requests when was_error is set: 0 - block; 1 - discard.
49143 … PF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set att…
49145 …er requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set att…
49147 …F master requests when was_error is set: 0 - Always set (and log error details); 1 - never set att…
49149 … VF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set att…
49151 …er requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set att…
49153 …F master requests when was_error is set: 0 - Always set (and log error details); 1 - never set att…
49155 …t for that function will not generate an attention. This bit will allow SW to extend the period in…
49156 …t for that function will not generate an attention. This bit will allow SW to extend the period in…
49162 …ataWidth:0x1 // A value of '1' instructs PGLUE to use the client ID value in the 'tag' field of…
49163 … field is an enable bit for 'detection of out-of-range requests' debug feature. It should be initi…
49165 … of ) the minimal legal address value. It is used in the 'detection of out-of-range requests' debu…
49167 … of ) the maximal legal address value. It is used in the 'detection of out-of-range requests' debu…
49171 …th illegal address. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49172 …- address was smaller than minimal_address_log; 1 - address was bigger than maximal_address_log. …
49175 …th TPH information. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49176 …nt ID. [6:5] PH. [14:7] Steering Tag. [15] - write_n_read: 0 - read; 1 - write. [16] - last SR. […
49177 …x1 // 0 - never pad write sub-requests with zeros. 1 - Pad write sub-requests with zeros and al…
49178 …/Access:RW DataWidth:0x3 // Cache line size for padding. 0 - 32B. 1 - 64B. 2 - 128B. 3 - 256B.
49179 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49180 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49181 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49182 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49183 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49184 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49185 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49186 …Width:0x20 // Indicates the status of tags. 0 - tags is used - read completion did not return ye…
49188 …ess:RW DataWidth:0x20 // This register is used for backdoor rbc access to PCI config space reg…
49189 …3:0 in PCIE_REG_PCIER_CONFIG_2) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128…
49190 …PCIE_REG_PCIER_REG_BAR2_CONFIG) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128…
49191 …in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 disabled; 1 4K; 2 8K…
49192 …Indication to clear MCTP attention that was genertaed due to bus number change detected by PCIe IP…
49196 …t error indication. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20]…
49197 …[15:0] Request ID. [20:16] client ID. [21] - write_n_read: 0 - read; 1 - write. [22] - last SR. […
49199 …is for engine 0 and bit 1 for engine 1. Set by PXP. Reset by MCP writing 1 to the corresponding bi…
49200 …it 0 is for engine 0 and bit 1 for engine 1. MCP writes 1 to a bit in this register in order to cl…
49201 …idth:0x10 // MPS attention dirty bit. Set by PXP. Reset by MCP writing 1 to the corresponding bi…
49202 …dth:0x10 // MPS attention dirty bit clear. MCP writes 1 to a bit in this register in order to cl…
49203 … the corresponding PF was set. Set by PXP. Reset by MCP according to VPD flow (write to 0x2430). N…
49204 …idth:0x10 // This register controls the path_in_d3 output to CPMU. Each bit corresponds to a PF …
49209 … 0x2aaeb0UL //Access:RW DataWidth:0x1 // Chicken bit to disable app_xfer_pen…
49210 …:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 2K; 1 4K; 2 8K; u…
49211 …:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 2k; 1 4K; 2 8K; u…
49226 …x2aaef4UL //Access:R DataWidth:0xc // Error log for dllp abort bit8 to 11 pfid bit0 to 7 tag
49229 …to Bit1 pcie_pgl_dbi_addr Bit17 to Bit5 Dbi_func_num Bit21 to…
49233 … 0x2aaf10UL //Access:R DataWidth:0x10 // pm_dstate 47-032
49235 … 0x2aaf60UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 31-0
49236 … 0x2aaf64UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 63 -32
49237 … 0x2aaf68UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 95 - 64
49238 … 0x2aaf6cUL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 127 - 96
49239 … 0x2aaf70UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 159-128
49240 … 0x2aaf74UL //Access:R DataWidth:0x20 // FLR Invalidate in progress vf 191 to 160
49241 … 0x2aaf78UL //Access:R DataWidth:0x10 // FLR Invalidate in progress pf 31 to 0
49243 … // Indicates there was an error in MCTP BIt 21-30 Message code Bit 7-22 Vender ID Bit 3-6 TAG…
49244 …dth:0x20 // Indicates there was an error in MCTP Bit 21-30 Length Bit 5-20 PCIE REQ ID Bit 0-4 …
49245 …x2aaf88UL //Access:R DataWidth:0xc // Error log for ecrc abort bit8 to 11 pfid bit0 to 7 tag
49246 …0x2aaf8cUL //Access:R DataWidth:0xc // Error log for tlp abort bit8 to 11 pfid bit0 to 7 tag
49247 … 0x2aaf90UL //Access:R DataWidth:0xc // Error log for poison bit8 to 11 pfid bit0 to 7 tag
49249 …ress for configuration access to PCIE config address 0xe8. any write to this PCIE address will cau…
49250 …ress for configuration access to PCIE config address 0xec. any write to this PCIE address will ca…
49251 …ress for configuration access to PCIE config address 0xf0. any write to this PCIE address will ca…
49252 …ress for configuration access to PCIE config address 0xf4. any write to this PCIE address will ca…
49256 …0x2aafb4UL //Access:RW DataWidth:0x1 // 0 - Don't discard target request with unknown header …
49257 … // 0 - Don't compare the function received in the completion to the original MRD function. 1 - Co…
49258 … 0x2aafbcUL //Access:RW DataWidth:0x1 // 0 - Enable b2b pop from sync fifos in pgl_pci_core_r…
49259 … 0x2aafc0UL //Access:RW DataWidth:0x1 // 0 - Don't discard master request during FLR 1 …
49260 … DataWidth:0x4 // 0 - TXCPL sync fifo push overflow 1 - TXR sync fifo push overflow 2 - TXW hea…
49261 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo pop underflow 1 - RX header syn…
49262 …x2aafccUL //Access:R DataWidth:0x12 // 8:0 - RX target read and config sync fifo pop status …
49273 … // When set, the self init for the context memory is done. TBD - need to change to read, all t…
49296 …to the Expiration FIFO row size. The number of allowed CFC load requests …
49298 … (0x1<<0) // Signals an unknown address to the rf module.
49358 … (0x1<<30) // Command arrived to the host handler uni…
49428 … (0x1<<0) // Signals an unknown address to the rf module.
49488 … (0x1<<30) // Command arrived to the host handler uni…
49493 … (0x1<<0) // Signals an unknown address to the rf module.
49553 … (0x1<<30) // Command arrived to the host handler uni…
49562 … (0x1<<2) // Context Read with Last indication de-asserted.
49564 … (0x1<<3) // Context Write with Last indication de-asserted.
49608 … (0x1<<2) // Context Read with Last indication de-asserted.
49610 … (0x1<<3) // Context Write with Last indication de-asserted.
49631 … (0x1<<2) // Context Read with Last indication de-asserted.
49633 … (0x1<<3) // Context Write with Last indication de-asserted.
49751 …he VF functions for the connections. This configuration is applicable only to scan operation. Was…
49752 …able the PF functions for the connections. This configuration is applicable only to scan opeartion.
49753 …able the VF functions for the tasks. This configuration is applicable only to scan operation. Was…
49754 …able the PF functions for the tasks. This configuration is applicable only to scan opeartion. Bit …
49757 …of ticks (tick_timer) that generate a connection scan pulse, an indication to scan the connections…
49759 …mber of ticks (tick_timer) that generate a tasks scan pulse, an indication to scan the tasks timer…
49769 … the pci outstanding read requests, generated by the scan engine. The applicable values are 1 to 4.
49770 …x2 // Number of timers per connection group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49771 …idth:0x2 // Number of timers per task group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 1…
49772 …to scan a connection group: 00 - the pre scan feature is disabled, i.e. every scan pulse all the g…
49773 …to scan a task group: 00 - the pre scan feature is disabled, i.e. every scan pulse all the groups …
49774 …sed. This configuration is applicable only if PreScanRange register is set to 0. TBD = name of the…
49776 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49777 …lock in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49778 …ckss in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49779 …eld for writes; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search …
49780 …to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client …
49781 …to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client …
49782 …to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client …
49783 …to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client …
49784 …to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client …
49785 …to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client …
49786 …to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client …
49787 …to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client …
49788 …to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checkin…
49789 …to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checkin…
49790 …to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checkin…
49791 …to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checkin…
49792 …to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checkin…
49793 …to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checkin…
49794 …ons, which is used on decision on whether to send a write command to the host or postpone the writ…
49795 …ons, which is used on decision on whether to send a write command to the host or postpone the writ…
49796 …ons, which is used on decision on whether to send a write command to the host or postpone the writ…
49797 …sks, which is used on decision on whether to send a write command to the host or postpone the writ…
49798 …asks which is used on decision on whether to send a write command to the host or postpone the writ…
49799 …skss which is used on decision on whether to send a write command to the host or postpone the writ…
49831 …//Access:RC DataWidth:0x20 // Number of commands (write requests) sent to host (set, clear, st…
49836 … 0x2c0674UL //Access:RC DataWidth:0x20 // Number of read requests (scan) sent to host.
49839 …f ticks (tick_timer) that generates a connection scan pulse, an indication to scan the connections…
49840 …mber of ticks (tick_timer) that generates a task scan pulse, an indication to scan the tasks timer…
49854 …command, Bit [7]: if = 1, the following error is enabled: command arrived to the host handler uni…
49856 …, if the error took place, only a command with error for the fid identical to this regsiter is kep…
49858 …cal to this regsiter is kept in the debug_0 registers. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XC…
49859 …tes that the debug_0 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49863 …- SET TIMER, 1 - CLEAR TIMER, 2 - STOP ALL TIMERS, 3 - INIT, 4 - FORCE CLEAR TIMER, 5 - reserved,…
49866 …s:R DataWidth:0x1 // The Leader Type field for the errored command: 0 - connection, 1 - task.
49867 …r the errored command. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved,…
49868 …e bit. This status information doesnt exist for the error: command arrived to the host handler uni…
49869 …D command, Bit [7]: if = 1, the following error happened: command arrived to the host handler uni…
49870 …tes that the debug_1 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49872 …-0: LCID, Bit 9: scan type (0 - connection, 1 - task), Bits 12-10: type (3 LSbits), Bit 13: Load E…
49873 …tes that the debug_2 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49874 …last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 10…
49875 …tes that the debug_3 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49876 …ion de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 11-10: Qward V…
49877 …-0: cmd_handler. Bit 3: reserved. Bits 7-4: writ…
49878 …tes that the debug_4 registers contain valid data. Asserted by the hardware, de-asserted by the SW.
49879 … Bits 8-0: function # (0-239 VFs, 240 and above PFs / segments) . Bit 9: type (0 - connecti…
49880 … 0x2c07a8UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
49881 … line) in the selected line (before shift).for selecting a line to output
49889 …to 239 are for VFs 0 to 239: row 0 for VF 0, row 1 for VF1, row 2 for VF 2, etc. Rows 240 to 255 a…
49893 …to 239 are for VFs 0 to 239: row 0 for VF 0, row 1 for VF1, row 2 for VF 2, etc. Rows 240 to 303 a…
49897 …r connections, the last 512 rows contain the scan rate fields for tasks. TBD - describe the fields.
49900 …ed to two sections: the first section is for the LCIDs, the second section is for the LTIDs. Ie ad…
49904 … (0x1<<0) // When set activity counter ram will be initialized to zeros. when this ope…
49906 …STERS_INIT_REG.LL_INIT . indicates the last lcid to be used by the CFC. this field can strict the …
49908 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be lo…
49910 … (0x1<<11) // When set the CFC CAMs will be initialized to zeros. When this ope…
49912 …// Setting this bit causes the TID Lock RAM to be initialized. This cannot be set during normal op…
49919 … (0x1<<0) // Signals an unknown address to the rf module.
49929 … (0x1<<0) // Signals an unknown address to the rf module.
49934 … (0x1<<0) // Signals an unknown address to the rf module.
49972 … 0x2d0410UL //Access:RW DataWidth:0xe // Used to mask the various loa…
49980 … 0x2d0500UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
49981 … line) in the selected line (before shift).for selecting a line to output
49993 … it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Request…
49994 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
49995 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
49996 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50010 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50020 … (0xf<<10) // This register is not used in BB-B0. Reduced width to 1 bit to keep i…
50047 … 0x2d05c8UL //Access:RW DataWidth:0x7 // Used to mask all various typ…
50048 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50049 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50050 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50051 …st WB change: When an inactivate request is processed do not move the LCID to Inactive state if an…
50052 … 0x2d05dcUL //Access:RW DataWidth:0x1 // The Interface to Searcher Request Que…
50053 … 0x2d05e0UL //Access:RW DataWidth:0x1 // The Interface to Parser Response Queu…
50078 …cess:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a load requ…
50079 …cess:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a load requ…
50080 …ear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search …
50081 …ear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search …
50084 …e to enable the MiniCache in the Load Clients. If there are less Empty LCIDs than this threshold,…
50086 … (0x1<<10) // This field is not used in BB-B0. When set, this co…
50092 … (0x1<<9) // When set to 1 the search string …
50094 … (0x1<<10) // When set to 1 the cid cam is dis…
50096 …hat region will be submitted; otherwise an immediate response will be sent to the client with erro…
50098 … (0x1<<12) // When set to 1 the string cam hit…
50100 … (0x1<<13) // When set to 1 the string cam mis…
50102 … (0x1<<14) // When set to 1 the cid cam hit pa…
50104 … (0x1<<15) // When set to 1 the cid cam miss p…
50112 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50116 … (0x3<<0) // This register is used to set the usage policy…
50118 … (0x3<<2) // This register is used to set the usage policy…
50123 …r, LC controller can start working on a new request. This is used in order to prevent deadlock whe…
50124 …Threshold for LC CLient 0 (YULD). When the number of Active LCIDs is equal to or greater than this…
50125 …Threshold for LC CLient 1 (XYLD). When the number of Active LCIDs is equal to or greater than this…
50126 …Threshold for LC CLient 2 (TMLD). When the number of Active LCIDs is equal to or greater than this…
50127 …Threshold for LC CLient 3 (MULD). When the number of Active LCIDs is equal to or greater than this…
50128 …Threshold for LC CLient 4 (YSDM). When the number of Active LCIDs is equal to or greater than this…
50129 …Threshold for LC CLient 5 (XSDM). When the number of Active LCIDs is equal to or greater than this…
50130 …Threshold for LC CLient 6 (USDM). When the number of Active LCIDs is equal to or greater than this…
50131 …Threshold for LC CLient 7 (TSDM). When the number of Active LCIDs is equal to or greater than this…
50132 …Threshold for LC CLient 8 (PSDM). When the number of Active LCIDs is equal to or greater than this…
50133 …Threshold for LC CLient 9 (MSDM). When the number of Active LCIDs is equal to or greater than this…
50134 …eshold for LC CLient 10 (Timers). When the number of Active LCIDs is equal to or greater than this…
50135 … Threshold for LC CLient 11 (QM). When the number of Active LCIDs is equal to or greater than this…
50136 …eshold for LC CLient 12 (Parser). When the number of Active LCIDs is equal to or greater than this…
50137 …hreshold for LC CLient 13 (DORQ). When the number of Active LCIDs is equal to or greater than this…
50138 …to disable Direct messages in the DORQ. When the number of Active LCIDs is above this value, CFC w…
50139 …to one of the state machines [2:0]. Writing the bits to 1'b1 will restart the Timer in each Genera…
50169 … (0x1<<0) // When set, the String CAM will be used to cache results from t…
50171 … (0x1<<1) // When set, the String CAM will be used to cache results from t…
50173 …k is used for Searches and Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a sea…
50174 …ting to the ccam will cause a search operation on the written item (written using CFC_REGISTERS_LC…
50185 …g to the scam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_…
50186 … 0x2d0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous…
50187 …n E4B0. 0 - tid is not included in hash calculation (like in A0). 1 - tid is included in hash calc…
50188 …ded in E4B0. 0 - vlan is not included in hash calculation (like in A0). 1 - vlan is included in ha…
50189 … 0x2d0b00UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST …
50191 …to select the CID CAM BIST status word to read following the completion of a BIST test. Also used …
50192 … 0x2d0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CID CAM B…
50193 … 0x2d0b10UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST …
50195 …to select the STRING CAM BIST status word to read following the completion of a BIST test. Also us…
50196 … 0x2d0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the STRING CA…
50207 … 0x2db000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50215 … 0x2dd008UL //Access:R DataWidth:0x9 // VF port to VF/PF LCID state cou…
50216 … 0x2dd00cUL //Access:R DataWidth:0x9 // PF port to VF/PF LCID state cou…
50217 … 0x2dd010UL //Access:R DataWidth:0x9 // VF port to VF/PF LCID state cou…
50218 … 0x2dd014UL //Access:R DataWidth:0x9 // PF port to VF/PF LCID state cou…
50220 … (0x1<<0) // When set activity counter ram will be initialized to zeros. when this ope…
50222 …STERS_INIT_REG.LL_INIT . indicates the last lcid to be used by the CFC. this field can strict the …
50224 … (0x1<<10) // When set link list ram will be initialized - all LCIDs will be lo…
50226 … (0x1<<11) // When set the CFC CAMs will be initialized to zeros. When this ope…
50228 …// Setting this bit causes the TID Lock RAM to be initialized. This cannot be set during normal op…
50235 … (0x1<<0) // Signals an unknown address to the rf module.
50245 … (0x1<<0) // Signals an unknown address to the rf module.
50250 … (0x1<<0) // Signals an unknown address to the rf module.
50315 … 0x2e0410UL //Access:RW DataWidth:0xe // Used to mask the various loa…
50323 … 0x2e0500UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
50324 … line) in the selected line (before shift).for selecting a line to output
50336 … it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Request…
50337 … DataWidth:0x20 // When the CFC detects an internal error it updates these fields. [31:00] -- CID
50338 …CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active L…
50339 …an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00…
50353 …Width:0x3 // This field allows changing the priorities of the weighted-round-robin arbiter whic…
50363 … (0xf<<10) // This register is not used in BB-B0. Reduced width to 1 bit to keep i…
50390 … 0x2e05c8UL //Access:RW DataWidth:0x7 // Used to mask all various typ…
50391 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50392 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50393 …nctions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.
50394 …st WB change: When an inactivate request is processed do not move the LCID to Inactive state if an…
50395 … 0x2e05dcUL //Access:RW DataWidth:0x1 // The Interface to Searcher Request Que…
50396 … 0x2e05e0UL //Access:RW DataWidth:0x1 // The Interface to Parser Response Queu…
50421 …cess:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a load requ…
50422 …cess:RW DataWidth:0x1 // This bit when clear will cause a load-cancel response to a load requ…
50423 …ear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search …
50424 …ear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search …
50427 …e to enable the MiniCache in the Load Clients. If there are less Empty LCIDs than this threshold,…
50429 … (0x1<<10) // This field is not used in BB-B0. When set, this co…
50435 … (0x1<<9) // When set to 1 the search string …
50437 … (0x1<<10) // When set to 1 the cid cam is dis…
50439 …hat region will be submitted; otherwise an immediate response will be sent to the client with erro…
50441 … (0x1<<12) // When set to 1 the string cam hit…
50443 … (0x1<<13) // When set to 1 the string cam mis…
50445 … (0x1<<14) // When set to 1 the cid cam hit pa…
50447 … (0x1<<15) // When set to 1 the cid cam miss p…
50455 …L //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if les…
50459 … (0x3<<0) // This register is used to set the usage policy…
50461 … (0x3<<2) // This register is used to set the usage policy…
50466 …r, LC controller can start working on a new request. This is used in order to prevent deadlock whe…
50467 …Threshold for LC CLient 0 (YULD). When the number of Active LCIDs is equal to or greater than this…
50468 …Threshold for LC CLient 1 (XYLD). When the number of Active LCIDs is equal to or greater than this…
50469 …Threshold for LC CLient 2 (TMLD). When the number of Active LCIDs is equal to or greater than this…
50470 …Threshold for LC CLient 3 (MULD). When the number of Active LCIDs is equal to or greater than this…
50471 …Threshold for LC CLient 4 (YSDM). When the number of Active LCIDs is equal to or greater than this…
50472 …Threshold for LC CLient 5 (XSDM). When the number of Active LCIDs is equal to or greater than this…
50473 …Threshold for LC CLient 6 (USDM). When the number of Active LCIDs is equal to or greater than this…
50474 …Threshold for LC CLient 7 (TSDM). When the number of Active LCIDs is equal to or greater than this…
50475 …Threshold for LC CLient 8 (PSDM). When the number of Active LCIDs is equal to or greater than this…
50476 …Threshold for LC CLient 9 (MSDM). When the number of Active LCIDs is equal to or greater than this…
50477 …eshold for LC CLient 10 (Timers). When the number of Active LCIDs is equal to or greater than this…
50478 … Threshold for LC CLient 11 (QM). When the number of Active LCIDs is equal to or greater than this…
50479 …eshold for LC CLient 12 (Parser). When the number of Active LCIDs is equal to or greater than this…
50480 …hreshold for LC CLient 13 (DORQ). When the number of Active LCIDs is equal to or greater than this…
50481 …to disable Direct messages in the DORQ. When the number of Active LCIDs is above this value, CFC w…
50482 …to one of the state machines [2:0]. Writing the bits to 1'b1 will restart the Timer in each Genera…
50512 … (0x1<<0) // When set, the String CAM will be used to cache results from t…
50514 … (0x1<<1) // When set, the String CAM will be used to cache results from t…
50516 …k is used for Searches and Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a sea…
50517 …ting to the ccam will cause a search operation on the written item (written using CFC_REGISTERS_LC…
50528 …g to the scam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_…
50529 … 0x2e0a3cUL //Access:R DataWidth:0xa // {HIT;LCID}. HIT - if set then previous…
50530 …n E4B0. 0 - tid is not included in hash calculation (like in A0). 1 - tid is included in hash calc…
50531 …ded in E4B0. 0 - vlan is not included in hash calculation (like in A0). 1 - vlan is included in ha…
50532 … 0x2e0b00UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST …
50534 …to select the CID CAM BIST status word to read following the completion of a BIST test. Also used …
50535 … 0x2e0b0cUL //Access:R DataWidth:0x20 // Provides read-only access to the CID CAM B…
50536 … 0x2e0b10UL //Access:RW DataWidth:0x1 // Used to enable/disable BIST …
50538 …to select the STRING CAM BIST status word to read following the completion of a BIST test. Also us…
50539 … 0x2e0b1cUL //Access:R DataWidth:0x20 // Provides read-only access to the STRING CA…
50550 … 0x2eb000UL //Access:WB DataWidth:0x21 // CID cam access (Valid - 32;31:0 - Data).
50559 … 0x2ed008UL //Access:R DataWidth:0x9 // VF port to VF/PF LCID state cou…
50560 … 0x2ed00cUL //Access:R DataWidth:0x9 // PF port to VF/PF LCID state cou…
50561 … 0x2ed010UL //Access:R DataWidth:0x9 // VF port to VF/PF LCID state cou…
50562 … 0x2ed014UL //Access:R DataWidth:0x9 // PF port to VF/PF LCID state cou…
50564 … (0x1<<0) // Signals an unknown address to the rf module.
50654 … (0x1<<0) // Signals an unknown address to the rf module.
50699 … (0x1<<0) // Signals an unknown address to the rf module.
51180 …to the function for TX queues. There are 2 different values per fucntion and each PQ that belongs …
51181 …to the function for TX queues. There are 2 different values per fucntion and each PQ that belongs …
51182 …to the function for Other queues. There is single values per fucntion and each PQ that belongs to …
51183 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51184 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51185 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51186 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51187 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51188 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51189 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51190 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51191 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51192 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51193 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51194 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51195 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51196 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51197 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51198 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51199 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51200 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51201 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51202 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51203 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51204 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51205 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51206 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51207 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51208 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51209 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51210 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51211 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51212 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51213 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51214 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51215 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51216 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51217 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51218 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51219 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51220 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51221 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51222 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51223 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51224 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51225 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51226 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51227 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51228 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51229 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51230 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51231 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51232 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51233 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51234 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51235 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51236 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51237 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51238 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51239 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51240 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51241 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51242 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51243 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51244 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51245 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51246 …ize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ…
51250 …st buffer within the RC response unit for the TX connection requests (goes to the CCFC). NOTE: The…
51251 …buffer within the RC response unit for the Other connection requests (goes to the CCFC). NOTE: The…
51254 …L //Access:WB DataWidth:0x36 // Pointer Table Memory for Other queues 63-0; The mapping is as …
51257 … 0x2f1000UL //Access:RW DataWidth:0xd // The address of the TX BigRam to access. Accessing th…
51258 … 0x2f1008UL //Access:WB DataWidth:0x3e // The data of the TX bigRam to access (rd/wr). Acce…
51260 … 0x2f1010UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51261 …2f1014UL //Access:RW DataWidth:0xb // The address of the Other BigRam to access. Accessing th…
51262 … 0x2f1020UL //Access:WB DataWidth:0x6e // The data of the Other bigRam to access (rd/wr). Acce…
51264 … 0x2f1030UL //Access:W DataWidth:0x1 // The mem access cmd (0 - rd; 1 - wr) sent towards…
51265 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51266 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51267 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51268 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51269 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51270 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51271 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51272 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51273 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51274 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51275 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51276 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51277 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51278 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51279 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51280 …queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 4…
51281 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51282 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51283 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51284 …// Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Q…
51367 …-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in page; b7: reserved (zero)…
51368 …igured according to the minimal STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-…
51369 …H field used in the PCI request. Per PF value. bits: 8-0 TPH Steering Tag Index; 12-9 reserved; 14…
51370 … 0x2f1534UL //Access:RW DataWidth:0x1 // pad to cache line field as …
51372 … 0x2f153cUL //Access:RC DataWidth:0x1 // A flag to indicate that overfl…
51374 … 0x2f1544UL //Access:RC DataWidth:0x1 // A flag to indicate that overfl…
51375 …- VOQs [0..31] VoqCrdLineFull_msb - VOQs [32..35] Some VOQs are "not used" depending on the…
51376 … in the QM. must be smaller or equal to the matched Voq line credit (relevant only for VOQs that …
51377 …- VOQs [0..31]. VoqCrdByteFull_msb - VOQs [32..35]. Some VOQs are "not used" depending on t…
51378 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51379 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51380 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51381 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51382 …- VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functi…
51383 …- VOQs [0..31]. AFullQmBypThrLineVoqMask_msb - VOQs [32..35]. Some VOQs are "not used" depe…
51388 …- resource is required to be more than the almost full threshold. 0 - resource value is do not car…
51391 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_3
51392 …ost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_4
51395 …- resource is required to be more than the almost full threshold. 0 - resource value is do not car…
51396 … 0x2f1948UL //Access:RW DataWidth:0x1 // Allows the QM to work in qm bypass mo…
51397 … 0x2f194cUL //Access:RW DataWidth:0x1 // Allows the QM to answer and handle op…
51398 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51399 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51400 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51401 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51402 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51403 …at are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 -…
51404 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51405 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51406 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51407 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51408 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51409 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51410 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51411 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51412 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51413 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51414 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51415 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51416 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51417 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51418 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51419 …- for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - P…
51420 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51421 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51422 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51423 …-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are eit…
51424 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b01. NOTE: weight update is allowed only to queues w…
51425 …-s that belong to TxPqMap[WrrWeightGrpRng]==2'b11. NOTE: weight update is allowed only to queues w…
51436 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51437 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51438 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51439 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51440 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51441 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51442 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51443 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51444 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51445 … interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51446 …is masked. i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - Y…
51447 …to the matched CM interface. address: 7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-…
51462 …0x2f2800UL //Access:R DataWidth:0x1 // The status of the Other PQ-s: bit0 - PQ paused. Shoul…
51466 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51467 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51468 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51469 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51470 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51471 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51472 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51473 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51474 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51475 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51476 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51477 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51478 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51479 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51480 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51481 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51482 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51483 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51484 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51485 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51486 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51487 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51488 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51489 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51490 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51491 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51492 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51493 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51494 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51495 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51496 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51497 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51498 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51499 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51500 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51501 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51502 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51503 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51504 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51505 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51506 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51507 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51508 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51509 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51510 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51511 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51512 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51513 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51514 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51515 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51516 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51517 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51518 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51519 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51520 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51521 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51522 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51523 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51524 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51525 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51526 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51527 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51528 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51529 … PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Grou…
51530 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51531 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51532 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51533 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51534 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51535 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51536 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51537 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51538 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51539 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51540 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51541 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51542 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51543 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51544 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51545 … 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Grou…
51550 …y: For dbgmux usage (debug data that goes from QM to the DBG block) - for selecting a line to outp…
51551 …4 // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for enablin…
51552 …2 // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for circula…
51553 …4 // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing val…
51554 …4 // Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing fra…
51555 …nly: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that goes …
51556 …nly: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that goes …
51557 …nly: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits that goes…
51558 …nly: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits that goes…
51561 …through RBC) based on the functional flows (e.g. FLR). It is also possible to set this bit by the …
51571 …ut period in 25Mhz clock cycles for the global. VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51572 …out period in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51573 … for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. Upon init should be set with value of …
51574 …od counter in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Gl…
51575 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51576 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51577 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51578 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51579 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51580 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51581 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51582 …unter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 -…
51585 …e msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of th…
51587 …-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb …
51590 …2f4c04UL //Access:RW DataWidth:0x9 // number of active RL counters (between 1 to QM_NUM_OF_RL)
51591 …x1 // when 1 - force cam search and update sts_rlglbl_pq_blocked vector even when the rlglblcrd…
51592 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51593 …r)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51594 …o). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: clie…
51595 …ector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlGlblCrd; b1 …
51596 …ataWidth:0x20 // The RL timeout period in 25Mhz clock cycles for the PF RL-s. NOTE: ck25 domain.…
51597 …:0x20 // The RL timeout period counter in 25Mhz clock cycles for the PF RL-s. Upon init should b…
51601 …e msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of th…
51604 …-init mode. In init mode should be written with the same value of RlPfUpperBound. Sign: the msb is…
51608 … the PF RL mechanism per VOQ. RlPfVoqEnable (This one) - VOQs [0..31]. RlPfVoqEnable_msb - …
51609 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51610 …ter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51611 …ero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: clie…
51612 … vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlPfCrd; b1 …
51616 …e msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of th…
51619 …- VOQ0..VOQ15. WfqPfCrd_msb - VOQ16..VOQ35. Should be read only access in non-init mode. In init m…
51624 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51625 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51626 …- error valid; b1: reserved (should be filled with zeroes); b5-b2: pf id; b11-b6: voq id; b15-b12…
51627 …vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqPfCrd; b1 …
51629 …0x1 // when 1 - force cam search and update sts_wfqvp_pq_blocked vector even when the wfqvpcrd …
51630 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51631 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51632 …- error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (s…
51633 …vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqVpCrd; b1 …
51634 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51635 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51636 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51637 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51638 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51639 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51640 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51641 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51642 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51643 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51644 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51645 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51646 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51647 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51648 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51649 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51650 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51651 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51652 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51653 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51654 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51655 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51656 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51657 …- highest priority;...; Weight7 - lowest priority; The values are TC numbers (to reflect the prio…
51659 …to non-idle state, trying to start new TX arbitration depends on the GO mode as follows: 0 - start…
51662 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51663 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51664 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51665 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51666 …when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqLineCrd; b1 - Err_…
51667 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51668 …ue. b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51669 …r)) b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51670 …o). b0 - error valid; b2-b1: reserved (should be filled with zeroes); b8-b3: voq id; b12-b9: clie…
51671 …when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqByteCrd; b1 - Err_…
51678 …to verify that prior to sending go command. (b) Go command can be sent only in init mode (i.e. no …
51679 … DataWidth:0x1 // When set indicates that the mem init unit is ready to accept mem init comm…
51680 …to init upon Mem_Init_Go command. When set the mem is initiazlied. when reset the mem in not initi…
51681 …to init upon Mem_Init_Go command. When set the mem is initiazlied. when reset the mem in not initi…
51682 …to write upon Mem_Init_Go command When set the mem is initialized with all ones. when reset the me…
51683 …to write upon Mem_Init_Go command When set the mem is initialized with all ones. when reset the me…
51684 …ly being initialized. There is status bit per mem, the following are mems 31-0: b0: qm_mem_bigram_…
51685 …ly being initialized. There is status bit per mem, the following are mems 63-32: b32: qm_mem_cfc_l…
51686 … 0x2f5d9cUL //Access:RW DataWidth:0x1 // Used to enable/disable BIST …
51688 …sed to select the BIST status word to read following the completion of a BIST test. Also used to s…
51689 … 0x2f5da8UL //Access:R DataWidth:0x16 // Provides read-only access to the BIST stat…
51936 …th:0x4 // The status of the TX PQ-s: bit0 - PQ global VP/QCN RL block; bit1 - PQ active; bit2 -…
51939 …- PQ valid; bits 8:1 - RL id; bits 17:9 - VP id (value of all ones is reserved for pure-LB VOQ …
51945 …e msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of th…
51948 …-init mode. In init mode should be written with the same value of WfqVpUpperBound. Sign: the msb i…
51951 … between VP WFQ counter and its resources as follows: bit 5:0 - Voq id; bit 9:6 - Pf id; Som…
51954 …0UL //Access:WB DataWidth:0x36 // Pointer Table Memory for TX queues 447-0; The mapping is as …
51957 …-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb i…
51958 …-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb i…
51961 …to the matched CM interface. address: 7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-…
51962 …to the matched CM interface. address: 7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-…
51964 … // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mo…
51965 …-init mode. In init mode should be written with the same value of voqinitcrdline. Granularity of 1…
51969 …it and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of …
51970 …-1-2^9. Granularity of 16B. Some VOQs are "not used" depending on the port_mode. Namely : port_mo…
51974 … // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mo…
51975 …-init mode. In init mode should be written with the same value of voqinitcrdbyte. Some VOQs are "n…
51979 …0x18 // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16.
51980 …-1-2^16. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port devi…
51984 …- VOQs [0..31]. AFullQmBypThrLineVoqMask_msb (This one) - VOQs [32..35]. Some VOQs are "not used" …
51985 …F RL mechanism per VOQ. RlPfVoqEnable - VOQs [0..31]. RlPfVoqEnable_msb (This one) …
51986 …- VOQs [0..31]. VoqCrdLineFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51987 …- VOQs [0..31]. VoqCrdByteFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending …
51988 … 0x300000UL //Access:W DataWidth:0x1 // Write one to this register will write zero to all…
51989 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
51994 …UL //Access:W DataWidth:0x1 // Writing to this register (any value) will copy the data in bu…
51996 …UL //Access:W DataWidth:0x1 // Writing to this register (any value) will copy the data in bu…
52001 …; the data in the debug_error_info address[5:3] = i is valid. By writing 1 to bit j it will clear …
52004 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52005 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52007 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52008 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52013 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52014 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52016 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52017 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52021 … 0x3000ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52022 … 0x3000d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52025 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52028 … (0x1<<0) // Signals an unknown address to the rf module.
52032 … (0x1<<2) // Fatal configuration error due to illigal comdination …
52034 … (0x1<<3) // Write to full FIFO or read fr…
52036 … (0x1<<4) // Write to full FIFO or read fr…
52038 … (0x1<<5) // Write to full FIFO or read fr…
52066 … (0x1<<0) // Signals an unknown address to the rf module.
52070 … (0x1<<2) // Fatal configuration error due to illigal comdination …
52072 … (0x1<<3) // Write to full FIFO or read fr…
52074 … (0x1<<4) // Write to full FIFO or read fr…
52076 … (0x1<<5) // Write to full FIFO or read fr…
52085 … (0x1<<0) // Signals an unknown address to the rf module.
52089 … (0x1<<2) // Fatal configuration error due to illigal comdination …
52091 … (0x1<<3) // Write to full FIFO or read fr…
52093 … (0x1<<4) // Write to full FIFO or read fr…
52095 … (0x1<<5) // Write to full FIFO or read fr…
52106 …-7). Do not read from address[3:5]=i if debug_error_data_valid[i] isn't set. Bits [2:0] in the add…
52108 … 0x300500UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
52109 … line) in the selected line (before shift).for selecting a line to output
52117 …-Initial reference tag Address offset-0 bits [31:0]; Field name-Application tag value Address offs…
52118 …- Has 8 QWORDs per task allocated (All are valid). In RDIF - Has 8 QWORDs per task allocated (QWOR…
52121 … 0x310000UL //Access:W DataWidth:0x1 // Write one to this register will write zero to all…
52122 …dth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed.
52123 …al DIF data arrived. If clear and this event occuer a fatal error will cause the DIF block to stop.
52128 …UL //Access:W DataWidth:0x1 // Writing to this register (any value) will copy the data in bu…
52130 …UL //Access:W DataWidth:0x1 // Writing to this register (any value) will copy the data in bu…
52135 …; the data in the debug_error_info address[5:3] = i is valid. By writing 1 to bit j it will clear …
52138 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52139 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52141 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52142 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52147 …ss:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - application tag; [31:16] - applica…
52148 …ess:R DataWidth:0x20 // DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calcula…
52150 … //Access:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - referance tag.
52151 …ss:R DataWidth:0x20 // DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application t…
52155 … 0x3100ccUL //Access:R DataWidth:0x1 // DEBUG: 0 - no credit; 1 - there is cred…
52156 … 0x3100d0UL //Access:R DataWidth:0x1 // DEBUG: 0 - no message pending; 1 - message …
52158 … 0x3100d8UL //Access:R DataWidth:0x1b // [3:0] - error type ([0] Writ…
52160 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52161 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52162 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52163 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52164 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52165 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52166 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52167 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52168 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52169 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52170 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52171 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52172 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52173 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52174 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52175 …UL //Access:RW DataWidth:0x20 // Number of interval with error arrived to the DIF for protocol…
52178 … (0x1<<0) // Signals an unknown address to the rf module.
52182 … (0x1<<2) // Fatal configuration error due to illigal comdination …
52184 … (0x1<<3) // Write to full FIFO or read fr…
52186 … (0x1<<4) // Write to full FIFO or read fr…
52188 … (0x1<<5) // Write to full FIFO or read fr…
52216 … (0x1<<0) // Signals an unknown address to the rf module.
52220 … (0x1<<2) // Fatal configuration error due to illigal comdination …
52222 … (0x1<<3) // Write to full FIFO or read fr…
52224 … (0x1<<4) // Write to full FIFO or read fr…
52226 … (0x1<<5) // Write to full FIFO or read fr…
52235 … (0x1<<0) // Signals an unknown address to the rf module.
52239 … (0x1<<2) // Fatal configuration error due to illigal comdination …
52241 … (0x1<<3) // Write to full FIFO or read fr…
52243 … (0x1<<4) // Write to full FIFO or read fr…
52245 … (0x1<<5) // Write to full FIFO or read fr…
52311 …-7). Do not read from address[3:5]=i if debug_error_data_valid[i] isn't set. Bits [2:0] in the add…
52313 … 0x310500UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
52314 … line) in the selected line (before shift).for selecting a line to output
52322 …- Has 8 QWORDs per task allocated (All are valid). In RDIF - Has 8 QWORDs per task allocated (QWOR…
52325 … 0x320040UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
52326 … line) in the selected line (before shift).for selecting a line to output
52335 … (0x1<<0) // Signals an unknown address to the rf module.
52341 … (0x1<<0) // Signals an unknown address to the rf module.
52344 … (0x1<<0) // Signals an unknown address to the rf module.
52372 … 0x320410UL //Access:RW DataWidth:0x5 // Number of MSB hash bits to be used for bin
52373 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52374 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52389 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52399 … 0x322040UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
52400 … line) in the selected line (before shift).for selecting a line to output
52409 … (0x1<<0) // Signals an unknown address to the rf module.
52415 … (0x1<<0) // Signals an unknown address to the rf module.
52418 … (0x1<<0) // Signals an unknown address to the rf module.
52446 … 0x322410UL //Access:RW DataWidth:0x5 // Number of MSB hash bits to be used for bin
52447 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_…
52448 …-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_…
52463 …- SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; …
52473 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
52474 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
52475 …BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from wri…
52477 … (0x1<<0) // Signals an unknown address to the rf module.
52539 …X_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for …
52607 … (0x1<<0) // Signals an unknown address to the rf module.
52669 …X_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for …
52672 … (0x1<<0) // Signals an unknown address to the rf module.
52734 …X_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for …
52765 … (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
52767 … (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descr…
52793 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/R…
52795 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
52887 … (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
52889 … (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descr…
52915 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/R…
52917 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
52948 … (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
52950 … (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descr…
52976 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/R…
52978 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53005 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53007 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53033 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53035 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53119 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53121 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53147 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53149 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53176 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53178 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53204 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53206 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53777 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53779 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53803 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53805 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53907 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53909 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53933 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53935 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53972 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
53974 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
53998 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
54000 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
54025 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
54027 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
54051 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
54053 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
54095 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
54097 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
54121 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
54123 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
54130 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
54132 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
54156 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
54158 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
54673 …0420UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54677 …0424UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54678 …0428UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54679 …042cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54731 …0430UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54783 …0434UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54835 …0438UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54839 …043cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54840 …0440UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54841 …0444UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54842 …0448UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54843 …044cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54844 …0450UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54845 …0454UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54846 …0458UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54847 …045cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
54848 …to Big RAM for RBC operations. Value of this register will be incremented by one it was done write…
54849 …der in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packet avai…
54850 … 0x340810UL //Access:RW DataWidth:0xe // Head pointer to each one of 4 free l…
54857 …e requests till reset in a case of length error other way it will continue to work as usual.::s/ST…
54858 …to total_mac_size - SUM(tc_guarantied) Reset value is right for 128B block size only. It should be…
54861 …256B block size. When unified_shared_area is 1, then the threshold applies to the common area for …
54864 …340900UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54865 …340904UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54866 …340908UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54867 …34090cUL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54868 …340910UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54869 …340914UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54870 …340918UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54871 …34091cUL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54872 …340920UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54873 …340924UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54874 …340928UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54875 …34092cUL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54876 …340930UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54877 …340934UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54878 …340938UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54879 …34093cUL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54880 …340940UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54881 …340944UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54882 …340948UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54883 …34094cUL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC.…
54920 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54921 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54922 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54923 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54924 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54925 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54926 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54927 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54928 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54929 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54930 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54931 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54932 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54933 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54934 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54935 …h:0xe // If the area guaranteed for TC of each main write client is full - the number of free b…
54936 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54937 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54938 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54939 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54940 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54941 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54942 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54943 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54944 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54945 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54946 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54947 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54948 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54949 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54950 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54951 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54952 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54953 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54954 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54955 …dth:0xe // If the area guaranteed for TC of each LB write client is full - the number of free b…
54956 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54957 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54958 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54959 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54960 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54961 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54962 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54963 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54964 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54965 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54966 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54967 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54968 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54969 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54970 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54971 …of each main write client is full - the number of free blocks in the shared and headroom areas abo…
54972 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54973 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54974 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54975 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54976 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54977 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54978 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54979 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54980 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54981 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54982 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54983 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54984 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54985 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54986 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54987 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54988 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54989 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54990 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54991 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
54992 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54993 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54994 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54995 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54996 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54997 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54998 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
54999 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55000 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55001 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55002 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55003 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55004 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55005 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55006 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55007 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55008 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55009 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55010 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55011 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55012 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55013 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55014 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55015 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55016 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55017 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55018 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55019 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55020 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55021 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55022 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55023 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55024 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55025 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55026 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55027 …/Access:RW DataWidth:0xe // If the area guaranteed for that TC is full - the number of free b…
55028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55033 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55034 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55035 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55036 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55037 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55038 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55039 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55040 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55041 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55042 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55043 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55044 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55045 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55046 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55047 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55048 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55049 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55050 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55051 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55052 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55053 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55054 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55055 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55056 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55057 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55058 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55059 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55060 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55061 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55062 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55063 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
55064 …umber of allocated blocks in each TC after asserting pause upper whih full to that TC or interrupt…
55065 …en number of allocated blocks in TC bigger lossless_threshold, if 0 - then full to that TC will b…
55066 …/d in Existance. When unified_shared_area is 1, then the threshold applies to the common area for …
55067 …/d in Existance. When unified_shared_area is 1, then the threshold applies to the common area for …
55070 …to client 0 and so on. If bit is set then packet will be read without dead cycles.B0-PRM; B1 -MSDM…
55072 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55074 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55076 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55078 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
55080 … priority then selection between them is done with RR. Possible values are 1-3. Priority 7 is high…
55082 …t 0 suits to client 0 and so on. If bit is set then packet will be written without intra packet de…
55083 …uits to client 0 and so on. If bit is set then highest priority mechanism is enabled for the corre…
55084 …taWidth:0x2 // This is priority for SOP read client to Big RAM arbiter. Possible values are 1-3…
55085 …taWidth:0x2 // This is priority for EOP read client to BIG RAM arbiters. Possible values are 0-…
55086 …s is priority for packet request of write client group to Big RAM arbiter. Possible values are 1-3…
55087 …h multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is high…
55088 …of entries inside input FIFO of each write client upper which full outputs to this write client in…
55094 …ries inside descriptors FIFO of each write client upper which full outputs to this write client in…
55095 …of entries inside queue FIFO of each write client upper which full outputs to this write client in…
55097 … // Number of packets above which BRB_above_threshold_mac_n is asserted to power management blo…
55098 …// Number of free blocks below which BRB_above_threshold_mac_n is asserted to power management blo…
55099 …W DataWidth:0x9 // Per TC enable for output BRB_above_threshold_mac_n to power management blo…
55100 …W DataWidth:0x9 // Per TC enable for output BRB_above_threshold_mac_n to power management blo…
55101 …W DataWidth:0x9 // Per TC enable for output BRB_above_threshold_mac_n to power management blo…
55102 …W DataWidth:0x9 // Per TC enable for output BRB_above_threshold_mac_n to power management blo…
55103 …upied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value…
55106 … 0x340ed0UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
55107 … line) in the selected line (before shift).for selecting a line to output
55116 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When…
55118 … (0xf<<10) // There is bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is…
55122 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
55125 …-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When…
55127 …read client interface: B0 - IF0, B1- IF1. When bit is set then appropriate interface is enabled.Wh…
55129 …is set then appropriate interface is enabled. When bit is reset then valid to that interface will …
55141 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55142 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55143 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55144 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55145 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55146 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55147 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55148 …- NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spe…
55149 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55150 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55151 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55152 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55153 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55154 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55155 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55156 …ter. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55159 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55160 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55161 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55162 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55163 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
55164 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55165 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55166 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55167 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55168 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
55169 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55170 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55171 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55172 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55173 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
55174 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55175 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
55176 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
55183 …F to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area i…
55184 …F to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area i…
55185 …F to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area i…
55186 …F to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area i…
55241 … and headroom areas. When unified_shared_area is 1, then the value applies to the common area for …
55242 … and headroom areas. When unified_shared_area is 1, then the value applies to the common area for …
55243 … and headroom areas. When unified_shared_area is 1, then the value applies to the common area for …
55244 … and headroom areas. When unified_shared_area is 1, then the value applies to the common area for …
55289 …to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according …
55291 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
55294 …nt will be copied to this register for each erad packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; …
55296 …nt will be copied to this register for each read packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; …
55298 …-port per-TC counters. In BigBear, entries 0-7 are port 0 (main 0) TCs 0-7. Entries 8-16 are port …
55301 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55303 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55305 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55307 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55309 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55311 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55313 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55315 … counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
55317 … 0x341c00UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
55318 … 0x341c04UL //Access:RW DataWidth:0x8 // command to CPU BIST
55319 … 0x341c08UL //Access:RW DataWidth:0x8 // address to CPU BIST
55330 …Access:RW DataWidth:0xe // Link list dual port memory that contains per-block descriptor::s/B…
55331 …Access:RW DataWidth:0xf // Link list dual port memory that contains per-block descriptor::s/B…
55339 … 0x4c0018UL //Access:RW DataWidth:0x2 // Selects the queue to which bypass message…
55346 … 0x4c0034UL //Access:RW DataWidth:0x2 // The QID to which the segment me…
55351 …c0048UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 1
55352 …c004cUL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 2
55353 …c0050UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 3
55354 …c0054UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 0
55355 …c0058UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 0
55356 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 1
55357 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 2
55358 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 3
55359 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 4
55360 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 5
55364 … 0x4c007cUL //Access:R DataWidth:0x9 // Number of messages pending to PCI read request
55367 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55368 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55370 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55371 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55372 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55373 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55374 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55375 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55376 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55377 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55378 …0x4c00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55379 …0x4c00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55380 …0x4c00bcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55381 …0x4c00c0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55382 … 0x4c00c4UL //Access:W DataWidth:0x1 // Writing to this register clears…
55383 …:0x8 // Logging register for segment message error: bits 3:0 - header len; bits 7:4 - number of…
55384 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 31:0 of the seg…
55385 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 63:32 of the se…
55386 … DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 95:64 of the se…
55387 … 0x4c00d8UL //Access:W DataWidth:0x1 // Writing to this register clears…
55389 … 0x4c00e0UL //Access:RC DataWidth:0x20 // Number of FIC messages sent to the loader
55392 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55394 … 0x4c00f4UL //Access:W DataWidth:0x1 // Writing to this register clears…
55397 … (0x1<<0) // Signals an unknown address to the rf module.
55399 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
55401 … (0x1<<2) // Issuese related to the seg message fields - the sum…
55403 … (0x1<<3) // Mini cache error - meaning that A load …
55405 … (0x1<<4) // Mini cache error - meaning that A load …
55423 … (0x1<<0) // Signals an unknown address to the rf module.
55425 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
55427 … (0x1<<2) // Issuese related to the seg message fields - the sum…
55429 … (0x1<<3) // Mini cache error - meaning that A load …
55431 … (0x1<<4) // Mini cache error - meaning that A load …
55436 … (0x1<<0) // Signals an unknown address to the rf module.
55438 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
55440 … (0x1<<2) // Issuese related to the seg message fields - the sum…
55442 … (0x1<<3) // Mini cache error - meaning that A load …
55444 … (0x1<<4) // Mini cache error - meaning that A load …
55521 … 0x4c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55523 … 0x4c0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55528 … (0x1<<1) // indicates not to perform the aggregat…
55530 … (0x1<<2) // defines that only back-to-back aggregation is …
55539 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
55541 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
55543 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
55545 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
55547 … DataWidth:0x10 // Limit the number of �packets� in the Loader according to the number of parent…
55549 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
55551 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
55553 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
55555 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
55558 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
55560 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
55562 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
55564 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
55567 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
55569 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
55571 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
55573 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
55576 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
55578 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
55580 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
55582 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
55618 … 0x4c0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55619 … 0x4c0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55620 … 0x4c092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55621 … 0x4c0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55622 … 0x4c0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55623 … 0x4c0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55624 … 0x4c093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55625 … 0x4c0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55626 … 0x4c0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55627 … 0x4c0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55628 … 0x4c094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55629 … 0x4c0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55630 … 0x4c0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55631 … 0x4c0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55632 … 0x4c095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55633 … 0x4c0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55634 … 0x4c0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55635 … 0x4c0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55636 … 0x4c096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55637 … 0x4c0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55638 … 0x4c0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55639 … 0x4c0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55640 … 0x4c097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55641 … 0x4c0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55642 … 0x4c0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55643 … 0x4c0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55644 … 0x4c098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55645 … 0x4c0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55646 … 0x4c0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55647 … 0x4c0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55648 … 0x4c099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55649 … 0x4c09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
55651 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
55653 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
55655 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
55657 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
55660 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
55662 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
55664 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
55666 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
55669 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
55671 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
55673 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
55675 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
55678 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
55680 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
55682 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
55684 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
55723 … (0x1<<0) // indication if to include the flow-ID in the stream-ID …
55725 … (0x1<<1) // indication if to include the flow-ID in the stream-ID …
55727 … (0x1<<2) // indication if to include the flow-ID in the stream-ID …
55729 … (0x1<<3) // indication if to include the flow-ID in the stream-ID …
55731 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
55733 … (0x1f<<9) // offset of the flow-ID, in 32b units, fro…
55735 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
55737 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
55740 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
55742 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
55744 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
55746 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
55758 … (0xff<<0) // The value by which to increment the event-ID in case…
55760 … (0xff<<8) // The value by which to increment the event-ID in case…
55762 … (0xff<<16) // The value by which to increment the event-ID in case…
55764 … (0xff<<24) // The value by which to increment the event-ID in case…
55773 … 0x4c1600UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
55774 … line) in the selected line (before shift).for selecting a line to output
55782 … 0x4c2000UL //Access:WB DataWidth:0x80 // Access to input FIC FIFO
55784 … 0x4c4000UL //Access:WB DataWidth:0x80 // Debug access to The message queue me…
55790 … 0x4c8010UL //Access:RW DataWidth:0x2 // Selects the queue to which bypass message…
55800 …c8038UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 1
55801 …c803cUL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 2
55802 …c8040UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 3
55803 …c8044UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 0
55804 …c8048UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 0
55805 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 1
55806 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 2
55807 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 3
55808 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 4
55809 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 5
55813 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55814 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55816 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55817 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55818 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55819 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55820 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55821 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55822 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55823 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55824 …0x4c8098UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55825 …0x4c809cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55826 …0x4c80a0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55827 …0x4c80a4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55828 … 0x4c80a8UL //Access:W DataWidth:0x1 // Writing to this register clears…
55829 … 0x4c80acUL //Access:RC DataWidth:0x20 // Number of FIC messages sent to the loader
55832 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55834 … 0x4c80c0UL //Access:W DataWidth:0x1 // Writing to this register clears…
55837 … (0x1<<0) // Signals an unknown address to the rf module.
55839 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
55841 … (0x1<<2) // Issuese related to the seg message fields - the sum…
55843 … (0x1<<3) // Mini cache error - meaning that A load …
55845 … (0x1<<4) // Mini cache error - meaning that A load …
55863 … (0x1<<0) // Signals an unknown address to the rf module.
55865 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
55867 … (0x1<<2) // Issuese related to the seg message fields - the sum…
55869 … (0x1<<3) // Mini cache error - meaning that A load …
55871 … (0x1<<4) // Mini cache error - meaning that A load …
55876 … (0x1<<0) // Signals an unknown address to the rf module.
55878 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
55880 … (0x1<<2) // Issuese related to the seg message fields - the sum…
55882 … (0x1<<3) // Mini cache error - meaning that A load …
55884 … (0x1<<4) // Mini cache error - meaning that A load …
55902 … 0x4c8400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
55904 … 0x4c8800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
55906 … 0x4c9600UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
55907 … line) in the selected line (before shift).for selecting a line to output
55915 … 0x4ca000UL //Access:WB DataWidth:0x80 // Access to input FIC FIFO
55917 … 0x4cc000UL //Access:WB DataWidth:0x80 // Debug access to The message queue me…
55921 … 0x4d0010UL //Access:RW DataWidth:0x2 // Selects the queue to which bypass message…
55925 …the BRB read response buffer. The slot size would be the BRB-response-buffer-size/number-of-slots.…
55928 …data returning from the BRB is swapped. meaning that bytes 0-3 is swapped with bytes 4-7 in …
55929 …30UL //Access:RW DataWidth:0x3 // Max credit number for the BRB request-resonse interface::/M…
55934 …d0044UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 1
55935 …d0048UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 2
55936 …d004cUL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 3
55937 …d0050UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 0
55938 …d0054UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 0
55939 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 1
55940 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 2
55941 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 3
55942 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 4
55943 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 5
55949 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
55950 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
55952 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55953 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55954 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55955 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
55956 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55957 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55958 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55959 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
55960 …0x4d00acUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55961 …0x4d00b0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55962 …0x4d00b4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55963 …0x4d00b8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
55964 … 0x4d00bcUL //Access:W DataWidth:0x1 // Writing to this register clears…
55965 … 0x4d00c0UL //Access:RC DataWidth:0x20 // Number of FIC messages sent to the loader
55968 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
55970 … 0x4d00d4UL //Access:W DataWidth:0x1 // Writing to this register clears…
55973 … (0x1<<0) // Signals an unknown address to the rf module.
55975 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
55977 … (0x1<<2) // Issuese related to the seg message fields - the sum…
55979 … (0x1<<3) // Mini cache error - meaning that A load …
55981 … (0x1<<4) // Mini cache error - meaning that A load …
55999 … (0x1<<0) // Signals an unknown address to the rf module.
56001 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
56003 … (0x1<<2) // Issuese related to the seg message fields - the sum…
56005 … (0x1<<3) // Mini cache error - meaning that A load …
56007 … (0x1<<4) // Mini cache error - meaning that A load …
56012 … (0x1<<0) // Signals an unknown address to the rf module.
56014 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
56016 … (0x1<<2) // Issuese related to the seg message fields - the sum…
56018 … (0x1<<3) // Mini cache error - meaning that A load …
56020 … (0x1<<4) // Mini cache error - meaning that A load …
56083 … 0x4d0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56085 … 0x4d0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56090 … (0x1<<1) // indicates not to perform the aggregat…
56092 … (0x1<<2) // defines that only back-to-back aggregation is …
56101 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
56103 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
56105 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
56107 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
56109 … DataWidth:0x10 // Limit the number of �packets� in the Loader according to the number of parent…
56111 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
56113 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
56115 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
56117 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
56120 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
56122 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
56124 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
56126 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
56129 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
56131 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
56133 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
56135 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
56138 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
56140 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
56142 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
56144 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
56180 … 0x4d0924UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56181 … 0x4d0928UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56182 … 0x4d092cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56183 … 0x4d0930UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56184 … 0x4d0934UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56185 … 0x4d0938UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56186 … 0x4d093cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56187 … 0x4d0940UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56188 … 0x4d0944UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56189 … 0x4d0948UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56190 … 0x4d094cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56191 … 0x4d0950UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56192 … 0x4d0954UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56193 … 0x4d0958UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56194 … 0x4d095cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56195 … 0x4d0960UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56196 … 0x4d0964UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56197 … 0x4d0968UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56198 … 0x4d096cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56199 … 0x4d0970UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56200 … 0x4d0974UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56201 … 0x4d0978UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56202 … 0x4d097cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56203 … 0x4d0980UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56204 … 0x4d0984UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56205 … 0x4d0988UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56206 … 0x4d098cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56207 … 0x4d0990UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56208 … 0x4d0994UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56209 … 0x4d0998UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56210 … 0x4d099cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56211 … 0x4d09a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56213 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
56215 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
56217 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
56219 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
56222 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
56224 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
56226 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
56228 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
56231 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
56233 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
56235 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
56237 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
56240 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
56242 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
56244 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
56246 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
56285 … (0x1<<0) // indication if to include the flow-ID in the stream-ID …
56287 … (0x1<<1) // indication if to include the flow-ID in the stream-ID …
56289 … (0x1<<2) // indication if to include the flow-ID in the stream-ID …
56291 … (0x1<<3) // indication if to include the flow-ID in the stream-ID …
56293 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
56295 … (0x1f<<9) // offset of the flow-ID, in 32b units, fro…
56297 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
56299 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
56302 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
56304 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
56306 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
56308 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
56320 … (0xff<<0) // The value by which to increment the event-ID in case…
56322 … (0xff<<8) // The value by which to increment the event-ID in case…
56324 … (0xff<<16) // The value by which to increment the event-ID in case…
56326 … (0xff<<24) // The value by which to increment the event-ID in case…
56335 … 0x4d1600UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
56336 … line) in the selected line (before shift).for selecting a line to output
56344 … 0x4d2000UL //Access:WB DataWidth:0x80 // Access to input FIC FIFO
56346 … 0x4d4000UL //Access:WB DataWidth:0x80 // Debug access to The message queue me…
56353 … 0x4e0014UL //Access:RW DataWidth:0x4 // Log 2 of the BD size in bytes - 2:BD size is 4bytes;…
56355 …0x4e001cUL //Access:RW DataWidth:0x4 // Log 2 of the SGE size in bytes - 2:SGE size is 4bytes…
56360 … 0x4e0030UL //Access:RW DataWidth:0x2 // Selects the queue to which bypass message…
56371 …e005cUL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 1
56372 …e0060UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 2
56373 …e0064UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 3
56374 …e0068UL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 0
56375 …e006cUL //Access:RC DataWidth:0x20 // Statistics counter of message pending to external event 0
56376 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 1
56377 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 2
56378 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 3
56379 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 4
56380 …Access:R DataWidth:0x9 // Counts the number of messages currently pending to external event 5
56382 … 0x4e0088UL //Access:R DataWidth:0x9 // Number of messages pending to BD fetch
56383 … 0x4e008cUL //Access:R DataWidth:0x9 // Number of messages pending to SGE fetch
56386 … 0x4e0098UL //Access:R DataWidth:0x9 // Number of messages pending to PCI read request
56389 …// Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_…
56390 …// Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_…
56392 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56393 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56394 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56395 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
56396 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56397 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56398 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56399 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
56400 …0x4e00d0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56401 …0x4e00d4UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56402 …0x4e00d8UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56403 …0x4e00dcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
56404 … 0x4e00e0UL //Access:W DataWidth:0x1 // Writing to this register clears…
56405 … 0x4e00e4UL //Access:RC DataWidth:0x20 // Number of FIC messages sent to the loader
56408 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
56410 … 0x4e00f8UL //Access:W DataWidth:0x1 // Writing to this register clears…
56413 … (0x1<<0) // Signals an unknown address to the rf module.
56415 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
56417 … (0x1<<2) // Issuese related to the seg message fields - the sum…
56419 … (0x1<<3) // Mini cache error - meaning that A load …
56421 … (0x1<<4) // Mini cache error - meaning that A load …
56439 … (0x1<<0) // Signals an unknown address to the rf module.
56441 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
56443 … (0x1<<2) // Issuese related to the seg message fields - the sum…
56445 … (0x1<<3) // Mini cache error - meaning that A load …
56447 … (0x1<<4) // Mini cache error - meaning that A load …
56452 … (0x1<<0) // Signals an unknown address to the rf module.
56454 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
56456 … (0x1<<2) // Issuese related to the seg message fields - the sum…
56458 … (0x1<<3) // Mini cache error - meaning that A load …
56460 … (0x1<<4) // Mini cache error - meaning that A load …
56557 … 0x4e0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
56559 … 0x4e0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access.
56561 … 0x4e0c00UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue2 - Debug access::/TMLD_…
56563 … 0x4e1000UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue3 - Debug access::/TMLD_…
56568 … (0x1<<1) // indicates not to perform the aggregat…
56570 … (0x1<<2) // defines that only back-to-back aggregation is …
56579 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
56581 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
56583 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
56585 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
56587 … DataWidth:0x10 // Limit the number of �packets� in the Loader according to the number of parent…
56589 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
56591 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
56593 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
56595 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
56598 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
56600 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
56602 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
56604 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
56607 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
56609 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
56611 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
56613 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
56616 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
56618 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
56620 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
56622 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
56658 … 0x4e1424UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56659 … 0x4e1428UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56660 … 0x4e142cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56661 … 0x4e1430UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56662 … 0x4e1434UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56663 … 0x4e1438UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56664 … 0x4e143cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56665 … 0x4e1440UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56666 … 0x4e1444UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56667 … 0x4e1448UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56668 … 0x4e144cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56669 … 0x4e1450UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56670 … 0x4e1454UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56671 … 0x4e1458UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56672 … 0x4e145cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56673 … 0x4e1460UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56674 … 0x4e1464UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56675 … 0x4e1468UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56676 … 0x4e146cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56677 … 0x4e1470UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56678 … 0x4e1474UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56679 … 0x4e1478UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56680 … 0x4e147cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56681 … 0x4e1480UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56682 … 0x4e1484UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56683 … 0x4e1488UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56684 … 0x4e148cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56685 … 0x4e1490UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56686 … 0x4e1494UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56687 … 0x4e1498UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56688 … 0x4e149cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56689 … 0x4e14a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
56691 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
56693 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
56695 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
56697 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
56700 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
56702 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
56704 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
56706 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
56709 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
56711 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
56713 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
56715 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
56718 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
56720 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
56722 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
56724 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
56763 … (0x1<<0) // indication if to include the flow-ID in the stream-ID …
56765 … (0x1<<1) // indication if to include the flow-ID in the stream-ID …
56767 … (0x1<<2) // indication if to include the flow-ID in the stream-ID …
56769 … (0x1<<3) // indication if to include the flow-ID in the stream-ID …
56771 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
56773 … (0x1f<<9) // offset of the flow-ID, in 32b units, fro…
56775 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
56777 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
56780 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
56782 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
56784 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
56786 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
56798 … (0xff<<0) // The value by which to increment the event-ID in case…
56800 … (0xff<<8) // The value by which to increment the event-ID in case…
56802 … (0xff<<16) // The value by which to increment the event-ID in case…
56804 … (0xff<<24) // The value by which to increment the event-ID in case…
56808 … 0x4e1600UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
56809 … line) in the selected line (before shift).for selecting a line to output
56817 … 0x4e2000UL //Access:WB DataWidth:0x80 // Access to input FIC FIFO
56819 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56823 …- Fields order[Link page]: [180] Next address valid; [179:178] Endianity bits; [177] No snoop flag…
56827 … 0x4f0000UL //Access:WB DataWidth:0x80 // Debug access to The message queue me…
56830 … (0x1<<0) // Signals an unknown address to the RF module.
56888 … (0x1<<0) // Signals an unknown address to the RF module.
56917 … (0x1<<0) // Signals an unknown address to the RF module.
57206 … (0x1<<0) // Error in the pure-loopback SOPQ.
57296 … (0x1<<0) // Error in the pure-loopback SOPQ.
57341 … (0x1<<0) // Error in the pure-loopback SOPQ.
57534 … (0x1<<0) // Error in the pure-loopback SOPQ.
57624 … (0x1<<0) // Error in the pure-loopback SOPQ.
57669 … (0x1<<0) // Error in the pure-loopback SOPQ.
57862 … (0x1<<0) // Error in the pure-loopback SOPQ.
57952 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
57997 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58190 … (0x1<<0) // Error in the pure-loopback SOPQ.
58280 …_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
58325 …2_E5 (0x1<<0) // Error in the pure-loopback SOPQ.
59324 …-gate function disable bit: 0 - egress drain mode is enabled when close-gate input from MISC to N…
59331 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
59332 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
59333 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
59334 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
59335 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
59336 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
59337 … 0x500834UL //Access:RW DataWidth:0x1 // Direct all management traffic to BMB toward MCP.
59338 …RX packets. 0 is for XSTORM; 1 is for YSTORM. This configuration should be static during run-time.
59339 …nd YSEM. Read this register to get the current credit count on the interface. This configuration s…
59341 … (0xff<<0) // Event ID to be used in CM header for packets forwarded …
59343 … (0x1<<8) // T-bit to be used in CM header for packets forward…
59345 … (0x1<<9) // DstStormFlg to be used in CM header for packets forwarded …
59347 … (0x1<<10) // ConnectionDomainExist to be used in CM header for packets forwarded …
59349 …to drop the per-PF drop and per-VPORT drop packets or forward the packet to the destination with t…
59350 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59351 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59352 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59353 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59354 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59355 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59356 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59357 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59358 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59359 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59360 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59361 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59362 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59363 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59364 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59365 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59366 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59367 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59368 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59369 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59370 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59371 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59372 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59373 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59374 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59375 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59376 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59377 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59378 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59379 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59380 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59381 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59382 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59383 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59384 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59385 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59386 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59387 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59388 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59389 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59390 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59391 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59392 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59393 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59394 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59395 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59396 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59397 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59398 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59399 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59400 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59401 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59402 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59403 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59404 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59405 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59406 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59407 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59408 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59409 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59410 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59411 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59412 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59413 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59414 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59415 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59416 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59417 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59418 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59419 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59420 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59421 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59422 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59423 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59424 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59425 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59426 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59427 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59428 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59429 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59430 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59431 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59432 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59433 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59434 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59435 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59436 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59437 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59438 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59439 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59440 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59441 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59442 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59443 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59444 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59445 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59446 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59447 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59448 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59449 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59450 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59451 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59452 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59453 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59454 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59455 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59456 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59457 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59458 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59459 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59460 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59461 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59462 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59463 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59464 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59465 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59466 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59467 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59468 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59469 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59470 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59471 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59472 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59473 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59474 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59475 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59476 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59477 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59478 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59479 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59480 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59481 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59482 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59483 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59484 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59485 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59486 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59487 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59488 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59489 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59490 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59491 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59492 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59493 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59494 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59495 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59496 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59497 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59498 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59499 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59500 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59501 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59502 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59503 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59504 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59505 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59506 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59507 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59508 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59509 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59510 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59511 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59512 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59513 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59514 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59515 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59516 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59517 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59518 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59519 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59520 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59521 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59522 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59523 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59524 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59525 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59526 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59527 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59528 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59529 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59530 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59531 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59532 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59533 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59534 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59535 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59536 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59537 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59538 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59539 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59540 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59541 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59542 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59543 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59544 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59545 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59546 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59547 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59548 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59549 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59550 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59551 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59552 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59553 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59554 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59555 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59556 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59557 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
59558 …s:RW DataWidth:0x1 // Per-PF drop configuration to be used for main and LB traffic of all por…
59561 …0cUL //Access:R DataWidth:0x18 // TX SOP descriptor queue empty status - for main traffic que…
59562 …c10UL //Access:R DataWidth:0x18 // TX SOP descriptor queue full status - for main traffic que…
59563 … DataWidth:0x40 // Addresses for TimeSync related registers in the timesync generator sub-module.
59567 …1 // Output enable for the STORM interface. This configuration should be static during run-time.
59568 … 0x500e0cUL //Access:RW DataWidth:0x1 // Output enable of message to PXP IF.
59571 … 0x500e18UL //Access:RW DataWidth:0x1 // Output enble for RX path to BRB.
59572 … 0x500e1cUL //Access:RW DataWidth:0x1 // Output enable for LB path to BRB.
59573 … 0x500e20UL //Access:RW DataWidth:0x1 // Output enable for flow control interfaces to the MAC.
59577 … 0x500e4cUL //Access:R DataWidth:0x1 // TX FIFO for transmitting data to MAC is almost full.
59578 … 0x500e50UL //Access:R DataWidth:0x1 // TX FIFO for transmitting data to MAC is empty.
59579 … 0x500f00UL //Access:R DataWidth:0x1 // TX FIFO for transmitting data to MAC is full.
59580 …-bit words, that is present at the start of the packet. This configuration applies to all packets…
59581 …t of the packet, to pass to the frame crackers in LLHs. The actual size passed to LLH is the enti…
59582 …cess:RW DataWidth:0x1 // Packet has Ethernet FCS field. Set this bit to indicate that the pa…
59586 …-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer tag);…
59587 … 0x50101cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59588 … 0x501020UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59589 …Access:RW DataWidth:0x8 // Bit-map indicating which L2 hdrs may appear after L2 tag 1. Reset…
59590 … 0x501028UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59591 … 0x50102cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59592 … 0x501030UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59593 … 0x501034UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59594 …-map indicating which L2 hdrs may appear after the basic Ethernet header. Bit 0-tag0 (outer tag);…
59595 … 0x50103cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59596 … 0x501040UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59597 …Access:RW DataWidth:0x8 // Bit-map indicating which L2 hdrs may appear after L2 tag 1. Reset…
59598 … 0x501048UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59599 … 0x50104cUL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59600 … 0x501050UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59601 … 0x501054UL //Access:RW DataWidth:0x8 // Bit-map indicating which …
59603 …) // Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation. This enables the comparison of the …
59605 …0x1<<1) // Enable bit for IP-over-GRE (IP GRE) encapsulation. This enables the comparison of the …
59607 …psulation. This enables the comparison of the UDP destination port number to the configured *vxla…
59610 … 0x501060UL //Access:RW DataWidth:0x10 // Ethertype for IPv4 packets. Defaults to 0x0800.
59611 … 0x501064UL //Access:RW DataWidth:0x10 // Ethertype for IPv6 packets. Defaults to 0x86DD.
59612 … 0x501068UL //Access:RW DataWidth:0x10 // FCOE Ethertype - default is 0x8906.
59613 … 0x50106cUL //Access:RW DataWidth:0x10 // Ethertype for RoCE packets. Defaults to 0x8915.
59617 … 0x50107cUL //Access:RW DataWidth:0x8 // IPv4 protocol field for ICMPv4 - defaults to 0x01.
59618 … 0x501080UL //Access:RW DataWidth:0x8 // IPv6 next header field for ICMPv6 - defaults to 0x3A.
59637 …to be compared with for NCSI outer tag rules that are enabled by *llh_ncsi_*_mask_otag0 mask bits.…
59638 …to be compared with for NCSI outer tag rules that are enabled by *llh_ncsi_*_mask_otag1 mask bits.…
59651 …cess:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_0: 0 - IPv6; 1-I…
59652 …cess:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_1: 0 - IPv6; 1-I…
59653 …cess:RW DataWidth:0x1 // Determine the IP version to look for in llh_dest_ip_2: 0 - IPv6; 1-I…
59661 … (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to MCP.
59663 …warding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to MCP.
59667 …// Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to MCP.
59669 … (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to MCP.
59671 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_0 to MCP.
59673 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_1 to MCP.
59675 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_2 to MCP.
59677 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_3 to MCP.
59679 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_4 to MCP.
59681 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_5 to MCP.
59683 … (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to MCP.
59685 …ask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
59687 … (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and Bcast address to MCP.
59689 …destination address matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to MCP.
59691 …destination address matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to MCP.
59693 …destination address matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to MCP.
59695 … // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to MCP.
59697 … // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to MCP.
59699 … // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to MCP.
59705 … // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to MCP.
59707 … // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to MCP.
59709 … // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to MCP.
59711 … (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to MCP.
59713 … (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to MCP.
59719 …vertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to MCP.
59721 …dvertisement packets (ICMP over IPv6 with ICMP type= 134 and dst_mac = 0x33:33:00:00:00:01) to MCP.
59723 … (0x1<<31) // Mask bit for forwarding ICMPv6 packets to MCP.
59726 … (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to MCP.
59728 … (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to MCP.
59730 …(0x1<<2) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to MCP.
59732 …(0x1<<3) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to MCP.
59734 …(0x1<<4) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to MCP.
59737 … (0x1<<0) // Mask bit for forwarding packets with outer tag present to MCP.
59739 … (0x1<<1) // Mask bit for forwarding packets with no outer tag to MCP.
59741 … (0x1<<2) // Mask bit for forwarding packets with the outer tag matching *outer_tag_id0 to MCP.
59743 … (0x1<<3) // Mask bit for forwarding packets with the outer tag matching *outer_tag_id1 to MCP.
59745 … bit for forwarding packets with outer tag matching the outer tag of one of the enabled PFs to MCP.
59748 … (0x1<<0) // Mask bit for forwarding packets with Ethertype matching llh_arp_type to MCP.
59750 …1) // Mask bit for forwarding IPv4 packets with protocol field matching llh_icmpv4_protocol to MCP.
59752 …// Mask bit for forwarding IPv6 packets with next header field matching llh_icmpv6_protocol to MCP.
59754 … (0x1<<3) // Mask bit for forwarding ICMPv4 packets with ICMP type 8 to MCP.
59756 … (0x1<<4) // Mask bit for forwarding ICMPv6 packets with ICMP type 128 to MCP.
59758 … (0x1<<5) // Mask bit for forwarding ICMPv6 packets with ICMP type 135 to MCP.
59760 …ing packets from all PFs, including packets that failed PF classification, to MCP in multifunction…
59761 …1 // Enable bit for forwarding packets for each PF to MCP in multifunction mode. This is a per…
59763 … // Mask bit for not forwarding broadcast (MAC destination address of all 1's) packets to the host.
59765 …ng multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to the host.
59769 …it for not forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the host.
59771 …x1<<4) // Mask bit for not forwarding unicast (MAC destination address[40]==0) packets to the host.
59773 …for not forwarding packets with the MAC destination address matching *llh*_dest_mac_0 to the host.
59775 …for not forwarding packets with the MAC destination address matching *llh*_dest_mac_1 to the host.
59777 …for not forwarding packets with the MAC destination address matching *llh*_dest_mac_2 to the host.
59779 …for not forwarding packets with the MAC destination address matching *llh*_dest_mac_3 to the host.
59781 …for not forwarding packets with the MAC destination address matching *llh*_dest_mac_4 to the host.
59783 …for not forwarding packets with the MAC destination address matching *llh*_dest_mac_5 to the host.
59785 …x1<<11) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype0 to the host.
59787 …bit for not forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
59789 …<13) // Mask bit for not forwarding packets with Ethertype of 0x0806 and bcast address to the host.
59791 …nation address matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the host.
59793 …nation address matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the host.
59795 …nation address matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the host.
59797 …bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the host.
59799 …bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the host.
59801 …bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the host.
59807 …bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the host.
59809 …bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the host.
59811 …bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the host.
59813 …(0x1<<25) // Mask bit for not forwarding packets with RMCP UDP ports (0x26f and 0x298) to the host.
59815 …) // Mask bit for not forwarding packets with NetBIOS UDP destination port 137/138/139 to the host.
59821 …sement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the host.
59823 …sement packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the host.
59825 … (0x1<<31) // Mask bit for not forwarding ICMPv6 packets to the host.
59828 … (0x1<<0) // Mask bit for not forwarding packets with inner VLAN present to the host.
59830 … (0x1<<1) // Mask bit for not forwarding packets with no inner VLAN to the host.
59832 …// Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the host.
59834 …// Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the host.
59836 …// Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the host.
59839 … (0x1<<0) // Mask bit for not forwarding packets with outer tag present to the host.
59841 … (0x1<<1) // Mask bit for not forwarding packets with no outer tag to the host.
59843 …<<2) // Mask bit for not forwarding packets with the outer tag matching *outer_tag_id0 to the host.
59845 …<<3) // Mask bit for not forwarding packets with the outer tag matching *outer_tag_id1 to the host.
59847 …not forwarding packets with outer tag matching the outer tag of one of the enabled PFs to the host.
59850 … (0x1<<0) // Mask bit for not forwarding packets with Ethertype matching llh_arp_type to the host.
59852 …k bit for not forwarding IPv4 packets with protocol field matching llh_icmpv4_protocol to the host.
59854 …it for not forwarding IPv6 packets with next header field matching llh_icmpv6_protocol to the host.
59856 … (0x1<<3) // Mask bit for not forwarding ICMPv4 packets with ICMP type 8 to the host.
59858 … (0x1<<4) // Mask bit for not forwarding ICMPv6 packets with ICMP type 128 to the host.
59860 … (0x1<<5) // Mask bit for not forwarding ICMPv6 packets with ICMP type 135 to the host.
59862 …ing packets from all PFs, including packets that failed PF classification, to the host in multifun…
59863 …/ Enable bit for not forwarding packets for the PF to the host in multifunction mode. This is a p…
59885 … (0x1<<0) // L2 filter rule enable. Set this bit to enable this rule.
59889 …for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
60005 … (0x1<<0) // L2 filter (for not forwarding to the host) rule enable. Set this bit to …
60007 … (0x1<<1) // L2 filter (for not forwarding to the host) address ma…
60009 …to the host) address select for choosing one of the *llh_l2filt_mac_da* configurations for compari…
60011 … (0x1<<5) // L2 filter (for not forwarding to the host) Ethertype …
60013 … (0x7<<6) // L2 filter (for not forwarding to the host) Ethertype …
60124 …idth:0x1 // Disable bit for forwarding packets to the host for this port. No packet is forward…
60125 … DataWidth:0x1 // Disable bit for forwarding packets to the host. No packet is forwarded to B…
60126 …g packets that failed PF classification to the host. No packet with classification failed status …
60127 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60128 … 0x5011f8UL //Access:RW DataWidth:0x10 // Ethertype for filtering packets to the STORM(s).
60129 … 0x5011fcUL //Access:RW DataWidth:0x10 // Ethertype for filtering packets to the STORM(s).
60130 … 0x501200UL //Access:RW DataWidth:0x10 // Ethertype for filtering packets to the STORM(s).
60131 … 0x501204UL //Access:RW DataWidth:0x10 // Ethertype for filtering packets to the STORM(s).
60133 …0) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype0 to the STORM(s).
60135 …1) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype1 to the STORM(s).
60137 …2) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype2 to the STORM(s).
60139 …3) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype3 to the STORM(s).
60147 …- message FIFO empty. Bit 1 - descriptor FIFO empty. Bit 2 - message FIFO has more than 32 entries…
60148 …-to-send data remaining below which ETS arbiter for the LB path should start selecting the next pa…
60149 …cess:RW DataWidth:0x1 // Packet has Ethernet FCS field. Set this bit to indicate that the pa…
60150 …-padding enable for LB packets. Set this bit to enable the padding of short packets to 60B. When…
60152 …<<0) // Enable bit for the BRB interface rate limiter to be used in pacing LB traffic. Default to…
60156 … DataWidth:0x20 // Increment PERIOD for the BRB interface rate limiter - in term of 25MHz clo…
60157 …- in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the …
60158 … DataWidth:0x20 // Upper bound VALUE for the BRB interface rate limiter - in term of bytes, cy…
60159 …L //Access:RW DataWidth:0x8 // Value to be added to the packet size for the BRB interface rat…
60161 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. D…
60163 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60166 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. D…
60168 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60171 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. D…
60173 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60176 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. D…
60178 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60181 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. D…
60183 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60186 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. D…
60188 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60191 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. D…
60193 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60196 … (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic. D…
60198 …<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter. 0 s…
60200 …40UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60201 …44UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60202 …48UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60203 …4cUL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60204 …50UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60205 …54UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60206 …58UL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60207 …5cUL //Access:RW DataWidth:0x20 // Increment PERIOD for the per-TC rate limiter - in term of …
60208 …-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configurat…
60209 …-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configurat…
60210 …-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configurat…
60211 …-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configurat…
60212 …-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configurat…
60213 …-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configurat…
60214 …-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configurat…
60215 …-TC rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configurat…
60216 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60217 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60218 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60219 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60220 …0UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60221 …4UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60222 …8UL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60223 …cUL //Access:RW DataWidth:0x20 // Upper bound VALUE for the per-TC rate limiter - in term of …
60224 …5015a0UL //Access:RW DataWidth:0x8 // Value to be added to the packet size for the rate limit…
60225 …5015a4UL //Access:RW DataWidth:0x8 // Value to be added to the packet size for the rate limit…
60226 …5015a8UL //Access:RW DataWidth:0x8 // Value to be added to the packet size for the rate limit…
60227 …5015acUL //Access:RW DataWidth:0x8 // Value to be added to the packet size for the rate limit…
60228 …5015b0UL //Access:RW DataWidth:0x8 // Value to be added to the packet size for the rate limit…
60229 …5015b4UL //Access:RW DataWidth:0x8 // Value to be added to the packet size for the rate limit…
60230 …5015b8UL //Access:RW DataWidth:0x8 // Value to be added to the packet size for the rate limit…
60231 …5015bcUL //Access:RW DataWidth:0x8 // Value to be added to the packet size for the rate limit…
60232 …to client ID (client IDs are defined in *_arb_priority_client): 0-management; 1-TC0 traffic; 2-TC…
60233 …to WFQ credit blocking. The bits are mapped according to client ID (client IDs are defined in *_a…
60234 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60235 …to be assigned to each priority of the strict priority arbiter. Priority 0 is the highest priorit…
60237 …to have the round-robin arbiter stays on the winning input instead of moving to the next one. Bit…
60238 … // Specify the number of bytes to be deducted from the client credit register at the time of gr…
60239 … 0x5015e0UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mo…
60240 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 0 is allowed to reach.
60241 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 1 is allowed to reach.
60242 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 2 is allowed to reach.
60243 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 3 is allowed to reach.
60244 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 4 is allowed to reach.
60245 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 5 is allowed to reach.
60246 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 6 is allowed to reach.
60247 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 7 is allowed to reach.
60248 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 8 is allowed to reach.
60249 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 9 is allowed to reach.
60250 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 0 when it is tim…
60251 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 1 when it is tim…
60252 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 2 when it is tim…
60253 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 3 when it is tim…
60254 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 4 when it is tim…
60255 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 5 when it is tim…
60256 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 6 when it is tim…
60257 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 7 when it is tim…
60258 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 8 when it is tim…
60259 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 9 when it is tim…
60260 …0x501634UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60261 …0x501638UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60262 …0x50163cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60263 …0x501640UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60264 …0x501644UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60265 …0x501648UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60266 …0x50164cUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60267 …0x501650UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60268 …0x501654UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60269 …0x501658UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in LB arbit…
60270 … DataWidth:0x1 // Disable bit for forwarding packets to the host. No packet is forwarded to B…
60271 …g packets that failed PF classification to the host. No packet with classification failed status …
60272 …-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that …
60289 …ote that for HW to detect PTP packet and extract data from the packet, at least one of the version…
60290 …ote that for HW to detect PTP packet and extract data from the packet, at least one of the version…
60291 … 0x501908UL //Access:RW DataWidth:0x1 // Set to 1 to enable PTP packets to be forwarded t…
60292 … 0x50190cUL //Access:RW DataWidth:0x1 // Set to 1 to enable PTP packets to be forwarded t…
60293 …-specified packet timestamp mode. NIG will capture the timestamp value of the packet that SW indi…
60294 …ype 1 for PTP packet detection. Ethertype 0 is fixed at 0x88F7. This register defaults to 0x88f7.
60295 …AC destination address 1 is fixed at 0x0180_C200_000E. This register defaults to 0x011B_1900_0000.
60296 …AC destination address 1 is fixed at 0x0180_C200_000E. This register defaults to 0x011B_1900_0000.
60297 …to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.1…
60298 …to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2-{IP…
60299 …to 1 to mask out the particular parameter. 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.1…
60300 …to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1-{IPv4 DA 0; UDP DP 1} . 2-{IP…
60301 …1-deep FIFOs for the host. Bits [15:0] return the sequence ID of the packet. Bit 16 indicates th…
60302 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60303 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
60304 …in 1-deep FIFOs for MCP. Bits [15:0] return the sequence ID of the packet. Bit 16 indicates the …
60305 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60306 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFOs for MCP. …
60307 …-deep FIFOs for TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 indicates the…
60308 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60309 …s:R DataWidth:0x20 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
60310 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60311 …-bit time for the 64-bit timestamp value. Error occurs when bits [31:30] of the MAC timestamp val…
60312 … // Multifunction mode enable. Set this bit to perform PF classification before sending the pa…
60313 … based on protocol. 3: dual-stage classification. When no classification is performed in multifunc…
60314 …to select the resolution method for combining the results from the two stages in dual-stage classi…
60315 …Default per-port value to be used when protocol-based classification fails. This is the per-port …
60316 …lt per-port value to be used when outer-tag/inner VLAN/MAC classification fails. This is the per…
60317 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60318 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60319 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60320 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60321 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60322 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60323 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60324 …-bit PPFID to 4-bit global PFID. Each port supports 8 functions. These 8 functions are locally re…
60325 …to specify the index of the 64-bit field immediately following the Ethertype to be used for each o…
60329 …uter tag value mask. Set a bit to 0 to mask out the corresponding bit of the outer tag value. Th…
60330 …-port per-PF register. This register selects the classification type for the tag/VLAN/MAC mode. …
60331 … 0x5019b0UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60333 … // This is a per-port per-PF register. Per-function select bit for choosing between the tunnel …
60335 …-port per-PF register. Per-function outer tag/inner VLAN configuration for PF classification. Th…
60337 … // This is a per-port per-PF register. Per-function no outer tag/inner VLAN configuration for …
60338 …er-port per-PF register. Per-function MAC addresses to be matched with for MAC-address-based clas…
60340 … 0x501a80UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Per-function…
60342 …-port per-PF register. Per-function mode select bit to indicate whether the filter is to be used …
60344 …-port per-PF register. Per-function select bits for the different protocol types to be evaluated …
60346 … a per-port per-PF register. Per-function select bit for choosing between the tunnel and encapsul…
60348 …e. 0 selects connection-based classification. 1 selects the PF-based classification. This regist…
60349 …-tuple search for TCP packets. Set this bit to use the TCP 4-tuple (TCP source and destination po…
60350 …-tuple search for UDP packets. Set this bit to use the UDP 4-tuple (UDP source and destination po…
60351 …he CRC8 function used to hash the data string in connection-based engine classification. This reg…
60352 …-entry Engine ID lookup table, with 1 bit per entry. Set the bit to 1 to have packets associated …
60354 …ts one of the 24-bit destination QP bits to be used as the engine ID. Valid values are 0-23. Thi…
60355 …-global-PF engine ID to be used in PF-based engine classification. Set the bit to 1 to have packe…
60356 …ss:RW DataWidth:0x3 // Flow control mode. 0 - disable; 1 - PFC; 2 - LLFC; 3 - PPP; 4 - PAUSE…
60357 …taWidth:0x20 // Eight 4-bit configurations for specifying which TC (0-15 for future expansion) e…
60359 …to be used for extracting the packet priority information. Valid values are 2-5 for selecting one…
60361 … (0xf<<3) // Bit offset in the outer tag starting from which to extract the 3-bit packet pr…
60363 … (0xf<<7) // Bit offset in the selected tag starting from which to extract the 3-bit packet pr…
60365 …to both RX and LB interfaces to the BRB of the same port. Set a bit to 1 to force 'full' conditio…
60366 …to BRB. There is one bit per TC and the same configuration is applicable to both RX and LB interf…
60367 …:RW DataWidth:0x8 // Per-TC flow control enable for received XOFF requests to pause transmit …
60368 … //Access:RW DataWidth:0x8 // Per-TC flow control enable for XOFF messages sent to the MAC. …
60369 …ess:RW DataWidth:0x9 // Per-TC flow control enable for received XOFF requests to pause LB que…
60370 …DataWidth:0x1 // Enable bit for the no-drop-hdr-ind field of the LB-only-header. When set, the…
60371 …-drop of LB packets with the no-drop-hdr-ind bit set due to per-TC full backpressure from the BRB.…
60372 …-bit cycles, starting from the SOP cycle, of the packet not to be dropped due to no_drop_on_full. …
60373 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60374 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60375 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60376 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60377 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60378 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60379 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60380 …th:0x10 // Flow control priorities used for each TC. This register is bit-mapped with one bit f…
60381 …-map indicating which received SAFC/PFC priorities to map to the TC. A priority is mapped to the …
60382 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60383 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60384 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60385 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60386 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60387 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60388 …-map indicating which SAFC/PFC priorities to map to the TC. A priority is mapped to the TC when t…
60393 …able. Set this bit to enable drain mode. Drain mode starts immediately upon assertion and stops a…
60394 …to enable drain mode. Drain mode starts immediately upon assertion and stops at the next packet b…
60395 …to enable the drain mode for TC0 and TC7. Bit 0 is for TC0 flow. Bit 7 is for TC7 flow. When ena…
60396 …to enable the drain mode for TC0 and TC7. Bit 0 is for TC0 flow. Bit 8 is for TC8 flow. When ena…
60397 … LLFC messages to the MAC. The value is in term of the number of core clock cycles. The timer st…
60398 … //Access:RW DataWidth:0xa // Number of cycles between 2 LLFC request to the MAC; The minimum…
60404 …ataWidth:0x10 // Current value of PFC/LLFC priority or PAUSE signal sent to MAC/PXP, depending o…
60406 … 0x501c50UL //Access:RW DataWidth:0x1 // Set this bit to clear the current fl…
60407 …to be used in the header of the flow control message sent to PXP internal write interface. This c…
60408 …to be used for the Destination Client ID field for the header of the flow control message sent to …
60409 … flow control message sent to PXP internal write interface. This configuration should be static wh…
60410 …to be used in the header of the flow control message sent to PXP internal write interface. This co…
60411 …4UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60412 …8UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60413 …cUL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60414 …0UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60415 …4UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60416 …8UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60417 …cUL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60418 …0UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60419 …01ca0UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60421 …01ca8UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60423 …01cb0UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60425 …01cb8UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60427 …01cc0UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60429 …01cc8UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60431 …01cd0UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60433 …01cd8UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60435 …ce0UL //Access:RC DataWidth:0x20 // Statistics for packets dropped due to minimum size, parsin…
60436 …he number of single-cycle packets dropped. This is an RF generated RC statistics register - readin…
60437 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60438 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60439 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60440 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60441 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60442 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60443 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60444 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60445 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60446 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60447 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60448 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60449 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60450 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60451 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60452 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60453 …28UL //Access:RC DataWidth:0x20 // Statistics for the number of packets forwarded to the STORM.
60454 …M that are dropped due to buffer full. This is an RF generated RC statistics register - reading t…
60455 …that are truncated due to buffer full. This is an RF generated RC statistics register - reading t…
60456 …0UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60457 …4UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60458 …8UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60459 …cUL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60460 …0UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60461 …4UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60462 …8UL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60463 …cUL //Access:RC DataWidth:0x20 // Statistics for the number of packets to be routed toward the…
60464 …01d60UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60466 …01d68UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60468 …01d70UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60470 …01d78UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60472 …01d80UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60474 …01d88UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60476 …01d90UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60478 …01d98UL //Access:ST DataWidth:0x40 // Statistics for the number octets to be routed toward the…
60480 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60481 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60482 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60483 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60484 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60485 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60486 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60487 …cess:RC DataWidth:0x20 // Statistics for the number of packets being truncated due to BRB full.
60488 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60489 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60490 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60491 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60492 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60493 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60494 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60495 …ss:RC DataWidth:0x20 // Statistics for the number of packets discarded due to BRB backpressure.
60496 …de0UL //Access:RC DataWidth:0x20 // Statistics for packets dropped due to minimum size, parsin…
60497 …he number of single-cycle packets dropped. This is an RF generated RC statistics register - readin…
60498 …packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the MCP/per-TC dra…
60499 …of TX packets that have the per-PF drop or per-VPORT drop configuration set. These packets may be …
60500 …B packets dropped, due to the drop bit, the per-PF drop, the per-VPORT drop, and the per-TC drain…
60501 …-PF drop or per-VPORT drop configuration set while the no-drop-hdr-ind in the packet is cleared. T…
60558 … 0x501ed8UL //Access:RC DataWidth:0x20 // Number of RX octets to be forwarded to BMB.
60559 … 0x501edcUL //Access:RC DataWidth:0x20 // Number of RX packets to be forwarded to BMB.
60560 …ccess:RC DataWidth:0x20 // Number of RX packets to be forwarded to BMB that got truncated due …
60561 …ccess:RC DataWidth:0x20 // Number of RX packets to be forwarded to BMB that got discarded due …
60562 … 0x501ee8UL //Access:RC DataWidth:0x20 // Number of TX octets to be forwarded to BMB.
60563 … 0x501eecUL //Access:RC DataWidth:0x20 // Number of TX packets to be forwarded to BMB.
60564 …ccess:RC DataWidth:0x20 // Number of TX packets to be forwarded to BMB that got truncated due …
60565 …ccess:RC DataWidth:0x20 // Number of TX packets to be forwarded to BMB that got discarded due …
60566 …aWidth:0x20 // Statistics for the number of packets received from BMB for sending to the network.
60567 …L //Access:RC DataWidth:0x20 // Number of packets received from BMB for forwarding to the host.
60568 …aWidth:0x20 // Number of packets from BMB to be forwarded to the host that got truncated due to …
60569 …taWidth:0x20 // Number of packets from BMB to be forwarded to the host that got dropped due to B…
60570 …ess:RW DataWidth:0x1 // Zero-padding enable for TX packets. Set this bit to enable the paddi…
60574 … EDPM. There is one bit per TC. This is used in the generation of the EDPM enable output to DORQ.
60576 …-to-transmit data remaining below which ETS arbiter for the transmit path should start selecting …
60580 …// Enable bit for the global rate limiter to be used in pacing TX and LB traffic of the same port.…
60584 …ccess:RW DataWidth:0x20 // Increment PERIOD for the global rate limiter - in term of 25MHz clo…
60585 …- in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the …
60586 …cess:RW DataWidth:0x20 // Upper bound VALUE for the global rate limiter - in term of bytes, cy…
60587 …501f2cUL //Access:RW DataWidth:0x8 // Value to be added to the packet size for the rate limit…
60589 …to client ID (client IDs are defined in *_arb_priority_client): 0-DORQ; 1-management; 2-debug tra…
60590 …to WFQ credit blocking. The bits are mapped according to client ID (client IDs are defined in *_a…
60591 …-robin arbitration slots to avoid starvation. A value of 0 means no strict priority cycles - the …
60592 …to be assigned to each priority of the strict priority arbiter. Priority 0 is the highest priorit…
60594 …to have the round-robin arbiter stays on the winning input instead of moving to the next one. Bit…
60595 … // Specify the number of bytes to be deducted from the client credit register at the time of gr…
60596 … 0x501f50UL //Access:RW DataWidth:0x1 // Enable bit for the pseudo-random arbitration mo…
60597 …501f54UL //Access:RW DataWidth:0x1 // Set this bit to disable debug traffic at the inputs to …
60598 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 0 is allowed to reach.
60599 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 1 is allowed to reach.
60600 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 2 is allowed to reach.
60601 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 3 is allowed to reach.
60602 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 4 is allowed to reach.
60603 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 5 is allowed to reach.
60604 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 6 is allowed to reach.
60605 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 7 is allowed to reach.
60606 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 8 is allowed to reach.
60607 …Access:RW DataWidth:0x20 // Specify the upper bound that credit register 9 is allowed to reach.
60608 …ccess:RW DataWidth:0x20 // Specify the upper bound that credit register 10 is allowed to reach.
60609 …ccess:RW DataWidth:0x20 // Specify the upper bound that credit register 11 is allowed to reach.
60610 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 0 when it is tim…
60611 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 1 when it is tim…
60612 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 2 when it is tim…
60613 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 3 when it is tim…
60614 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 4 when it is tim…
60615 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 5 when it is tim…
60616 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 6 when it is tim…
60617 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 7 when it is tim…
60618 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 8 when it is tim…
60619 … DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 9 when it is tim…
60620 …DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 10 when it is tim…
60621 …DataWidth:0x20 // Specify the weight (in bytes) to be added to credit register 11 when it is tim…
60622 …0x501fb8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60623 …0x501fbcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60624 …0x501fc0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60625 …0x501fc4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60626 …0x501fc8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60627 …0x501fccUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60628 …0x501fd0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60629 …0x501fd4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60630 …0x501fd8UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60631 …0x501fdcUL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60632 …0x501fe0UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60633 …0x501fe4UL //Access:R DataWidth:0x20 // Current upper 32 bits of the 33-bit value in TX arbit…
60635 … (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to MCP.
60637 …warding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to MCP.
60641 …// Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to MCP.
60643 … (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to MCP.
60645 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_0 to MCP.
60647 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_1 to MCP.
60649 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_2 to MCP.
60651 … Mask bit for forwarding packets with the MAC destination address mtching *llh*_dest_mac_3 to MCP.
60653 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_4 to MCP.
60655 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_5 to MCP.
60657 … (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to MCP.
60659 …ask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
60661 … (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and bcast address to MCP.
60663 …destination address matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to MCP.
60665 …destination address matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to MCP.
60667 …destination address matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to MCP.
60669 … // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to MCP.
60671 … // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to MCP.
60673 … // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to MCP.
60679 … // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to MCP.
60681 … // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to MCP.
60683 … // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to MCP.
60685 … (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to MCP.
60687 … (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to MCP.
60693 …vertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to MCP.
60695 …dvertisement packets (ICMP over IPv6 with ICMP type= 134 and dst_mac = 0x33:33:00:00:00:01) to MCP.
60697 … (0x1<<31) // Mask bit for forwarding ICMPv6 packets to MCP.
60700 … (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to the network.
60702 … (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to the network.
60704 … // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the network.
60706 … // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the network.
60708 … // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the network.
60711 … Mask bit for not forwarding broadcast (MAC destination address of all 1's) packets to the network.
60713 …multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to the network.
60717 …for not forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the network.
60719 …<4) // Mask bit for not forwarding unicast (MAC destination address[40]==0) packets to the network.
60721 … not forwarding packets with the MAC destination address matching *llh*_dest_mac_0 to the network.
60723 … not forwarding packets with the MAC destination address matching *llh*_dest_mac_1 to the network.
60725 … not forwarding packets with the MAC destination address matching *llh*_dest_mac_2 to the network.
60727 … not forwarding packets with the MAC destination address matching *llh*_dest_mac_3 to the network.
60729 … not forwarding packets with the MAC destination address matching *llh*_dest_mac_4 to the network.
60731 … not forwarding packets with the MAC destination address matching *llh*_dest_mac_5 to the network.
60733 …<11) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype0 to the network.
60735 … for not forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the network.
60737 …) // Mask bit for not forwarding packets with Ethertype of 0x0806 and bcast address to the network.
60739 …ion address matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the network.
60741 …ion address matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the network.
60743 …ion address matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the network.
60745 … for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the network.
60747 … for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the network.
60749 … for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the network.
60755 … for not forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the network.
60757 … for not forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the network.
60759 … for not forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the network.
60761 …1<<25) // Mask bit for not forwarding packets with RMCP UDP ports (0x26f and 0x298) to the network.
60763 …/ Mask bit for not forwarding packets with NetBIOS UDP destination port 137/138/139 to the network.
60769 …ent packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the network.
60771 …ent packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the network.
60773 … (0x1<<31) // Mask bit for not forwarding ICMPv6 packets to the network.
60776 …) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to the network.
60778 …ing multicast (MAC destination address[40]==1 and it is a broadcast packet) packets to the network.
60782 …bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the network.
60784 …0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to the network.
60786 … for forwarding packets with the MAC destination address matching *llh*_dest_mac_0 to the network.
60788 … for forwarding packets with the MAC destination address matching *llh*_dest_mac_1 to the network.
60790 … for forwarding packets with the MAC destination address matching *llh*_dest_mac_2 to the network.
60792 … for forwarding packets with the MAC destination address matching *llh*_dest_mac_3 to the network.
60794 … for forwarding packets with the MAC destination address matching *llh*_dest_mac_4 to the network.
60796 … for forwarding packets with the MAC destination address matching *llh*_dest_mac_5 to the network.
60798 …0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to the network.
60800 … bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the network.
60802 …<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and bcast address to the network.
60804 …ion address matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the network.
60806 …ion address matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the network.
60808 …ion address matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the network.
60810 … bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the network.
60812 … bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the network.
60814 … bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the network.
60820 … bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the network.
60822 … bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the network.
60824 … bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the network.
60826 … (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to the network.
60828 …6) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to the network.
60834 …ent packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the network.
60836 …ent packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the network.
60838 … (0x1<<31) // Mask bit for forwarding ICMPv6 packets to the network.
60841 … (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to the network.
60843 … (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to the network.
60845 … // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the network.
60847 … // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the network.
60849 … // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the network.
60867 … 0x50203cUL //Access:RW DataWidth:0x20 // Value of outer tag to be inserted into the…
60868 … 0x502040UL //Access:RW DataWidth:0x20 // Value of outer tag to be inserted into the…
60869 … 0x502044UL //Access:RW DataWidth:0x20 // Value of outer tag to be inserted into the…
60870 … 0x502048UL //Access:RW DataWidth:0x20 // Value of outer tag to be inserted into the…
60871 …ner VLAN tag to be used in tag insertion/override for management packets. This field consists of …
60872 …ner VLAN tag to be used in tag insertion/override for management packets. This field consists of …
60873 … 0x502054UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60874 … 0x502058UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60875 … 0x50205cUL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60876 … 0x502060UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60877 … 0x502064UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60878 … 0x502068UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60879 … 0x50206cUL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60880 … 0x502070UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60881 … 0x502074UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60882 … 0x502078UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60883 … 0x50207cUL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60884 … 0x502080UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60885 … 0x502084UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60886 … 0x502088UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60887 … 0x50208cUL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60888 … 0x502090UL //Access:RW DataWidth:0x20 // Value of proprietary header to be inserted into the…
60889 …to be used for management traffic. This is used in the BMC-to-host path to BRB. This is also use…
60890 …to control the flow of TX management traffic. Set this bit to 1 to enable the use of *mng_tc conf…
60891 …-to-MCP path enable. Set this bit to enable the routing of management packets from PBF interface …
60892 … 0x5020a0UL //Access:RW DataWidth:0x1 // Indicate to timestamp the packet from MCP to net…
60893 … //Access:RW DataWidth:0x1 // Enable the usage of BMB WC pause inputs to OR with others for p…
60895 … 0x5020acUL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
60900 … 0x5020c0UL //Access:RW DataWidth:0x7 // Almost-full threshold for DO…
60903 …cket for transmission. This is applicalbe to packets longer than this many cycles. The valid val…
60904 …. 0 - send debug traffic through port 0. 1 - send debug traffic through port 1. 2 - send debug tr…
60906 …cket for transmission. This is applicalbe to packets longer than this many cycles. The valid val…
60907 … 0x5020dcUL //Access:RW DataWidth:0x8 // Almost-full threshold for de…
60910 …to RX LLH through RBC. The bits are mapped as follow: [255:0] data; [260:256]eop_bvalid - the num…
60912 … 0x502140UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
60913 … line) in the selected line (before shift).for selecting a line to output
60921 … 0x502188UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
60922 … line) in the selected line (before shift).for selecting a line to output
60926 … 0x50219cUL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
60927 … line) in the selected line (before shift).for selecting a line to output
60931 … 0x5021b0UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
60932 … line) in the selected line (before shift).for selecting a line to output
60936 … 0x5021c4UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
60937 … line) in the selected line (before shift).for selecting a line to output
60941 … 0x5021d8UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
60942 … line) in the selected line (before shift).for selecting a line to output
60946 … 0x5021ecUL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
60947 … line) in the selected line (before shift).for selecting a line to output
60953 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
60954 …er-port per-PF register. Proprietary header removal configuration for ACPI. Set this bit to 1 to…
60955 …Width:0x1 // Set this bit to enable ACPI pattern matching and TCP SYN matching in multi-functio…
60956 …to enable ACPI and TCP SYN matching even when the packet is forwarded to MCP. Clear this bit to d…
60957 … 0x508080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
60959 … 0x508100UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
60960 … 0x508104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60961 … 0x508108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60962 … 0x50810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60963 … 0x508110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60964 … 0x508114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60965 … 0x508118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60966 … 0x50811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60967 … 0x508120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60968 … 0x508124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60969 … 0x508128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60970 … 0x50812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60971 … 0x508130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60972 … 0x508134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60973 … 0x508138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60974 … 0x50813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
60975 … 0x508140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
60976 …W DataWidth:0x2 // This is a per-port per-PF register. Set bit 0 to enable wake on IPv4 TCP …
60977 …-port per-PF register. Enable bits for fields to be compared if IPv6 is present in the packet. B…
60978 …-port per-PF register. Enable bits for fields to be compared if IPv4 is present in the packet. B…
60979 … 0x508150UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60980 … 0x508154UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60981 … 0x508158UL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. IPv…
60982 … 0x50815cUL //Access:RW DataWidth:0x10 // This is a per-port per-PF register. TCP…
60983 … 0x508160UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60985 … 0x508170UL //Access:WB DataWidth:0x80 // This is a per-port per-PF register. IPv…
60987 … 0x508180UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60988 … 0x508184UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. IPv…
60989 … 0x508188UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
60990 … 0x508190UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
60992 … 0x508198UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high …
60993 … 0x5081a0UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
60995 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
60996 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
60997 … 0x5081c8UL //Access:R DataWidth:0xe // Wake packet length - the actual length of…
60998 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
60999 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFOs for the ho…
61001 …s:WB_R DataWidth:0x50 // Packet TimeSync information that is buffered in 1-deep FIFO for the TX …
61015 …ess:RW DataWidth:0x1 // This bit defines whether to add offset and jitter of the timestamp to…
61017 …cess:RW DataWidth:0x3 // Selector for the 48 bits timer which is sent to the port macro. 0: f…
61018 …0885cUL //Access:RW DataWidth:0x3 // Selects which timer will be sent to SEMI/MCP 0: free run…
61019 …to outgoing packet 1: ETHERTYPE � insert timestamp if EtherType filter had a hit 2: UDP � insert t…
61021 … Correction field offset for user protocol packets. the offset is relative to the configured value…
61022 …RW DataWidth:0x5 // Global timestamp shift for the free running counter. Legal values are 0-16
61023 … 0x508870UL //Access:RW DataWidth:0x1 // Output enable for TS passed to the Port Macro
61024 … 0x508874UL //Access:RW DataWidth:0x1 // Output enable for TS passed to the Port Macro
61025 … // Global parameter which defines that 32 bits timestamp will be inserted to the packet instead o…
61026 …-deep FIFOs. Bits [15:0] return the sequence ID of the packet which is set by free running counte…
61027 …ataWidth:0x40 // RX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61029 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Source add…
61031 …-deep FIFOs. Bits [15:0] return the sequence ID of the packet which is set by free running counte…
61032 …ataWidth:0x40 // TX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp …
61034 …ataWidth:0x30 // RX user protocol packet information that is buffered in 1-deep FIFO. Destinatio…
61036 …32 bit LSB of the configured free counter. The value is written to the HW when writing to the MSB …
61037 …s register contains the 32 bit MSB of the configured free counter. Writing to this register also u…
61038 …e. This value is added to the Free Running Counter to create the synchronized time. The value is w…
61039 …to the Free Running Counter to create the synchronized time. Writing to this register also updatea…
61041 … counter width is 64 bits, tsgen_freecnt_lsb should be read first in order to latch the counter's …
61043 …d time width is 64 bits, tsgen_sync_time_lsb should be read first in order to latch the counter's …
61044 …d are all configurable, and when asserting this bit the PPS starts to toggle accoring to HW machine
61048 … 0x5088d8UL //Access:RW DataWidth:0x1 // This is a level indication to reset drift counter'…
61049 …to wait before making a Drift adjustment to the TSGEN_OFFSET_T0 register. The drift frequency has …
61050 … 0x5088e0UL //Access:RW DataWidth:0x4 // Bits 3:0 are the active-low output enables fo…
61052 …FO data bytes occupancy is higher than this threshold nig_dorq_edpm_en is de-asserted. The value i…
61053 …:RW DataWidth:0x8 // This field sets message type value in ICMP header to identify MLD packets
61054 …to ROCE/RROCE: bit 0 marks that packet should be duplicated to host and Storm when BTH opcode equa…
61056 …ess:RW DataWidth:0x1 // This field enables the feature that maps DSCP to TC in case that ther…
61057 …0x508900UL //Access:RW DataWidth:0x4 // This field maps Port PF (PPF) to engine selection for…
61059 …aWidth:0x6 // This field maps (ipv4_tos >> 2) 6 bits to 6 bits: bits 5:3 - priority bits 2:0 - …
61061 … 0x508b00UL //Access:RW DataWidth:0x1 // This field defines whether to ignore zero UDP valu…
61062 … 0x508b04UL //Access:RW DataWidth:0x1 // This field defines whether to ignore zero UDP valu…
61063 … 0x508b08UL //Access:RW DataWidth:0x1 // This field defines whether to ignore zero UDP valu…
61065 …-port register L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L2 tags 0…
61066 … a per-port register. Proprietary header removal configuration for ACPI. Set this bit to 1 to en…
61067 …This is a per-port register. When enabled, NIG will check Ethernet CRC in the packet and update e…
61068 …th:0x1 // This is a per-port register. When enabled, NIG will remove Ethernet CRC from the pac…
61069 …-port register. When enabled, it indicates that the CNIG will add ethernet CRC to the packet. In …
61070 … 0x508b24UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
61071 … 0x508b28UL //Access:RW DataWidth:0x1 // This is a per-port register. Enabl…
61072 … 0x508b2cUL //Access:RW DataWidth:0x1 // This is a per-port register. Enable…
61073 …8b30UL //Access:RW DataWidth:0x1 // This is a per-port register. Perform NGE version match t…
61074 …x508b34UL //Access:RW DataWidth:0x10 // This is a per-port register. Next protocol value to b…
61075 …b38UL //Access:RW DataWidth:0x10 // This is a per-port register. Destination port value used t…
61076 … DataWidth:0x18 // This is a per-port register which defines mapping of TC from the received T…
61080 … (0x1<<0) // Mask bit for forwarding IPV6 MLD (configurable MLD MsgType) packets to MCP.
61082 … (0x1<<1) // Mask bit for forwarding IPv6 Neighbor solicitation packets to MCP.
61084 … (0x1<<2) // Mask bit for forwarding IPv6 DHCP server packets to MCP.
61086 …T (0x1<<3) // Mask bit for forwarding DCHPv4 client packets to MCP.
61088 …_SERVER (0x1<<4) // Mask bit for forwarding DHCP V4 packets to MCP.
61090 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_6 to MCP.
61092 …Mask bit for forwarding packets with the MAC destination address matching *llh*_dest_mac_7 to MCP.
61094 … (0x1<<7) // Mask bit for forwarding IPv6 DHCP multicast server to client packets to MCP.
61097 … (0x1<<0) // Mask bit for forwarding unicast IPv6 MLD (Configurable MsgType) packets to MCP.
61099 … (0x1<<1) // Mask bit for forwarding IPv6 neighbor solicitation packets to MCP.
61101 … (0x1<<2) // Mask bit for forwarding DHCP V6 server packets to MCP.
61103 … (0x1<<3) // Mask bit for forwarding DHCP V4 client packets to MCP.
61105 … (0x1<<4) // Mask bit for forwarding DHCP V4 server packets to MCP.
61107 … (0x1<<7) // Mask bit for forwarding DHCP V6 multicast server to client packets to MCP.
61110 … (0x1<<0) // Mask bit for not forwarding IPv6 MLD (Configurable MsgType) packets to the host.
61112 … (0x1<<1) // Mask bit for not forwarding IPv6 neighbor solicitation packets to the host.
61114 …ERVER (0x1<<2) // Mask bit for not forwarding DHCP V6 server packets to the host.
61116 …LIENT (0x1<<3) // Mask bit for not forwarding DHCP V4 client packets to the host.
61118 …ERVER (0x1<<4) // Mask bit for not forwarding DHCP V4 server packets to the host.
61120 …for not forwarding packets with the MAC destination address matching *llh*_dest_mac_6 to the host.
61122 …for not forwarding packets with the MAC destination address matching *llh*_dest_mac_7 to the host.
61124 … (0x1<<7) // Mask bit for not forwarding DHCP V6 multicast server to client packets to the host.
61127 … (0x1<<0) // Mask bit for not forwarding IPv6 MLD (Configurable MsgType) packets to the network.
61129 … (0x1<<1) // Mask bit for not forwarding IPv6 neighbor solicitation packets to the network.
61131 …RVER (0x1<<2) // Mask bit for not forwarding DHCP V6 server packets to the network.
61133 …IENT (0x1<<3) // Mask bit for not forwarding DHCP V4 client packets to the network.
61135 …RVER (0x1<<4) // Mask bit for not forwarding DHCP V4 server packets to the network.
61137 … (0x1<<7) // Mask bit for not forwarding DHCP V6 multicast server to client packets to the network.
61140 … (0x1<<0) // Mask bit for forwarding IPv6 MLD (Configurable MsgType) packets to the network.
61142 … (0x1<<1) // Mask bit for forwarding IPv6 neighbor solicitation packets to the network.
61144 … (0x1<<2) // Mask bit for forwarding DHCP V6 server packets to the network.
61146 … (0x1<<3) // Mask bit for forwarding DHCP V4 client packets to the network.
61148 … (0x1<<4) // Mask bit for forwarding DHCP V4 server packets to the network.
61150 … (0x1<<7) // Mask bit for forwarding DHCP V6 multicast server to client packets to the network.
61152 …the entries to the debug mux Were not written as the FIFO was full. This indication will be valid …
61159 … bit is set and there is a parity error on the Tranmit data path, the data to the CNIG will be dis…
61160 …taWidth:0x8 // This field defines the amount of time that the interface to the CNIG will be clo…
61161 …he DORQ request to one of the credit reisters. This enables credit sharing with one of the BTB TCs…
61162 …agement request to one of the credit reisters. This enables credit sharing with one of the BTB TCs…
61163 …g of the management request to one of the credit reisters. This enables credit sharing with one of…
61164 …1 // This bit inhibits sending more than one outstanding packet request to the BMB until the la…
61165 …1 // This bit inhibits sending more than one outstanding packet request to the BMB until the la…
61166 … 0x509000UL //Access:RW DataWidth:0x1 // When this bit is configured to 1, NIG trasmits port…
61167 … 0x509004UL //Access:RW DataWidth:0x1 // When this bit is configured to 1, NIG trasmits port…
61168 … 0x509008UL //Access:RW DataWidth:0x3 // Writing to this register: Bit 0…
61169 …dth:0x2 // This register selects which timer will be used as the source to PPS logic of nig_ifm…
61170 …dth:0x2 // This register selects which timer will be used as the source to PPS logic of nig_ifm…
61171 …dth:0x2 // This register selects which timer will be used as the source to PPS logic of nig_ifm…
61172 …dth:0x2 // This register selects which timer will be used as the source to PPS logic of nig_ifm…
61173 …ataWidth:0x4 // This register selects which TSIO Input signals are used to latch the synchroniz…
61185 …0904cUL //Access:RW DataWidth:0x3 // Selects which timer will be sent to PXP 0: free running …
61192 …idth:0x1 // This bit selects whether to use the MPA CRC calculation on one fully contained PDU …
61193 … pool of 512 MAC addresses to be matched with for MAC-address-based classification. This register…
61197 …to indicate whether the filter is to be used for MAC-addresss based classification or protocol-bas…
61199 …to be evaluated in protocol-based classification mode: bit 0: compare the Ethertype; bit 1: compar…
61201 …choosing between the tunnel and encapsulated header from which to take the MAC address to be compa…
61203 …ccess:RW DataWidth:0x5 // This fields maps between sets of 16 filters to the PPF that uses th…
61205 …setting. When configured to 1, it means that the packet will be sent to MCP and not BMC. The bits …
61206 …setting. When configured to 1, it means that the packet will be sent to MCP and not BMC. The bits …
61207 …:RW DataWidth:0x1 // Per-VPORT drop configuration to be used for main and LB traffic of all p…
61209 … 0x50d800UL //Access:RW DataWidth:0x6 // Almost-full threshold for BM…
61214 … 0x50d814UL //Access:RW DataWidth:0x14 // mpls_ipv4_label to be compared Vs the l…
61215 … 0x50d818UL //Access:RW DataWidth:0x14 // mpls_ipv6_label to be compared Vs the l…
61216 …50d81cUL //Access:RW DataWidth:0x1 // mpls_ipv6_label/mpls_ipv4_label to be compared Vs the l…
61219 …0x50d828UL //Access:RW DataWidth:0x1 // compare the GRE version field to the gre_version regi…
61220 …0x50d82cUL //Access:RW DataWidth:0x3 // compare the GRE version field to gre_version register…
61253 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
61254 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
61255 …BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from wri…
61257 … (0x1<<0) // Signals an unknown address to the rf module.
61287 …X_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for …
61323 … (0x1<<0) // Signals an unknown address to the rf module.
61353 …X_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for …
61356 … (0x1<<0) // Signals an unknown address to the rf module.
61386 …X_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for …
61415 … (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
61417 … (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descr…
61441 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/R…
61443 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
61529 … (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
61531 … (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descr…
61555 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/R…
61557 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
61586 … (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
61588 … (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descr…
61612 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/R…
61614 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
61639 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
61641 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
61665 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
61667 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
61745 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
61747 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
61771 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
61773 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
61798 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
61800 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
61824 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
61826 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
62797 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
62799 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
62823 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
62825 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
62927 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
62929 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
62953 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
62955 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
62992 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
62994 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63018 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63020 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63045 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63047 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63071 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63073 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63097 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63099 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63175 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63177 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63201 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63203 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63227 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63229 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63240 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63242 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63266 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63268 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63292 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63294 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63319 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63321 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63469 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63471 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63544 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write c…
63546 … E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descr…
63869 …0420UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63870 …0424UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63871 …0428UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63872 …042cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63873 …0430UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63874 …0434UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63875 …0438UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63876 …043cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63877 …0440UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63878 …0444UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63879 …0448UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63880 …044cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63881 …0450UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63882 …0454UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63883 …0458UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63884 …045cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
63985 …to Big RAM for RBC operations. Value of this register will be incremented by one it was done write…
63986 …der in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packet avai…
63987 … 0x540810UL //Access:RW DataWidth:0xb // Head pointer to each one of 4 free l…
63994 …e requests till reset in a case of length error other way it will continue to work as usual.::s/ST…
63995 …to total_mac_size - SUM(tc_guarantied) Reset value is right for 128B block size only. It should be…
63996 …256B block size. When unified_shared_area is 1, then the threshold applies to the common area for …
63997 …540850UL //Access:RW DataWidth:0xb // The number of blocks guaranteed to each TC in each MAC.…
63998 …540854UL //Access:RW DataWidth:0xb // The number of blocks guaranteed to each TC in each MAC.…
63999 …540858UL //Access:RW DataWidth:0xb // The number of blocks guaranteed to each TC in each MAC.…
64000 …54085cUL //Access:RW DataWidth:0xb // The number of blocks guaranteed to each TC in each MAC.…
64001 …540860UL //Access:RW DataWidth:0xb // The number of blocks guaranteed to each TC in each MAC.…
64002 …540864UL //Access:RW DataWidth:0xb // The number of blocks guaranteed to each TC in each MAC.…
64009 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64010 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64011 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64012 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64013 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64014 …dth:0xb // If the area guaranteed for TC of each LB write client is full - the number of free b…
64015 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64016 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64017 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64018 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64019 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64020 …C of each LB write client is full - the number of free blocks in the shared and headroom areas abo…
64021 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64022 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64023 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64024 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64025 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64026 …/Access:RW DataWidth:0xb // If the area guaranteed for that TC is full - the number of free b…
64027 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64028 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64029 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64030 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64031 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64032 …-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will …
64033 …to client 0 and so on. If bit is set then packet will be read without dead cycles.TBD ::s/NO_DEAD_…
64035 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64037 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64039 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64041 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64043 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64045 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64047 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64049 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64051 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64053 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
64055 …DataWidth:0xa // There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. …
64056 …DataWidth:0xa // There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. …
64057 …taWidth:0x2 // This is priority for SOP read client to Big RAM arbiter. Possible values are 1-3…
64058 …s is priority for packet request of write client group to Big RAM arbiter. Possible values are 1-3…
64059 …h multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is high…
64060 …of entries inside input FIFO of each write client upper which full outputs to this write client in…
64066 …ries inside descriptors FIFO of each write client upper which full outputs to this write client in…
64067 …of entries inside queue FIFO of each write client upper which full outputs to this write client in…
64069 …W DataWidth:0x6 // Per TC enable for output BRB_above_threshold_mac_n to power management blo…
64070 …L //Access:RW DataWidth:0xb // Per COS threshold. BRTB indicates full to CPMU if one of the C…
64071 …L //Access:RW DataWidth:0xb // Per COS threshold. BRTB indicates full to CPMU if one of the C…
64072 …L //Access:RW DataWidth:0xb // Per COS threshold. BRTB indicates full to CPMU if one of the C…
64073 …L //Access:RW DataWidth:0xb // Per COS threshold. BRTB indicates full to CPMU if one of the C…
64074 …L //Access:RW DataWidth:0xb // Per COS threshold. BRTB indicates full to CPMU if one of the C…
64075 …L //Access:RW DataWidth:0xb // Per COS threshold. BRTB indicates full to CPMU if one of the C…
64076 …upied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value…
64079 … 0x540a7cUL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
64080 … line) in the selected line (before shift).for selecting a line to output
64089 …C_PKT_INP_IF_RST/15/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser…
64093 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
64096 …to that interface will never be asserted. All bits of this register should be set after init proce…
64098 …is set then appropriate interface is enabled. When bit is reset then valid to that interface will …
64106 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64107 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64108 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64109 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64110 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64111 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64112 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64113 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64114 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64115 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
64128 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64129 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64130 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64131 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64132 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64133 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64134 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64135 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64136 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64137 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
64138 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64139 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64140 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64141 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64142 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64143 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64144 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64145 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64146 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64147 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
64148 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64149 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64150 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64151 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64152 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64153 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64154 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64155 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64156 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64157 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
64158 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64159 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
64160 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
64247 … and headroom areas. When unified_shared_area is 1, then the value applies to the common area for …
64250 …to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according …
64252 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
64254 …st from read client will be copied to this register for each erad packet client interface: TBD. Me…
64257 …st from read client will be copied to this register for each read packet client interface: TBD. Me…
64280 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
64284 …is connected and BMB WC9/RC2 is connected to NCSI. When this bit is cleared, then MCP second IF is…
64285 … 0x560000UL //Access:RW DataWidth:0x1 // Initiate the ATC array - reset all the valid …
64287 …taWidth:0x20 // Logging register for reuse miss on transpend entry [31:0] - TID of the problemat…
64288 …taWidth:0x1c // Logging register for reuse miss on transpend entry [27:0] - ATC page index of th…
64289 …gister for reuse miss on transpend entry [11:0] - Reuse count of the problematic lookuprequest [23…
64290 …ster for the case of invalidation halt (lkpres of invalidated range) [31:0] - TID of the problemat…
64291 …ster for the case of invalidation halt (lkpres of invalidated range) [27:0] - ATC page index of th…
64292 …ster for the case of invalidation halt (lkpres of invalidated range) [11:0] - Reuse count of the p…
64294 …s of the PXP read requests issued by the PTU logic. [0:8] - ST index; [10:9] - ST hint; [11] - ST …
64300 …:R DataWidth:0x10 // Counter for the number of PTU requests to addresses belongs to ongoing i…
64301 … 0x560078UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per PF.
64304 …aWidth:0x1 // Bit per PF. Indicates that the marked invalidation is done - when read it is also…
64305 …it per PF. If set, the block halts in case it gets PTU requests to an address belongs to a range w…
64306 … 0x56008cUL //Access:RW DataWidth:0x1 // When set - the block will halt …
64307 … 0x560090UL //Access:RW DataWidth:0x3 // Max credits of the PBF->PXP interface.
64308 … 0x560094UL //Access:RW DataWidth:0x3 // Max credits of the PRM->PXP interface.
64309 … 0x560098UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64310 … 0x56009cUL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64311 … 0x5600a0UL //Access:RW DataWidth:0x3 // Max credits of the PTU->PXP interface.
64320 …00c4UL //Access:RW DataWidth:0x1 // Replacement mode for the ATC. If de-asserted then low pri…
64327 … 0x560100UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
64328 … line) in the selected line (before shift).for selecting a line to output
64337 … (0x1<<0) // Signals an unknown address to the rf module.
64339 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend stat…
64343 … (0x1<<3) // RCPL arrives to an entry with empty …
64347 … (0x1<<5) // Indicates Lookup to invalidated range wi…
64349 … (0x1<<6) // Indicates Lookup to entry markes as tran…
64371 … (0x1<<0) // Signals an unknown address to the rf module.
64373 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend stat…
64377 … (0x1<<3) // RCPL arrives to an entry with empty …
64381 … (0x1<<5) // Indicates Lookup to invalidated range wi…
64383 … (0x1<<6) // Indicates Lookup to entry markes as tran…
64388 … (0x1<<0) // Signals an unknown address to the rf module.
64390 … (0x1<<1) // TCPL arrives to an entry not in Trans-Pend stat…
64394 … (0x1<<3) // RCPL arrives to an entry with empty …
64398 … (0x1<<5) // Indicates Lookup to invalidated range wi…
64400 … (0x1<<6) // Indicates Lookup to entry markes as tran…
64477 …00UL //Access:RW DataWidth:0x2 // Defines the number of sets - 3 - 512 ;2- 256; 1- 128; 0- 64.
64483 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64484 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64485 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64486 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64487 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64488 …-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same.…
64489 …to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-S…
64490 …to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-S…
64491 …to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-S…
64492 …to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-S…
64493 …to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-S…
64494 …to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-S…
64498 …1 below the configured value, but 4 request still can be received when the register configured to 6
64500 … 0x56045cUL //Access:RW DataWidth:0x1 // Allows the ATC to return Wait response.
64509 … 0x560480UL //Access:RW DataWidth:0x1 // CheckTags configuration bit - when set the availab…
64510 … 0x560484UL //Access:RW DataWidth:0x8 // TAG threshold - for the checkTags fe…
64521 … 0x5604b0UL //Access:RW DataWidth:0x8 // Number of cycles between one scrub event to another.
64523 … 0x5604b8UL //Access:RC DataWidth:0x20 // Number of hits for Main-lookups in the ATC.
64525 … 0x5604c0UL //Access:RC DataWidth:0x20 // Number of treqs issued due to pre-lookup.
64571 … 0x560578UL //Access:R DataWidth:0x19 // Data belongs to an erroneous TCPL: […
64572 … 0x56057cUL //Access:R DataWidth:0x20 // Data belongs to an erroneous TCPL: [31:0]-bits [3…
64573 … 0x560580UL //Access:R DataWidth:0x14 // Data belongs to an erroneous TCPL: [19:0]-bits [5…
64575 … 0x560588UL //Access:RW DataWidth:0x1 // Allows GRC access to the GPA and SPA tabl…
64578 … 0x560594UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 31-0.
64579 … 0x560598UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 63-32.
64580 … 0x56059cUL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 95-64.
64581 … 0x5605a0UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 127-96.
64582 … 0x5605a4UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 159-128.
64583 … 0x5605a8UL //Access:R DataWidth:0x20 // Indicates the end of FLI flow for VF 191-160.
64584 … 0x5605acUL //Access:R DataWidth:0x10 // Indicates the end of FLI flow for PF 15-0.
64585 …b0UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 31-0 accordingly.
64586 …b4UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 63-32 accordingly.
64587 …8UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 95-64 accordingly.
64588 …cUL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 127-96 accordingly.
64589 …L //Access:RW DataWidth:0x20 // Clears the FLI done indication for VF bits 159-128 accordingly.
64590 …UL //Access:RW DataWidth:0x20 // Clears the FLI done indication for VFbits 191-160 accordingly.
64591 …c8UL //Access:RW DataWidth:0x10 // Clears the FLI done indication for PF bits 15-0 accordingly.
64592 …upied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value…
64610 …605e4UL //Access:RW DataWidth:0x8 // Resource Type of the invalidated range - register per PF.
64612 …er for the case of invalidation halt (lkpres of invalidated range) [7:0] - Resource type of the…
64614 …x8 // Logging register for reuse miss on transpend entry bits [35:28] - of the problematic r…
64615 …Width:0x8 // Logging register for reuse miss on transpend entry [7:0] - Resource type of the…
64617 … 0x560600UL //Access:RW DataWidth:0x20 // TID of the invalidated range - register per Strom.
64621 … 0x560640UL //Access:RW DataWidth:0x8 // TID of the invalidated range - register per Storm.
64627 …dth:0x1 // Bit per Storm. Indicates that the marked invalidation is done - when read it is also…
64629 …it per PF. If set, the block halts in case it gets PTU requests to an address belongs to a range w…
64631 …x40 // Access the GPA table way 0; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64633 …x40 // Access the GPA table way 1; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64635 …x40 // Access the GPA table way 2; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:…
64637 … 0x562000UL //Access:WB DataWidth:0x34 // Debug access to the SPA array.
64639 …h:0x40 // Access the GPA table way3; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID-…
64641 …- {par - [51]; NS bit - [50]; W bit - [49]; R bit - [48]; U bit - [47]; Priority bit - [46]; PLRU …
64643 … // Access the GPA table way 0; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64645 … // Access the GPA table way 1; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64647 … // Access the GPA table way 2; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64649 … // Access the GPA table way3; format is: 31:0 - TID 39:32 - Resource type 51:40 - Reuse count 8…
64651 …- { Priority bit - [23]; PLRU - [22]; Err bit - [21]; invpend bit [20]; transpend bit - [19]; vali…
64653 … 0x570000UL //Access:WB DataWidth:0x34 // Debug access to the SPA array.
64658 … (0x1<<1) // Enables CDU Inputs -- Must be set for norm…
64660 … (0x1<<2) // Enables CDU Outputs -- Must be set for nor…
64662 … (0x1<<3) // Sets the L1TT Arbiter to Strict Priority; This causes the WB Controll…
64664 … (0x1<<4) // Sets the MATT Arbiter to Strict Priority; This causes the WB Controll…
64666 … (0x1<<5) // Sets the PXP Arbiter to Strict Priority; This causes the WB Controll…
64668 … (0x1<<6) // Masks all PCIE Errors for Load transactions. NOTE -- This is not connecte…
64671 … (0x1<<0) // Signals an unknown address to the rf module.
64688 … (0x1<<0) // Signals an unknown address to the rf module.
64705 … (0x1<<0) // Signals an unknown address to the rf module.
64755 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64757 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64759 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64761 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64764 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64766 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64768 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64770 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64773 …n for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64775 …n for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64777 …n for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64779 …n for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64782 …n for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64784 …n for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64786 …n for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64788 …n for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Ch…
64790 …Controls the Full signal to PXP. This register must never be set higher than 8 -- doing so will re…
64791 …his register must never be set higher than 13 -- doing so will result in data corruption to the PX…
64841 … (0x1<<23) // Uses pxp_init_ldcredit to update PXP Read Cred…
64847 … (0x1<<31) // Uses pxp_init_wbcredit to update PXP Write Cre…
64849 … 0x580704UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
64850 … line) in the selected line (before shift).for selecting a line to output
64859 … 0x58074cUL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
64860 … 0x580750UL //Access:RW DataWidth:0x8 // command to CPU BIST
64861 … 0x580754UL //Access:RW DataWidth:0x8 // address to CPU BIST
64872 … (0xfff<<12) // Block waste within a page. this number equals to PageSize-NCIB*ContextSize.
64904 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64910 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64911 … L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*…
64922 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64923 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64924 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64925 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
64926 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64927 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64928 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64929 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
64930 …0x5a0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64931 …0x5a0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64932 …0x5a0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64933 …0x5a003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
64934 … 0x5a0040UL //Access:W DataWidth:0x1 // Writing to this register clears…
64935 … 0x5a0044UL //Access:RC DataWidth:0x20 // Number of FIC messages sent to the loader
64936 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
64938 … 0x5a0050UL //Access:W DataWidth:0x1 // Writing to this register clears…
64941 … (0x1<<0) // Signals an unknown address to the rf module.
64943 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
64945 … (0x1<<2) // Issuese related to the seg message fields - the sum…
64947 … (0x1<<3) // Mini cache error - meaning that A load …
64949 … (0x1<<4) // Mini cache error - meaning that A load …
64967 … (0x1<<0) // Signals an unknown address to the rf module.
64969 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
64971 … (0x1<<2) // Issuese related to the seg message fields - the sum…
64973 … (0x1<<3) // Mini cache error - meaning that A load …
64975 … (0x1<<4) // Mini cache error - meaning that A load …
64980 … (0x1<<0) // Signals an unknown address to the rf module.
64982 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
64984 … (0x1<<2) // Issuese related to the seg message fields - the sum…
64986 … (0x1<<3) // Mini cache error - meaning that A load …
64988 … (0x1<<4) // Mini cache error - meaning that A load …
65013 … 0x5a0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65018 … (0x1<<1) // indicates not to perform the aggregat…
65020 … (0x1<<2) // defines that only back-to-back aggregation is …
65029 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
65031 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
65033 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
65035 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
65037 … DataWidth:0x10 // Limit the number of �packets� in the Loader according to the number of parent…
65039 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
65041 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
65043 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
65045 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
65048 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
65050 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
65052 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
65054 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
65057 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
65059 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
65061 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
65063 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
65066 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
65068 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
65070 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
65072 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
65108 … 0x5a0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65109 … 0x5a0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65110 … 0x5a082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65111 … 0x5a0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65112 … 0x5a0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65113 … 0x5a0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65114 … 0x5a083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65115 … 0x5a0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65116 … 0x5a0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65117 … 0x5a0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65118 … 0x5a084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65119 … 0x5a0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65120 … 0x5a0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65121 … 0x5a0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65122 … 0x5a085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65123 … 0x5a0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65124 … 0x5a0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65125 … 0x5a0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65126 … 0x5a086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65127 … 0x5a0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65128 … 0x5a0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65129 … 0x5a0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65130 … 0x5a087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65131 … 0x5a0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65132 … 0x5a0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65133 … 0x5a0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65134 … 0x5a088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65135 … 0x5a0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65136 … 0x5a0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65137 … 0x5a0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65138 … 0x5a089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65139 … 0x5a08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65141 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
65143 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
65145 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
65147 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
65150 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
65152 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
65154 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
65156 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
65159 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
65161 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
65163 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
65165 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
65168 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
65170 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
65172 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
65174 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
65213 … (0x1<<0) // indication if to include the flow-ID in the stream-ID …
65215 … (0x1<<1) // indication if to include the flow-ID in the stream-ID …
65217 … (0x1<<2) // indication if to include the flow-ID in the stream-ID …
65219 … (0x1<<3) // indication if to include the flow-ID in the stream-ID …
65221 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
65223 … (0x1f<<9) // offset of the flow-ID, in 32b units, fro…
65225 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
65227 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
65230 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
65232 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
65234 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
65236 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
65248 … (0xff<<0) // The value by which to increment the event-ID in case…
65250 … (0xff<<8) // The value by which to increment the event-ID in case…
65252 … (0xff<<16) // The value by which to increment the event-ID in case…
65254 … (0xff<<24) // The value by which to increment the event-ID in case…
65257 … 0x5a1600UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
65258 … line) in the selected line (before shift).for selecting a line to output
65266 … 0x5a2000UL //Access:WB DataWidth:0x80 // Access to input FIC FIFO
65268 … 0x5b0000UL //Access:WB DataWidth:0x80 // Debug access to The message queue me…
65274 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65275 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65276 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65277 … //Access:R DataWidth:0x20 // Logging of the first loader header cycle - for the case ld_hdr_…
65278 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65279 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65280 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65281 …//Access:R DataWidth:0x20 // Logging of the second loader header cycle - for the case ld_hdr_…
65282 …0x5c0030UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65283 …0x5c0034UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65284 …0x5c0038UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65285 …0x5c003cUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_…
65286 … 0x5c0040UL //Access:W DataWidth:0x1 // Writing to this register clears…
65287 … 0x5c0044UL //Access:RC DataWidth:0x20 // Number of FIC messages sent to the loader
65288 …-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SG…
65290 … 0x5c0050UL //Access:W DataWidth:0x1 // Writing to this register clears…
65293 … (0x1<<0) // Signals an unknown address to the rf module.
65295 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
65297 … (0x1<<2) // Issuese related to the seg message fields - the sum…
65299 … (0x1<<3) // Mini cache error - meaning that A load …
65301 … (0x1<<4) // Mini cache error - meaning that A load …
65319 … (0x1<<0) // Signals an unknown address to the rf module.
65321 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
65323 … (0x1<<2) // Issuese related to the seg message fields - the sum…
65325 … (0x1<<3) // Mini cache error - meaning that A load …
65327 … (0x1<<4) // Mini cache error - meaning that A load …
65332 … (0x1<<0) // Signals an unknown address to the rf module.
65334 …here is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scen…
65336 … (0x1<<2) // Issuese related to the seg message fields - the sum…
65338 … (0x1<<3) // Mini cache error - meaning that A load …
65340 … (0x1<<4) // Mini cache error - meaning that A load …
65365 … 0x5c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access.
65370 … (0x1<<1) // indicates not to perform the aggregat…
65372 … (0x1<<2) // defines that only back-to-back aggregation is …
65381 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
65383 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
65385 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
65387 … associated with each child in number of 128b units for set 0(should be in accordance to DupParams)
65389 … DataWidth:0x10 // Limit the number of �packets� in the Loader according to the number of parent…
65391 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
65393 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
65395 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
65397 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
65400 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
65402 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
65404 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
65406 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
65409 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
65411 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
65413 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
65415 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
65418 … // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set…
65420 … // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set…
65422 … // Offset in 32b units from the beginning of the message to same parameter 2 of configuration-set…
65424 … // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set…
65460 … 0x5c0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65461 … 0x5c0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65462 … 0x5c082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65463 … 0x5c0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65464 … 0x5c0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65465 … 0x5c0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65466 … 0x5c083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65467 … 0x5c0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65468 … 0x5c0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65469 … 0x5c0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65470 … 0x5c084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65471 … 0x5c0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65472 … 0x5c0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65473 … 0x5c0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65474 … 0x5c085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65475 … 0x5c0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65476 … 0x5c0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65477 … 0x5c0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65478 … 0x5c086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65479 … 0x5c0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65480 … 0x5c0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65481 … 0x5c0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65482 … 0x5c087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65483 … 0x5c0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65484 … 0x5c0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65485 … 0x5c0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65486 … 0x5c088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65487 … 0x5c0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65488 … 0x5c0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65489 … 0x5c0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65490 … 0x5c089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65491 … 0x5c08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected …
65493 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
65495 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
65497 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
65499 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
65502 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
65504 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
65506 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
65508 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
65511 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
65513 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
65515 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
65517 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
65520 … // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set …
65522 … // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set …
65524 … // Offset in 32b units from the beginning of the message to dup parameter 2 of configuration-set …
65526 … // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set …
65565 … (0x1<<0) // indication if to include the flow-ID in the stream-ID …
65567 … (0x1<<1) // indication if to include the flow-ID in the stream-ID …
65569 … (0x1<<2) // indication if to include the flow-ID in the stream-ID …
65571 … (0x1<<3) // indication if to include the flow-ID in the stream-ID …
65573 … (0x1f<<4) // offset of the flow-ID, in 32b units, fro…
65575 … (0x1f<<9) // offset of the flow-ID, in 32b units, fro…
65577 … (0x1f<<14) // offset of the flow-ID, in 32b units, fro…
65579 … (0x1f<<19) // offset of the flow-ID, in 32b units, fro…
65582 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
65584 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
65586 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
65588 …s from the beginning of the message in which to put (overwrite) the serial number. Sn Offset shoul…
65600 … (0xff<<0) // The value by which to increment the event-ID in case…
65602 … (0xff<<8) // The value by which to increment the event-ID in case…
65604 … (0xff<<16) // The value by which to increment the event-ID in case…
65606 … (0xff<<24) // The value by which to increment the event-ID in case…
65609 … 0x5c1600UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
65610 … line) in the selected line (before shift).for selecting a line to output
65618 … 0x5c2000UL //Access:WB DataWidth:0x80 // Access to input FIC FIFO
65620 … 0x5d0000UL //Access:WB DataWidth:0x80 // Debug access to The message queue me…
65623 … (0x1<<0) // Signals an unknown address to the RF module.
65629 … (0x1<<0) // Signals an unknown address to the RF module.
65632 … (0x1<<0) // Signals an unknown address to the RF module.
65634 … 0x600140UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
65635 … line) in the selected line (before shift).for selecting a line to output
65693 …-port per-PF register. L2 tag removal configuration for ACPI. Bit mapped as follow: bit 0: 5 - L…
65694 …to enable ACPI and TCP SYN matching even when the packet is forwarded to MCP. Clear this bit to d…
65695 … 0x608080UL //Access:WB DataWidth:0x100 // This is a per-port per-PF register. Byt…
65697 … 0x608100UL //Access:RW DataWidth:0x1 // This is a per-port register. When …
65698 … 0x608104UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65699 … 0x608108UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65700 … 0x60810cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65701 … 0x608110UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65702 … 0x608114UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65703 … 0x608118UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65704 … 0x60811cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65705 … 0x608120UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65706 … 0x608124UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65707 … 0x608128UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65708 … 0x60812cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65709 … 0x608130UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65710 … 0x608134UL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65711 … 0x608138UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65712 … 0x60813cUL //Access:RW DataWidth:0x20 // This is a per-port per-PF register. CRC…
65713 … 0x608140UL //Access:RW DataWidth:0x8 // This is a per-port per-PF register. Len…
65714 … 0x608144UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. Whe…
65715 … 0x608148UL //Access:WB DataWidth:0x30 // This is a per-port per-PF register. MAC…
65717 … 0x608150UL //Access:RW DataWidth:0x1 // This is a per-port per-PF register. A low-to-high …
65718 … 0x608160UL //Access:WB_R DataWidth:0x100 // Read-only data from the Wa…
65720 …- a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details regist…
65721 …- all fields are sticky. Bits 15:0 - PF Vector: The bit-mapped vector indicating which of the gl…
65722 … 0x608188UL //Access:R DataWidth:0xe // Wake packet length - the actual length of…
65723 …- all fields are sticky. Bits 7:0 - ACPI MATCH: Per-function bit-mapped result from ACPI patte…
65725 …election - acpi_default_pf_sel. 2: Select the first of each: 2 ports (quad_port_mode is 0) - use o…
65726 …ess:RW DataWidth:0x2 // This is a per-PF register. Set bit 0 to enable wake on IPv4 TCP SYN.…
65727 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
65728 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
65729 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
65730 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
65731 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
65732 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
65740 … (0x1<<0) // Signals an unknown address to the RF module.
65746 … (0x1<<0) // Signals an unknown address to the RF module.
65749 … (0x1<<0) // Signals an unknown address to the RF module.
65751 … 0x610140UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
65752 … line) in the selected line (before shift).for selecting a line to output
65760 … 0x6101e0UL //Access:RW DataWidth:0x20 // Value of outer tag to be inserted into the…
65761 … 0x6101e4UL //Access:RW DataWidth:0x20 // Value of outer tag to be inserted into the…
65762 … 0x6101e8UL //Access:RW DataWidth:0x20 // Value of outer tag to be inserted into the…
65763 … 0x6101ecUL //Access:RW DataWidth:0x20 // Value of outer tag to be inserted into the…
65764 …ner VLAN tag to be used in tag insertion/override for management packets. This field consists of …
65765 …ner VLAN tag to be used in tag insertion/override for management packets. This field consists of …
65766 … DataWidth:0x3 // The length, in 2-byte granularity, of the info field for the L2 tag. Valid…
65821 … (0xff<<0) // Firmware must set this bit to 1 after finished configuring PCIe Serdes AHB regi…
65823 … (0x1<<8) // Firmware must set this bit to 1 after finished configuring PCIe Serdes AHB regi…
65836 …x628018UL //Access:RW DataWidth:0x10 // Bit masks to be ANDed with cxpl_debug_info_ei[15:0] to…
65865 …_E5 (0x1<<0) // When set to 1, represents FW exi…
65867 …E5 (0x1<<1) // When set to 0, HWInit controls c…
65869 …5 (0x1<<2) // When set to 0, HWInit controls l…
65876 … 0x629fe8UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
65877 … line) in the selected line (before shift).for selecting a line to output
65882 …al into the SerDes. This should be 0 (Reset value) write 1 to this bit to allow the SerDes to begi…
65884 … (0x1<<1) // Active low. Can be asserted on CMU0 in multiple CMU PHYs to save power if TX clo…
65886 …d on CMU0 in multiple CMU PHYs if there are any active lanes. Signal is over-riden by por_n_i so h…
65911 …- rxsig_det_mask_i 16 - rxeii_exit_type_i 15 - rxei_infer_i 14 - bslip_req_i 13 - data_width_i - 0…
65915 …to drive ms_opcs_sdet 0 - ln1_stat_o[2] (RX Locked indicator) 1 - ln1_astat_o[5] (Raw signal dete…
65918 … (0x1<<0) // Indicates CMU PLL has locked to the reference clock …
65920 … (0x1<<1) // Indicates CMU1 PLL has locked to the reference clock …
65923 …- not used 12 - ln1_ok_o 11 - ln1_runlen_err_o 10:4 - not used 3:2 - ln1_rx_locked_o - bit 3 =rxda…
65925 …(0x3f<<14) // 19 - Raw signal detect - Bit Slip Ack 18 - ln1_bitslip_ack_o - Bit Slip Ack 17 - not…
65930 … (0x1<<3) // Assert to provide CMU0 with th…
65934 … (0x1<<6) // Assert to provide CMU1 with th…
65942 … (0x1<<0) // Signals an unknown address to the rf module.
65948 … (0x1<<0) // Signals an unknown address to the rf module.
65951 … (0x1<<0) // Signals an unknown address to the rf module.
65957 … 0x6a0228UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
65958 … line) in the selected line (before shift).for selecting a line to output
65962 …upied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value…
65964 … 0x6a0244UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval * pclk, 2ns to 2ms.
65965 … 0 or 1, trigger on first occurrence. If greater than 1, wait until counter value match to trigger.
65966 …RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
65968 …-0x1ff. Reserved = 0x200-0x3ff. LANE1 registers = 0x400-0x5ff. Reserved = 0x600-0x7f…
65970 …x6b2000UL //Access:RW DataWidth:0x20 // This indirect register is used to access the AVS block…
65975 …s enabled, directly control the configuration registers that are connected to regulators 00: Using…
65977 …ted to regulators 0: Using registers belonging to set0 1: Using registers belonging to set1 SETS_W…
65979 …LOW_CTRL is enabled. Bit [0] : corresponds to FLOW 1 Bit [1] : corresponds to FLOW 2 Any toggle fr…
65984 … (0x3<<1) // It replicates the mode-sel value when voltag…
65986 … (0x7<<3) // It replicates the set-sel value when voltag…
65991 … (0x1<<0) // Signals an unknown address to the rf module.
66001 … (0x1<<0) // Signals an unknown address to the rf module.
66006 … (0x1<<0) // Signals an unknown address to the rf module.
66033 … (0x1<<12) // This bit is set to enable the use of th…
66035 … (0x1<<13) // This bit is set to enable the alternati…
66039 …-> MAC; 1-2 -> PHY1; 3 -> PHY3; 4 -> MAC2; 5-6 -> PHY4; 7 -> PHY6; 8 -> MAC3; …
66040 … // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location wi…
66041 … // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location wi…
66042 … // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location wi…
66043 …idth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G This register allo…
66045 …to Network Port 0, PF1 to NW1 and so on. However, there are cases when the PF and NW conenctions a…
66047 …Port 1 to the corresponding Physical function. 0 -> NW1 connects to PF0 1 -> NW1 connects to PF1…
66049 …Port 2 to the corresponding Physical function. 0 -> NW2 connects to PF0 1 -> NW2 connects to PF1…
66051 …Port 2 to the corresponding Physical function. 0 -> NW3 connects to PF0 1 -> NW3 connects to PF1…
66053 …1cUL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66054 …20UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66055 …24UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66056 …28UL //Access:R DataWidth:0x5 // LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -…
66057 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
66059 … (0x1<<0) // Signals an unknown address to the rf module.
66065 … (0x1<<0) // Signals an unknown address to the rf module.
66068 … (0x1<<0) // Signals an unknown address to the rf module.
66073 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66075 …Power-On-Reset Power Enable. When low, this input powers down the TX and RX analog circuits. It ca…
66081 … (0x1<<5) // Used to select which PLL output to use for this serdes lane 0 - Use p…
66084 …<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the lef…
66086 … (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro ref…
66088 … (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro re…
66090 …l is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (…
66094 …he SerDes in Reset. Once the memory is configured, write 1 to this bit to allow the SerDes to begi…
66096 …d be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begi…
66098 …d be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begi…
66100 …erDes. This should be 0 (Reset value) This holds the ln0 in Reset. write 1 to begin normal Operati…
66102 …erDes. This should be 0 (Reset value) This holds the ln1 in Reset. write 1 to begin normal Operati…
66104 …erDes. This should be 0 (Reset value) This holds the ln2 in Reset. write 1 to begin normal Operati…
66106 …erDes. This should be 0 (Reset value) This holds the ln3 in Reset. write 1 to begin normal Operati…
66108 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66110 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66112 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66114 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66116 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66118 …acro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered d…
66121 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66128 … (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz
66130 … Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66132 … Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125…
66148 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66150 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66152 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66154 …- Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x…
66157 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66164 … (0x1<<0) // 0x0 - No error 0x1 - Phy has inter…
66166 … (0x1<<1) // 0x1 - Indicates CMU0 PLL has locked to the …
66168 … (0x1<<2) // 0x1 - Indicates CMU1 PLL has locked to the …
66170 …<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signals should not …
66172 …<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signals should not …
66174 …<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signals should not …
66176 …<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signals should not …
66178 …<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signals should not …
66180 …<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signals should not …
66196 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66198 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66200 …to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in …
66204 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66207 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66209 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66211 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66213 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66215 …- Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New…
66218 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane…
66220 … (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - d…
66222 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66224 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66226 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. …
66231 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66233 …Power-On-Reset Power Enable. When low, this input powers down the TX and RX analog circuits. It ca…
66239 … (0x1<<5) // Used to select which PLL output to use for this serdes lane 0 - Use p…
66242 …US_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective …
66244 …US_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respective …
66246 …US_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective …
66248 …US_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective …
66250 …US_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective …
66252 …US_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective …
66254 …US_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective …
66256 …US_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective …
66258 …US_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective …
66261 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66268 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66270 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66272 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66274 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66276 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66278 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66280 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66282 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66284 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66286 … (0x1<<18) // This signal detect output corresponds to the sigdet variable …
66288 …to be used in instances where the PMD output is optically or magnetically coupled, and a changing …
66290 …to allow pause control packets to be generated in the MAC and transmitted from the output of the t…
66292 …to allow pause control packets that have arrived at the receiver to be detected in the MAC and sub…
66294 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66296 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66314 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66316 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66318 …to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in …
66322 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66325 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66332 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane…
66334 … (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - d…
66336 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66338 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66340 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. …
66356 …US_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective …
66358 …US_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respective …
66360 …US_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective …
66362 …US_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective …
66364 …US_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective …
66366 …US_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective …
66368 …US_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective …
66370 …US_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective …
66372 …US_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective …
66375 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66377 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66379 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66381 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66383 …- Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New…
66386 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66388 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66390 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66392 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66394 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66396 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66398 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66400 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66402 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66404 … (0x1<<18) // This signal detect output corresponds to the sigdet variable …
66406 …to be used in instances where the PMD output is optically or magnetically coupled, and a changing …
66408 …to allow pause control packets to be generated in the MAC and transmitted from the output of the t…
66410 …to allow pause control packets that have arrived at the receiver to be detected in the MAC and sub…
66412 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66414 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66421 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66423 …Power-On-Reset Power Enable. When low, this input powers down the TX and RX analog circuits. It ca…
66429 … (0x1<<5) // Used to select which PLL output to use for this serdes lane 0 - Use p…
66432 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66434 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66436 …to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in …
66440 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66443 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66450 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane…
66452 … (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - d…
66454 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66456 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66458 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. …
66474 …US_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective …
66476 …US_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respective …
66478 …US_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective …
66480 …US_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective …
66482 …US_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective …
66484 …US_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective …
66486 …US_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective …
66488 …US_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective …
66490 …US_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective …
66493 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66500 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66502 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66504 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66506 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66508 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66510 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66512 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66514 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66516 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66518 … (0x1<<18) // This signal detect output corresponds to the sigdet variable …
66520 …to be used in instances where the PMD output is optically or magnetically coupled, and a changing …
66522 …to allow pause control packets to be generated in the MAC and transmitted from the output of the t…
66524 …to allow pause control packets that have arrived at the receiver to be detected in the MAC and sub…
66526 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66528 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66546 … (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 …
66548 … (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Ph…
66550 …to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in …
66554 … (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2…
66557 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66559 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66561 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66563 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66565 …- Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New…
66568 … (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane…
66570 … (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - d…
66572 … (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run lengt…
66574 …tal LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66576 …igital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. …
66581 … (0x1<<1) // Receiver AC-coupling Mode Selecto…
66583 …Power-On-Reset Power Enable. When low, this input powers down the TX and RX analog circuits. It ca…
66589 … (0x1<<5) // Used to select which PLL output to use for this serdes lane 0 - Use p…
66592 …US_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective …
66594 …US_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respective …
66596 …US_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective …
66598 …US_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective …
66600 …US_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective …
66602 …US_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective …
66604 …US_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective …
66606 …US_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective …
66608 …US_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective …
66611 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88
66618 …<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66620 …<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66622 …<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66624 …<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66626 …<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66628 …<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66630 …<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66632 …<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66634 …<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration…
66636 … (0x1<<18) // This signal detect output corresponds to the sigdet variable …
66638 …to be used in instances where the PMD output is optically or magnetically coupled, and a changing …
66640 …to allow pause control packets to be generated in the MAC and transmitted from the output of the t…
66642 …to allow pause control packets that have arrived at the receiver to be detected in the MAC and sub…
66644 … (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error co…
66646 … (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error…
66664 … (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441
66684 … (0x1<<0) // 0x0 - Unlocked 0x1 - Locked
66686 … (0x1<<1) // 0x0 - Unlocked 0x1 - Locked
66688 … (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after…
66690 … (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after…
66692 …- Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New…
66695 …to �1�. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 s…
66697 …to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment. Thi…
66699 …to internal rotator control logic. Based on the setting of the Internal/External Early/Late Select…
66701 …to internal rotator control logic. Based on the setting of the Internal/External Early/Late Select…
66703 …to retard the phase rotators. Each rising edge of this signal causes one incremental adjustment (r…
66705 …to advance the phase rotators. Each rising edge of this signal causes one incremental adjustment (…
66707 … 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� until the core h…
66710 …to �1�. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 s…
66712 …to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment. Thi…
66714 …to internal rotator control logic. Based on the setting of the Internal/External Early/Late Select…
66716 …to internal rotator control logic. Based on the setting of the Internal/External Early/Late Select…
66718 …to retard the phase rotators. Each rising edge of this signal causes one incremental adjustment (r…
66720 …to advance the phase rotators. Each rising edge of this signal causes one incremental adjustment (…
66722 … 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� until the core h…
66725 …to �1�. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 s…
66727 …to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment. Thi…
66729 …to internal rotator control logic. Based on the setting of the Internal/External Early/Late Select…
66731 …to internal rotator control logic. Based on the setting of the Internal/External Early/Late Select…
66733 …to retard the phase rotators. Each rising edge of this signal causes one incremental adjustment (r…
66735 …to advance the phase rotators. Each rising edge of this signal causes one incremental adjustment (…
66737 … 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� until the core h…
66740 …to �1�. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 s…
66742 …to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment. Thi…
66744 …to internal rotator control logic. Based on the setting of the Internal/External Early/Late Select…
66746 …to internal rotator control logic. Based on the setting of the Internal/External Early/Late Select…
66748 …to retard the phase rotators. Each rising edge of this signal causes one incremental adjustment (r…
66750 …to advance the phase rotators. Each rising edge of this signal causes one incremental adjustment (…
66752 … 1 Enabled (external control of phase rotators). Note: Do not set this bit to �1� until the core h…
66755 …to �1�. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 s…
66757 …to support the 802.3ap standard. When TXxAECMDVAL is asserted, the command on these bits is read a…
66767 … Valid. For use with an external macro to support the 802.3ap standard. This strobe signal is used…
66769 … (0x1<<15) // Out of Band Signaling. Drives transmitter outputs to the DC common mode v…
66771 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66777 …to support the 802.3ap standard. This is a continuously updated status of the applied command with…
66779 …to �1�. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 s…
66781 …to support the 802.3ap standard. When TXxAECMDVAL is asserted, the command on these bits is read a…
66791 … Valid. For use with an external macro to support the 802.3ap standard. This strobe signal is used…
66793 … (0x1<<15) // Out of Band Signaling. Drives transmitter outputs to the DC common mode v…
66795 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66801 …to support the 802.3ap standard. This is a continuously updated status of the applied command with…
66803 …to �1�. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 s…
66805 …to support the 802.3ap standard. When TXxAECMDVAL is asserted, the command on these bits is read a…
66815 … Valid. For use with an external macro to support the 802.3ap standard. This strobe signal is used…
66817 … (0x1<<15) // Out of Band Signaling. Drives transmitter outputs to the DC common mode v…
66819 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66825 …to support the 802.3ap standard. This is a continuously updated status of the applied command with…
66827 …to �1�. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 s…
66829 …to support the 802.3ap standard. When TXxAECMDVAL is asserted, the command on these bits is read a…
66839 … Valid. For use with an external macro to support the 802.3ap standard. This strobe signal is used…
66841 … (0x1<<15) // Out of Band Signaling. Drives transmitter outputs to the DC common mode v…
66843 …-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = �1� and the tr…
66849 …to support the 802.3ap standard. This is a continuously updated status of the applied command with…
66852 …to detect the presence of energy on SerDes receive channels or to detect the receiver loss conditi…
66854 …to detect the presence of energy on SerDes receive channels or to detect the receiver loss conditi…
66856 …to detect the presence of energy on SerDes receive channels or to detect the receiver loss conditi…
66858 …to detect the presence of energy on SerDes receive channels or to detect the receiver loss conditi…
66862 …to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY tha…
66864 …to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY tha…
66866 …to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY tha…
66868 …to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY tha…
66876 … 0x700128UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
66877 … line) in the selected line (before shift).for selecting a line to output
66881 …upied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value…
66883 … 0x700144UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval * pclk, 2ns to 2ms.
66884 … 0 or 1, trigger on first occurrence. If greater than 1, wait until counter value match to trigger.
66885 …RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
66888 … (0x1<<0) // Signals an unknown address to the rf module.
66890 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
66892 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
66894 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
66896 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
66898 … (0x1<<5) // Autonegotiation resolved to 25g_gr
66900 … (0x1<<6) // Autonegotiation resolved to 25g_cr
66902 … (0x1<<7) // Autonegotiation resolved to 25g_kr
66904 … (0x1<<8) // Autonegotiation resolved to 10g_kr
66906 … (0x1<<9) // Autonegotiation resolved to 1g_kx
66930 … (0x1<<0) // Signals an unknown address to the rf module.
66932 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
66934 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
66936 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
66938 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
66940 … (0x1<<5) // Autonegotiation resolved to 25g_gr
66942 … (0x1<<6) // Autonegotiation resolved to 25g_cr
66944 … (0x1<<7) // Autonegotiation resolved to 25g_kr
66946 … (0x1<<8) // Autonegotiation resolved to 10g_kr
66948 … (0x1<<9) // Autonegotiation resolved to 1g_kx
66951 … (0x1<<0) // Signals an unknown address to the rf module.
66953 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
66955 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
66957 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
66959 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
66961 … (0x1<<5) // Autonegotiation resolved to 25g_gr
66963 … (0x1<<6) // Autonegotiation resolved to 25g_cr
66965 … (0x1<<7) // Autonegotiation resolved to 25g_kr
66967 … (0x1<<8) // Autonegotiation resolved to 10g_kr
66969 … (0x1<<9) // Autonegotiation resolved to 1g_kx
66972 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
66974 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
66976 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
66978 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
66980 … (0x1<<5) // Autonegotiation resolved to 25g_gr
66982 … (0x1<<6) // Autonegotiation resolved to 25g_cr
66984 … (0x1<<7) // Autonegotiation resolved to 25g_kr
66986 … (0x1<<8) // Autonegotiation resolved to 10g_kr
66988 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67010 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
67012 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
67014 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
67016 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
67018 … (0x1<<5) // Autonegotiation resolved to 25g_gr
67020 … (0x1<<6) // Autonegotiation resolved to 25g_cr
67022 … (0x1<<7) // Autonegotiation resolved to 25g_kr
67024 … (0x1<<8) // Autonegotiation resolved to 10g_kr
67026 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67029 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
67031 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
67033 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
67035 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
67037 … (0x1<<5) // Autonegotiation resolved to 25g_gr
67039 … (0x1<<6) // Autonegotiation resolved to 25g_cr
67041 … (0x1<<7) // Autonegotiation resolved to 25g_kr
67043 … (0x1<<8) // Autonegotiation resolved to 10g_kr
67045 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67048 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
67050 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
67052 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
67054 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
67056 … (0x1<<5) // Autonegotiation resolved to 25g_gr
67058 … (0x1<<6) // Autonegotiation resolved to 25g_cr
67060 … (0x1<<7) // Autonegotiation resolved to 25g_kr
67062 … (0x1<<8) // Autonegotiation resolved to 10g_kr
67064 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67086 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
67088 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
67090 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
67092 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
67094 … (0x1<<5) // Autonegotiation resolved to 25g_gr
67096 … (0x1<<6) // Autonegotiation resolved to 25g_cr
67098 … (0x1<<7) // Autonegotiation resolved to 25g_kr
67100 … (0x1<<8) // Autonegotiation resolved to 10g_kr
67102 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67105 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
67107 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
67109 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
67111 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
67113 … (0x1<<5) // Autonegotiation resolved to 25g_gr
67115 … (0x1<<6) // Autonegotiation resolved to 25g_cr
67117 … (0x1<<7) // Autonegotiation resolved to 25g_kr
67119 … (0x1<<8) // Autonegotiation resolved to 10g_kr
67121 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67124 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
67126 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
67128 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
67130 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
67132 … (0x1<<5) // Autonegotiation resolved to 25g_gr
67134 … (0x1<<6) // Autonegotiation resolved to 25g_cr
67136 … (0x1<<7) // Autonegotiation resolved to 25g_kr
67138 … (0x1<<8) // Autonegotiation resolved to 10g_kr
67140 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67162 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
67164 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
67166 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
67168 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
67170 … (0x1<<5) // Autonegotiation resolved to 25g_gr
67172 … (0x1<<6) // Autonegotiation resolved to 25g_cr
67174 … (0x1<<7) // Autonegotiation resolved to 25g_kr
67176 … (0x1<<8) // Autonegotiation resolved to 10g_kr
67178 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67181 … (0x1<<1) // Autonegotiation resolved to 50g_cr2
67183 … (0x1<<2) // Autonegotiation resolved to 50g_kr2
67185 … (0x1<<3) // Autonegotiation resolved to 40g_cr4
67187 … (0x1<<4) // Autonegotiation resolved to 40g_kr4
67189 … (0x1<<5) // Autonegotiation resolved to 25g_gr
67191 … (0x1<<6) // Autonegotiation resolved to 25g_cr
67193 … (0x1<<7) // Autonegotiation resolved to 25g_kr
67195 … (0x1<<8) // Autonegotiation resolved to 10g_kr
67197 … (0x1<<9) // Autonegotiation resolved to 1g_kx
67211 …10 // PHY instance0 = 0x000-0x1fff. PHY instance1 = 0x2000-0x3fff. PHY instance2 = 0x4000-0x5fff…
67213 …-0x7ff. CMU0 registers = 0x0800-0x0bff. CMU1 registers = 0x0c00-0x0fff. Reserved = …
67215 … 0x740000UL //Access:RW DataWidth:0x20 // Used to load operating table…
67217 … 0x760000UL //Access:RW DataWidth:0x20 // Used to load operating firmw…
67220 … (0x1<<0) // Signals an unknown address to the rf module.
67238 … (0x1<<16) // Lane 0 Resolved to 10Mb rate
67240 … (0x1<<17) // Lane 0 Resolved to 100Mb rate
67242 … (0x1<<18) // Lane 1 Resolved to 10Mb rate
67244 … (0x1<<19) // Lane 1 Resolved to 100Mb rate
67246 … (0x1<<20) // Lane 2 Resolved to 10Mb rate
67248 … (0x1<<21) // Lane 2 Resolved to 100Mb rate
67250 … (0x1<<22) // Lane 3 Resolved to 10Mb rate
67252 … (0x1<<23) // Lane 3 Resolved to 100Mb rate
67290 … (0x1<<0) // Signals an unknown address to the rf module.
67308 … (0x1<<16) // Lane 0 Resolved to 10Mb rate
67310 … (0x1<<17) // Lane 0 Resolved to 100Mb rate
67312 … (0x1<<18) // Lane 1 Resolved to 10Mb rate
67314 … (0x1<<19) // Lane 1 Resolved to 100Mb rate
67316 … (0x1<<20) // Lane 2 Resolved to 10Mb rate
67318 … (0x1<<21) // Lane 2 Resolved to 100Mb rate
67320 … (0x1<<22) // Lane 3 Resolved to 10Mb rate
67322 … (0x1<<23) // Lane 3 Resolved to 100Mb rate
67325 … (0x1<<0) // Signals an unknown address to the rf module.
67343 … (0x1<<16) // Lane 0 Resolved to 10Mb rate
67345 … (0x1<<17) // Lane 0 Resolved to 100Mb rate
67347 … (0x1<<18) // Lane 1 Resolved to 10Mb rate
67349 … (0x1<<19) // Lane 1 Resolved to 100Mb rate
67351 … (0x1<<20) // Lane 2 Resolved to 10Mb rate
67353 … (0x1<<21) // Lane 2 Resolved to 100Mb rate
67355 … (0x1<<22) // Lane 3 Resolved to 10Mb rate
67357 … (0x1<<23) // Lane 3 Resolved to 100Mb rate
67359 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67360 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67361 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67362 …0x1e // A so-called Peer Delay value that can be added to the correction field for all 1-step up…
67364 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67380 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67396 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67412 …- LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - …
67429 … (0x1<<0) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When set to…
67431 … (0x1<<1) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When set to…
67433 … (0x1<<2) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When set to…
67435 … (0x1<<3) // SGMII PCS Enable. When set to 1, the SGMII PCS is enabled. When set to…
67438 … (0x1<<0) // Set to '1' to indicate success…
67440 … (0x1<<1) // Auto-Negotiation status. Set to '1' when the Auto…
67442 … (0x1<<2) // Set to '1' to indicate success…
67444 … (0x1<<3) // Auto-Negotiation status. Set to '1' when the Auto…
67446 … (0x1<<4) // Set to '1' to indicate success…
67448 … (0x1<<5) // Auto-Negotiation status. Set to '1' when the Auto…
67450 … (0x1<<6) // Set to '1' to indicate success…
67452 … (0x1<<7) // Auto-Negotiation status. Set to '1' when the Auto…
67455 … (0xf<<0) // Set to '1' for a given lane to enable F…
67457 … (0xf<<4) // Set to '1' for a given lane to enable F…
67459 … (0xf<<8) // Set to '1' for a given lane to enable FEC74 forward indication of un…
67462 … (0x3<<0) // Defines for each physical serdes lane separately, to which PCS lane it sh…
67464 … (0x3<<2) // Defines for each physical serdes lane separately, to which PCS lane it sh…
67466 … (0x3<<4) // Defines for each physical serdes lane separately, to which PCS lane it sh…
67468 … (0x3<<6) // Defines for each physical serdes lane separately, to which PCS lane it sh…
67470 …-wake mode for the LPI transmit and receive functions. When set to 1, the link is to use fast wake…
67480 …alue that is set true (1) when the receive is in a low power state and set to false (0) when it is…
67491 …alue that is set true (1) when the receive is in a low power state and set to false (0) when it is…
67502 …alue that is set true (1) when the receive is in a low power state and set to false (0) when it is…
67513 …alue that is set true (1) when the receive is in a low power state and set to false (0) when it is…
67516 … (0x1<<0) // PCS Indication to the application that…
67522 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67525 … (0x1<<0) // PCS Indication to the application that…
67531 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67534 … (0x1<<0) // PCS Indication to the application that…
67540 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67543 … (0x1<<0) // PCS Indication to the application that…
67549 … remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
67554 …on state machines could successfully lock onto 66-bit block boundaries on all virtual lanes releva…
67556 …tance is configured (See Register VL_INTVL) the measurement period shrinks to 12.5�s, independent …
67558 …-lock or align-done status, depending on current mode, and a cleared hi-ber status. The signal sta…
67568 …to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmi…
67570 …to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmi…
67572 …to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and …
67574 …to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmi…
67576 …to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmi…
67578 …to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and …
67580 …to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmi…
67582 …to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmi…
67584 …to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and …
67586 …to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmi…
67588 …to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmi…
67590 …to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and …
67617 … 0x8000ecUL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
67618 … line) in the selected line (before shift).for selecting a line to output
67806 …RW DataWidth:0x1 // Init bit. When set the initial credits are copied to the credit registers…
67807 … 0xd80004UL //Access:W DataWidth:0x1 // Any write to this register trigge…
67809 … 0xd8000cUL //Access:RW DataWidth:0x1 // When set to 1 the cam hit parity…
67810 … 0xd80010UL //Access:RW DataWidth:0x1 // When set to 1 the cam miss parit…
67856 … 0xd80060UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
67857 … line) in the selected line (before shift).for selecting a line to output
67865 … 0xd800a8UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
67866 … line) in the selected line (before shift).for selecting a line to output
67868 … 0xd800b4UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
67869 … line) in the selected line (before shift).for selecting a line to output
67881 … 0xd80100UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
67882 … 0xd80104UL //Access:RW DataWidth:0x8 // command to CPU BIST
67883 … 0xd80108UL //Access:RW DataWidth:0x8 // address to CPU BIST
67888 … (0x1<<0) // Signals an unknown address to the rf module.
67894 … (0x1<<0) // Signals an unknown address to the rf module.
67897 … (0x1<<0) // Signals an unknown address to the rf module.
68144 …0220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
68154 …0224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
68155 …0230UL //Access:W DataWidth:0x14 // Register to generate up to two ECC errors on the next wri…
68156 …0234UL //Access:W DataWidth:0x14 // Register to generate up to two ECC errors on the next wri…
68157 …0238UL //Access:W DataWidth:0xe // Register to generate up to two ECC errors on the next wri…
68448 …0400UL //Access:RW DataWidth:0x3 // PXP read request interface initial credit - transoriented.
68449 … 0xd80404UL //Access:RW DataWidth:0x6 // TDIF pass-through command inter…
68450 … 0xd80408UL //Access:RW DataWidth:0x6 // TDIF non_pass-through command inter…
68452 …10UL //Access:RW DataWidth:0x2 // PXP internal write interface initial credit - transoriented.
68453 … 0xd80414UL //Access:RW DataWidth:0x3 // TM interface initial credit - transoriented.
68482 …-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
68483 …-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port. This applie…
68484 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. This applies to …
68485 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. This applies to …
68486 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. This applies to …
68487 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. This applies to …
68488 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. This applies to …
68489 …-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. This applies to …
68490 …-port: Bit-map indicating which headers must appear in the packet on this port. This applies to t…
68491 …r-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port. …
68492 …// Per-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port. Appli…
68493 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port. Applica…
68494 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port. Applica…
68495 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port. Applica…
68496 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port. Applica…
68497 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port. Applica…
68498 … // Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port. Applica…
68499 … // Per-port: Bit-map indicating which headers must appear in the packet on this port. Applicab…
68505 … 0xd8050cUL //Access:RW DataWidth:0x8 // Value used to designate TCP in the…
68506 … 0xd80510UL //Access:RW DataWidth:0x8 // Value used to designate UDP in the…
68507 … 0xd80514UL //Access:RW DataWidth:0x8 // Value used to designate GRE in the…
68508 … 0xd80518UL //Access:RW DataWidth:0x10 // Dest port value used to designate a VXLAN he…
68509 … 0xd8051cUL //Access:RW DataWidth:0x10 // Dest port value used to designate a NGE head…
68511 … 0xd80524UL //Access:RW DataWidth:0x1 // Per-port: Flag to compare the value of nge versio…
68515 …ables inclusion of the VPORT ID in lookup tuple. If disabled, zero assigned to this VPORT ID field.
68517 …es inclusion of the First VLAN ID in lookup tuple. If disabled, zero assigned to this VLAN ID field
68519 …nclusion of the First Destination MAC in lookup tuple. If disabled, zero assigned to this MAC field
68521 …es inclusion of the inner VLAN ID in lookup tuple. If disabled, zero assigned to this VLAN ID field
68531 … (0xf<<10) // Byte offset for vport id to be obtained from Y2P…
68533 … (0x1f<<14) // REGQ offset for vport id to be obtained from Y2P…
68544 …used only if sal_flex_upper_bytes is not 0, and number of bytes selected = 8 - sal_flex_upper_bytes
68550 …/ Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in each bit masks the correspondin…
68551 …/ Masks 64 bit Flexible field used for Same-as-last lookup. A 0 in each bit masks the correspondin…
68556 … 0xd80548UL //Access:RW DataWidth:0x14 // mpls_ipv4_label to be compared Vs the l…
68557 … 0xd8054cUL //Access:RW DataWidth:0x14 // mpls_ipv6_label to be compared Vs the l…
68563 …d80554UL //Access:RW DataWidth:0x1 // mpls_ipv6_label/mpls_ipv4_label to be compared Vs the l…
68601 … (0x1<<0) // compare the GRE version field to the gre_version regi…
68603 … (0x7<<1) // compare the GRE version field to gre_version register…
68605 …IT_E5 (0x1<<4) // Chicken bit to use single fc engine
68641 …d TAG order. Reset value is in the order from left to right: tag0; tag1; tag2; tag3; tag4; tag5; l…
68642 …//Access:RW DataWidth:0x4 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. T…
68645 …. A zero in this register will cause the corresponding bit to not be included in t…
68646 …. A zero in this register will cause the corresponding bit to not be included in t…
68651 …in Event ID modification logic. Setting to 1 selects or unmasks the condition. Bit 0 of this mask …
68653 …obal Destination Mac Address Match in Event ID modification logic. Setting to 1 selects or unmasks…
68655 …in Event ID modification logic. Setting to 1 selects or unmasks the condition. Bit 0 of this mask …
68658 …in Event ID modification logic. Setting to 1 selects or unmasks the condition. Bit 0 of this mask …
68660 …in Event ID modification logic. Setting to 1 selects or unmasks the condition. Bit 0 of this mask …
68663 …DataWidth:0xb // Number of shared BTB 256 byte blocks which can be used by all TC-s in the port.
68665 …/Access:RW DataWidth:0x6 // Jumbo packet threshold in 256 byte blocks to determine if a TC ca…
68666 …to MS nibble holds the TC number of the corresponding priority. bits 3:0 hold the TC number from 0…
68667 …-priority w/ anti-starvation arbiter is a RR arbiter. A value of all ones means no RR slots; i.e. …
68668 …W DataWidth:0x8 // L2 EDPM threshold in 256 byte blocks. Only if all TC-s have allocated bloc…
68669 …s:RW DataWidth:0xb // CPMU threshold in 256 byte blocks. Only if all TC-s in port N have allo…
68670 … DataWidth:0xb // RDMA EDPM threshold in 256 byte blocks. Only if all TC-s have allocated bloc…
68671 … 0xd80600UL //Access:RW DataWidth:0x10 // 1st bit mask used to control the rollover…
68672 … 0xd80604UL //Access:RW DataWidth:0x10 // 2nd bit mask used to control the rollover…
68673 … 0xd80608UL //Access:RW DataWidth:0x10 // 3rd bit mask used to control the rollover…
68674 … 0xd8060cUL //Access:RW DataWidth:0x10 // 4th bit mask used to control the rollover…
68685 … 0xd80640UL //Access:RW DataWidth:0x5 // PCI VOQ ID used in read request to PCI.
68686 …W DataWidth:0x1 // if set, packets with a PCIE/DIF error will be sent to BTB with a drop indi…
68688 … 0xd8065cUL //Access:RC DataWidth:0x20 // Number of packets sent to BTB
68689 … 0xd80660UL //Access:ST DataWidth:0x30 // Number of bytes sent to BTB
68692 … 0xd8066cUL //Access:RC DataWidth:0x8 // Number of packets sent to BTB with error indic…
68693 … 0xd80670UL //Access:RC DataWidth:0x8 // Number of packets sent to BTB with drop indica…
69356 … (0x1<<0) // Signals an unknown address to the rf module.
69394 … (0x1<<0) // Signals an unknown address to the rf module.
69413 … (0x1<<0) // Signals an unknown address to the rf module.
69435 … (0x1<<0) // Indicates if to switch the CRC resul…
69437 … (0x1<<1) // Indicates if to ignore the input err…
69443 …machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
69477 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the instruction…
69478 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the lower 32 bi…
69479 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the upper 32 bi…
69480 …debug register. This register provides the number of data bytes remaining to be read from DB at t…
69486 … 0xda0728UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
69487 … line) in the selected line (before shift).for selecting a line to output
69491 … 0xda2000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69496 … (0x1<<0) // Signals an unknown address to the rf module.
69534 … (0x1<<0) // Signals an unknown address to the rf module.
69553 … (0x1<<0) // Signals an unknown address to the rf module.
69575 … (0x1<<0) // Indicates if to switch the CRC resul…
69577 … (0x1<<1) // Indicates if to ignore the input err…
69583 …machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
69617 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the instruction…
69618 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the lower 32 bi…
69619 …ss:R DataWidth:0x20 // EOP mismatch debug register. Use this address to read the upper 32 bi…
69620 …debug register. This register provides the number of data bytes remaining to be read from DB at t…
69626 … 0xda4728UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
69627 … line) in the selected line (before shift).for selecting a line to output
69631 … 0xda6000UL //Access:WB_R DataWidth:0x108 // Provides read-only access of the da…
69635 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
69636 …0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en…
69637 …BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from wri…
69639 … (0x1<<0) // Signals an unknown address to the rf module.
69705 … (0x1<<0) // Signals an unknown address to the rf module.
69738 … (0x1<<0) // Signals an unknown address to the rf module.
69799 … (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
69801 … (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descr…
69865 … (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
69867 … (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descr…
69898 … (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
69900 … (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descr…
70832 …0410UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
70850 …0414UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
70851 …0418UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
70852 …041cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
70904 …0420UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
70956 …0424UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71008 …0428UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71012 …042cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71013 …0430UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71014 …0434UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71015 …0438UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71016 …043cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71017 …0440UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71018 …0444UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71019 …0448UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71020 …044cUL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
71021 …to Big RAM for RBC operations. Value of this register will be incremented by one it was done write…
71022 …der in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packet avai…
71023 … 0xdb0810UL //Access:RW DataWidth:0xd // Head pointer to each one of 4 free l…
71030 …e requests till reset in a case of length error other way it will continue to work as usual.::s/ST…
71031 …to BIG RAM from its input FIFO. Miniml value is total number of TCs for all ports + 2 + number of …
71032 …to client 0 and so on. If bit is set then packet will be read without dead cycles.B0-NIG main port…
71034 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71036 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71038 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71040 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71042 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71044 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71046 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71048 … priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is high…
71050 …to client 0 and so on. If bit is set then packet will be written without intra packet dead cycles …
71051 …to client 0 and so on. If bit is set then highest priority mechanism is enabled for the correspond…
71052 …taWidth:0x2 // This is priority for SOP read client to Big RAM arbiter. Possible values are 1-3…
71053 …s is priority for packet request of write client group to Big RAM arbiter. Possible values are 1-3…
71054 …h multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is high…
71055 …of entries inside input FIFO of each write client upper which full outputs to this write client in…
71061 …ries inside descriptors FIFO of each write client upper which full outputs to this write client in…
71062 …of entries inside queue FIFO of each write client upper which full outputs to this write client in…
71064 …upied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value…
71067 … 0xdb08c8UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
71068 … line) in the selected line (before shift).for selecting a line to output
71077 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropr…
71081 …- NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then…
71084 …-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropr…
71086 …is set then appropriate interface is enabled. When bit is reset then valid to that interface will …
71097 …fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main …
71101 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71102 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71103 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71104 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71105 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71106 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71107 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71108 …ty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read clien…
71109 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71110 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71111 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71112 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71113 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71114 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71115 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71116 …ll status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read clien…
71117 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71118 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71119 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71120 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71121 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71122 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71123 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71124 …s status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read clien…
71125 …4 // Debug register. Empty status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71126 …x4 // Debug register. Full status of read SOP clients: {B2-req_fifo; B1-dscr_fifo; B0-queue_f…
71127 … register. FIFO counters status of read SOP clients: {B11:8-req_fifo; B7:4-dscr_fifo; B3:0-queue…
71132 …ss:R DataWidth:0x1 // Debug register. This is almost full output IF to PBF::/ALM_FULL_EN/d …
71136 …to wait for, in power of 2, before sending new packet indication to read client. This should ensur…
71137 …ere is requister for each queue of duplicated client that contains pointer to first block of last …
71139 …to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according …
71141 …ter for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - qu…
71144 …ed to this register for each erad packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG…
71148 …ed to this register for each read packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG…
71155 …Access:RW DataWidth:0xc // Link list dual port memory that contains per-block descriptor::s/B…
71156 …Access:RW DataWidth:0xd // Link list dual port memory that contains per-block descriptor::s/B…
71176 … WATCHDOG_ATTN bit. When this bit is written as '1', the value will return to '0'. !!! Writing '1'…
71183 …e driver it indicates to MCP that it should start incrementing the MCP_HEARTBEAT register. The MCP…
71186 … (0x7ff<<0) // This value is written by the MCP and indicates (in ms) to the driver MCP_HEART…
71190 … (0x1<<31) // When set this bit validates bits 10-0 of this register.
71195 … (0x1<<30) // When set this bit causes MCP heartbeat counter to increment. Typically…
71199 … 0xe00094UL //Access:RW DataWidth:0x20 // Doorbell to reset the watchog ti…
71211 …chdog timer will result in MCP losing ability to perform GRC master write operations. Default is f…
71213 …s driver's attention. Low to high transition on this bit should generate MCP attention toward the …
71215 … (0x1<<30) // When set this bit enables the watchdog timer to reset the MCP instea…
71219 …chog timer #1. These bits specify the watchdog timeout period with respect to the MCP (1/2 speed) …
71220 …chog timer #2. These bits specify the watchdog timeout period with respect to the MCP (1/2 speed) …
71224 …to this bit in order to obtain the lock over the shared resources within the chip. The actual "loc…
71229 …er the PCIE function that is associated with. '0' corresponds to even PCIE functions '1' to odd PC…
71232 …-bit words) of the mailbox within the MCP scratchpad. There are two reset values. Register that co…
71236 … (0xfff<<20) // Mailbox size in 32-bit words. Default ma…
71239 …-bit words) of the mailbox within the MCP scratchpad. There are two reset values. Register that co…
71243 … (0xfff<<20) // Mailbox size in 32-bit words. Default ma…
71248 … (0x1<<31) // Set by the driver to alert the MCP. Changing this register updates the corr…
71251 … (0xff<<0) // Register supports up to an 8 bit VFID. For s…
71266 …taWidth:0x20 // Port mode for GRC Master transactions 0: 1-port mode, 1: 2-port mode, 2: 4-port …
71268 …:RW DataWidth:0x20 // EPIO mask for signal transitioning from high to low. 1 -> MASK the ev…
71269 …:RW DataWidth:0x20 // EPIO mask for signal transitioning from low to high. 1 -> MASK the ev…
71270 …00dcUL //Access:RW DataWidth:0x20 // EPIO event status for high to low transition prior to mask
71271 …00e0UL //Access:RW DataWidth:0x20 // EPIO event status for low to high transition prior to mask
71274 … (0x1<<0) // When this bit is written to a 1, the processor will reset as if from pow…
71276 … (0x1<<1) // When this bit is set, the processor is allowed to execute one cycle re…
71278 … (0x1<<2) // This bit enables the processor to halt and to latch the valu…
71280 … (0x1<<3) // This bit enables the processor to halt and to latch the valu…
71286 … (0x1<<7) // When this bit is set to 1, the interrupt is …
71290 …n or reset. If the processor does not have a ROM, then this bit will reset to set so that no code …
71292 …U will halt when any condition that causes bit 5 in the CPU state register to be set occurs. This …
71294 …U will halt when any condition that causes bit 6 in the CPU state register to be set occurs. This …
71303 …reakpoint as enabled in the mode register. This bit is cleared by writing a 1 to this bit position.
71307 …alted due fetching an invalid instruction. This bit is cleared by writing a 1 to this bit position.
71309 … processor is halted due to accessing data within page 0 (the first 256 bytes) of memory. This bit…
71311 …essor is halted due to executing an instruction within page 0 (the first 256 bytes) of memory. Thi…
71313 … is set while the processor is halted due to bad data reference address. This bit is cleared by wr…
71315 …et while the processor is halted due to bad value in the Program Counter (PC). This bit is cleared…
71317 …e processor is halted due to bad memory alignment problem on a load or store instruction. This bit…
71319 … (0x1<<8) // This bit is set while the processor is halted due to the generation of a …
71323 … (0x1<<10) // This bit is set while the processor is halted due to the setting of bit 1…
71325 … (0x1<<11) // This bit is each time an attempt is made to access the underflow…
71331 … (0x1<<14) // This bit is set while the processor is stalled due to data access.
71333 … (0x1<<15) // This bit is set while the processor is stalled due to instruction fetch.
71337 …to stall while data is fetched from memory. This is intended as a debugging tool. No state is save…
71339 …Width:0x20 // This register provides one bit for each state register bit to enable it into the e…
71340 … (0x1<<0) // This bit enables breakpoints to generate Attention o…
71344 … (0x1<<2) // This bit enables invalid instruction decodes to generate Attention o…
71346 … (0x1<<3) // This bit enables page 0 data access to generate Attention o…
71348 … (0x1<<4) // This bit enables page 0 instructions to generate Attention o…
71350 … (0x1<<5) // This bit enables invalid data addresses to generate Attention o…
71352 … (0x1<<6) // This bit enables invalid PC values to generate Attention o…
71354 … (0x1<<7) // This bit enables alignment errors to generate Attention o…
71360 … (0x1<<10) // This bit enables soft halts to generate Attention o…
71366 …to read at any time. The value can be modified when the processor is halted. Writes will also clea…
71367 …his register is only intended for debugging use. This register may be used to replace a halt instr…
71368 …to the address of the current data access of the processor. It is only valid when the processor is…
71369 …to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intende…
71370 …rogram counter value that will be loaded when an interrupt is performed due to the interrupt input.
71377 … (0x3fffffff<<2) // This field sets the 32-bit word on which the…
71380 … (0x7ff<<0) // 11 bit set-1 debug visibility ve…
71384 … (0xf<<12) // 4 bit select for the peek value of the set-1 debug visibility ve…
71386 … (0x7ff<<16) // 11 bit set-2 debug visibility ve…
71390 … (0xf<<28) // 4 bit select for the peek value of the set-2 debug visibility ve…
71399 …/ While the processor is halted, the general purpose processor registers (r0-r31) can be read and …
71402 …<0) // This value is used to specify the bit at the auto-polled address that indicates "link up". …
71404 … (0xffff<<16) // This value is used to define the register address in MDIO auto-…
71407 …-B0, on the first read of this register when the START_BUSY bit returns to '0', this value, in the…
71409 … (0x1f<<16) // This value is used to define the register …
71411 … (0x1f<<21) // This value is used to define the PHY addre…
71415 …, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen whe…
71417 …to a '1', the currently programmed MDIO transaction will activate. When the operation is complete,…
71420 …by the MDIO interface if auto-polling is enabled. The value of this bit is reflected by in the mai…
71427 … (0x1<<1) // If this bit is set, the 32-bit pre-amble will not be generated during au…
71431 …-polling. When auto-polling is on, the START_BUSY bit in the mdio_comm register must not be set. T…
71439 …etting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the B…
71441 …/ Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting thi…
71449 …rols the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_C…
71453 …to 1 this bit indicates that the current MDIO transaction will be executed as a Clause 45 transact…
71456 … is detected during a auto poll sequence. The bit is cleared by writing a '1' to this bit position.
71458 …e05900UL //Access:RW DataWidth:0x20 // This register controls accesses to 3 WarpCore SERDES mi…
71463 …ch of the uC interfaces will be accessed when the access_mode field is set to specific_read or spe…
71476 …arpCore SERDES microcontroller program memory interfaces. This register auto-increments after each…
71481 … (0x1<<0) // Write this bit as a '1' to set ext_uc_enable fo…
71483 … (0x1<<1) // Write this bit as a '1' to set ext_uc_enable fo…
71485 … (0x1<<2) // Write this bit as a '1' to set ext_uc_enable fo…
71489 … (0x1<<8) // Write this bit as a '1' to clear ext_uc_enable …
71491 … (0x1<<9) // Write this bit as a '1' to clear ext_uc_enable …
71493 … (0x1<<10) // Write this bit as a '1' to clear ext_uc_enable …
71503 …e05914UL //Access:RW DataWidth:0x20 // This register controls accesses to 2 PCIE SERDES microc…
71508 …ch of the uC interfaces will be accessed when the access_mode field is set to specific_read or spe…
71521 … 2 PCIE SERDES microcontroller program memory interfaces. This register auto-increments after each…
71526 … (0x1<<0) // Write this bit as a '1' to set ext_uc_enable fo…
71528 … (0x1<<1) // Write this bit as a '1' to set ext_uc_enable fo…
71532 … (0x1<<8) // Write this bit as a '1' to clear ext_uc_enable …
71534 … (0x1<<9) // Write this bit as a '1' to clear ext_uc_enable …
71542 …address offset for the AVS RBUS program memory interface. This register auto-increments after each…
71547 … (0x1f<<0) // Number of bytes to be transfered in Read or Write operation. Valid len…
71566 … (0xff<<0) // This field sets the address which is sent to the Slave Device as …
71570 …ice ID of the Slave Device. This is a 7-bit field as defined by the I2C spec, but can be written h…
71593 … 0xe05a20UL //Access:RW DataWidth:0x20 // This register is used to store bytes for Read…
71594 … 0xe05a24UL //Access:RW DataWidth:0x20 // This register is used to store bytes for Read…
71595 … 0xe05a28UL //Access:RW DataWidth:0x20 // This register is used to store bytes for Read…
71596 … 0xe05a2cUL //Access:RW DataWidth:0x20 // This register is used to store bytes for Read…
71598 …ing a packet. If this bit is set, no new data should be written to the FIFO memory or to the Heade…
71600 … (0x1<<1) // This bit indicates that in In-Use Error has occured…
71602 …t the packet FIFO was overwritten with too much data. The FIFO is designed to hold a max sized pac…
71606 … (0x1<<4) // This bit is set when a packet is transmitted while the VDM Length is set to 0x0.
71620 … (0x7f<<0) // This is the length of the VDM packet, in 32-bit DWords. 0x0 is an…
71642 … (0x1<<0) // This bit selects whether the VDM will be sent to Engine 0 or Engine 1.
71644 …612cUL //Access:W DataWidth:0x20 // Writing to this register will store the data in the Tx FI…
71657 … (0x1<<0) // Setting this bit will cause the P2M block to assert backpressure to the PXP …
71659 … (0x1<<1) // When set, this bit forces P2M to constantly drain the…
71661 … will cause any packet that doesn't match one of the two Vendor ID Filters to be discarded. If thi…
71666 … (0xffff<<0) // This is the Vendor ID to use for this VID Fil…
71668 … (0x1<<16) // When set, this bit causes packets which match this VID Filter to be discarded.
71673 … (0xffff<<0) // This is the Vendor ID to use for this VID Fil…
71675 … (0x1<<16) // When set, this bit causes packets which match this VID Filter to be discarded.
71680 … (0xff<<0) // This is the Tag Value to use in the Filter.
71682 … (0xff<<8) // This is the mask value to apply to the Tag for Fil…
71693 …th:0x20 // This statistic counts the number of VDM packets discarded due to VendorID Filtering. …
71694 …th:0x20 // This statistic counts the number of VDM packets discarded due to Tag Filtering. Readi…
71695 …th:0x20 // This statistic counts the number of VDM packets discarded due to Length Filtering. Re…
71696 …idth:0x20 // This statistic counts the number of VDM packets dropped due to the FIFO being full.…
71697 …0 // This statistic counts the number of VDM packets received and passed to the MCP. This does n…
71698 …-bits of the current Header. The first access will give bits [31:0], then [63:32], then [95:64]. T…
71707 … 0xe06240UL //Access:R DataWidth:0x20 // 32-bit Packet Data.
71709 … (0x7f<<0) // 7-bit Length from VDM H…
71712 … (0xffff<<0) // 16-bit PCI Requester ID …
71715 … (0xffff<<0) // 16-bit Vendor ID from VD…
71718 … (0xffff<<0) // 16-bit FID from VDM Head…
71720 … 0xe06254UL //Access:R DataWidth:0x20 // 32-bit Vendor Defined DW…
71730 … (0xff<<16) // This is the 8-bit Tag from VDM Head…
71734 … the look-up is bypassed and the scratchpad is always accessed with the address that was provided …
71736 … 0xe06308UL //Access:W DataWidth:0x20 // Any write to this register will s…
71744 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71753 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71762 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71771 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71780 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71789 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71798 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71807 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71816 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71825 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71834 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71843 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71852 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71861 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71870 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71879 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71884 … Expansion ROM Engine Baddr register used in the cache fetch logic. Reset value points to Engine 0.
71889 … Expansion ROM Engine Gaddr register used in the cache fetch logic. Reset value points to Engine 0.
71894 … Expansion ROM Engine Caddr register used in the cache fetch logic. Reset value points to Engine 0.
71899 … Expansion ROM Engine Cdata register used in the cache fetch logic. Reset value points to Engine 0.
71904 …he Expansion ROM Engine Cfg register used in the cache fetch logic. Reset value points to Engine 0.
71906 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction hi…
71907 …//Access:RW DataWidth:0x20 // Statistic: Incremented whenever a Pageable-memory instruction mi…
71915 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71924 …) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the p…
71930 … (0x1<<1) // If set, a read attempt to a second page was de…
71937 …sserted until doit is reasserted or the done bit is cleared by writing a 1 to the done bit. The do…
71939 … (0x1<<4) // Command from software to start the defined co…
71941 … (0x1<<5) // The Write/Not_Read command bit. Set high to execute write or era…
71943 … (0x1<<6) // The erase page/sector command bit. Set high to execute a page/secto…
71945 … (0x1<<7) // This bit is passed to the SEE_FSM or SPI_F…
71947 … any cleanup work will be done. This means that the buffer will be written to flash memory if need…
71949 … command sequence has finished. Intended to be used for consecutive read or write access eliminati…
71953 …nterface state machine Generate wren_cmd to flash device through SPI interface to set Flash device…
71955 …nterface state machine Generate wrdi_cmd to flash device through SPI interface to set Flash device…
71957 … (0x1<<18) // The erase all/chip command bit. Set high to execute an all/chip …
71965 …to the block. This mode is normally on. The mode helps convert a 264B page Atmel part to act more …
71972 …/ 24 bit address value used in read, write and erase operations. When in bit-bang mode, the bottom…
71976 …0x1<<0) // Legacy strap_value[1]. Read only. Set based on new strap values to indicate either Atme…
71978 …0x1<<1) // Legacy strap_value[0]. Read only. Set based on new strap values to indicate either Atme…
71980 … (0x1<<2) // Enable pass-thru mode to the byte level…
71982 … (0x1<<3) // Enable bit-bang mode to control pins.
71984 …to interpret as the "ready" flag. For Atmel, this defaults to 3'h7. For ST, this defaults to 3'h0.…
71986 …to create all "1x" time for all Flash Interface I/O pin timing definition A value of 0 means that …
71992 … (0x1<<23) // Legacy strap_control[1] bit. Read only set to 1, indicating FLASH …
71994 …x1<<24) // Legacy strap_value[2]. Read only. Set based on new strap values to indicate either Atme…
71996 …x1<<25) // Legacy strap_value[3]. Read only. Set based on new strap values to indicate either Atme…
71998 …x1<<26) // Legacy strap_value[1]. Read only. Set based on new strap values to indicate either Atme…
72000 …x1<<27) // Legacy strap_value[0]. Read only. Set based on new strap values to indicate either Atme…
72002 …x1<<28) // Legacy strap_value[2]. Read only. Set based on new strap values to indicate either Atme…
72004 …x1<<29) // Legacy strap_value[3]. Read only. Set based on new strap values to indicate either Atme…
72006 … (0x1<<30) // Legacy strap_control[1] bit. Read only set to 1, indicating FLASH …
72013 …0xff<<8) // Controls the delay from the CSB assertion to the first clock and from the last clock t…
72015 … (0xff<<16) // Flash status command. This command is used to poll the "ready" sta…
72017 … (0xff<<24) // Flash Read ID register command. This command is used to read the ID register…
72020 … (0xff<<0) // Transfer flash device page to its internal buffer …
72022 …to write one byte to the flash array or SSRAM buffer, depending on the value of buffer_mode. If BU…
72024 …is command, any number of bytes may be read up to the end of the flash memory. This command is sim…
72026 …to the end of the flash memory. For SEEPROM (flash_mode=0), this is SEEPROM read command. Bit[26:2…
72029 …) // Set Software Arbitration request Bit 0. This bit is set by writing a '1' to this bit position.
72031 …) // Set Software Arbitration request Bit 1. This bit is set by writing a '1' to this bit position.
72033 …) // Set Software Arbitration request Bit 2. This bit is set by writing a '1' to this bit position.
72035 …) // Set Software Arbitration request Bit 3. This bit is set by writing a '1' to this bit position.
72037 … (0x1<<4) // Write this bit as a '1' to clear req0 bit.
72039 … (0x1<<5) // Write this bit as a '1' to clear req1 bit.
72041 … (0x1<<6) // Write this bit as a '1' to clear req2 bit.
72043 … (0x1<<7) // Write this bit as a '1' to clear req3 bit.
72045 …ead as 1, when an operation is complete, then the CLR_ARB0 must be written to clear this bit. At t…
72047 …l be read as 1, when an operation is complete, then the CLR_ARB1 must be written to clear this bit.
72049 …l be read as 1, when an operation is complete, then the CLR_ARB2 must be written to clear this bit.
72051 …l be read as 1, when an operation is complete, then the CLR_ARB3 must be written to clear this bit.
72062 … (0xff<<0) // Length of extended device info to follow.
72069 …flash interface state machine through SPI interface To flash device, and make the flash device wri…
72071 …flash interface state machine through SPI interface To flash device, and make the flash device wri…
72077 …to 1, write operations to Flash will use an internal 4KB sector buffer. Some Flash (Macronix, Winb…
72079 … (0x1<<31) // Set to 1 to use legacy/previous flsh_spi_fsm. Clear t…
72082 …s not used by FLSH hardware. It is only used by software. This value is self-configured on reset b…
72084 … (0x1<<3) // This bit is self-configured on reset b…
72086 …to insert an empty address bit when MODE_256 is not set with Atmel devices. This value is self-con…
72088 …1, then 1 means "ready". For Atmel, this defaults to 1. For ST, this defaults to 0. This value is …
72090 …d. It should be cleared when using the 0x68 read command. This value is self-configured on reset b…
72092 …nput from the external flash device is latched one cycle later than normal. This bit defaults to 0.
72094 …de, this bit should be set whenever the si_input_relaxed_timing bit is set. This bit defaults to 0.
72096 … bit should only be set when the legacy status read command (0x57) is used. This bit defaults to 0.
72102 …ng f(SCLK) = f(core_clk)/(2*(SPI_SLOW_CLK_DIV +1)). [Ex: SPI_SLOW_CLK_DIV=0 -> f(SCLK) = f(core…
72104 …to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated f…
72106 …to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated f…
72108 …to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated f…
72110 …to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated f…
72112 …to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated f…
72114 …to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated f…
72116 …to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated f…
72118 …to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated f…
72120 …to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated f…
72122 … 0xe06430UL //Access:RW DataWidth:0x20 // NVM re-configuration registe…
72125 … (0xf<<4) // Used by software to numerically encode how the FLSH has been reconfigured. On reset,…
72129 …eset. After software finishes reconfiguring FLSH, they will set this bit to 1 to indicate that FLS…
72132 …d, the engine will not service a new request and the on chip cpu will have to take over the chores.
72134 …en this bit is set to '1', the expansion ROM engine will utilize the buffered mode address transla…
72138 … (0x3<<4) // Request number to use to arbitrate for expansion ROM access …
72146 … (0x1<<28) // This bit is set to '1' when the cache i…
72148 … (0x1<<29) // This bit is set to '1' when an arbitrat…
72150 … (0x1<<30) // This bit is set to '1' when a read time…
72152 … (0x1<<31) // This bit is set to '1' when the expansi…
72160 … The value of 0x20 is shifted left number of bits determined by this value to determine the number…
72162 …er of bits determined by this value to determine the number of core clocks to wait for the expansi…
72167 …it will place the offset from the BAR value in this register and re-try the PCI bus to make the re…
72169 … (0x3<<24) // The size of the PCI BAR rom read request. This value ranges from 1 to 3 dwords
72173 …ll be set if there is a pending request for action. This bit is equivalent to the EXP_ROM_ATTN att…
72193 …is register provides the value of the completion data that will be written to the completion addre…
72197 … granularity. A maximum of 64KB can be transfered with one command. A read to this register will i…
72201 …to arbitrate for access to the NVRAM. Once a master wins arbitration, it can keep the NVRAM till t…
72203 … (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4b…
72211 …oader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
72230 …is register provides the value of the completion data that will be written to the completion addre…
72234 … granularity. A maximum of 64KB can be transfered with one command. A read to this register will i…
72238 …to arbitrate for access to the NVRAM. Once a master wins arbitration, it can keep the NVRAM till t…
72240 … (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4b…
72248 …oader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
72267 …is register provides the value of the completion data that will be written to the completion addre…
72271 … granularity. A maximum of 64KB can be transfered with one command. A read to this register will i…
72275 …to arbitrate for access to the NVRAM. Once a master wins arbitration, it can keep the NVRAM till t…
72277 … (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4b…
72285 …oader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
72294 … (0x1<<8) // When this bit is set the SMBUS block will respond to ARP that is it to SMBUS Devic…
72296 … (0x1<<9) // When this bit is set the SMBUS block will respond to ARP that is it to SMBUS Devic…
72300 …as specified in this register before it reports lost of arbitration status to the firmware. When t…
72306 … (0x1<<27) // When this bit is '1' the SMBUS block responds to all SMBUS transactio…
72308 … (0x1<<28) // When this bit is '1' the SMBUS block responds to slave address 7'b000…
72310 … bit is '1', the SMBUS block is placed into bit-bang mode. SMBUS interface pins are controlled usi…
72312 …d slave behavior at the end of the current transaction and stop responding to the SMBUS master/sla…
72314 … (0x1<<31) // When this bit is set it will reset SMBUS block to its default state.
72321 …for which slave device is allowed to stretch the clock from the beginning to end of the message (t…
72323 …lave. This is useful in "legacy mode" to allow firmware time to handle the data. Note that this ti…
72328 … (0x7f<<0) // This is the first SM Bus addresses which will be used to match for incoming m…
72330 …<<7) // When this bit is '1' NIC_SMB_ADDR0 will be used as a slave address to match for incoming m…
72332 … (0x7f<<8) // This is the second SM Bus addresses which will be used to match for incoming m…
72334 …<15) // When this bit is '1' NIC_SMB_ADDR1 will be used as a slave address to match for incoming m…
72336 … (0x7f<<16) // This is the third SM Bus addresses which will be used to match for incoming m…
72338 …<23) // When this bit is '1' NIC_SMB_ADDR2 will be used as a slave address to match for incoming m…
72340 … (0x7f<<24) // This is the fourth SM Bus addresses which will be used to match for incoming m…
72342 …<31) // When this bit is '1' NIC_SMB_ADDR3 will be used as a slave address to match for incoming m…
72347 …the SMBUS block will generate an event for the control processor. When set to 0x0 event generation…
72362 …the SMBUS block will generate an event for the control processor. When set to 0x0 event generation…
72377 … (0x1<<28) // When the SMBUS interface is configured for bit-bang mode, this bit c…
72381 … (0x1<<30) // When the SM Bus interface is configured for bit-bang mode, this bit c…
72386 … (0xffff<<0) // This value counts down to zero once each secon…
72389 … (0xffff<<0) // This value counts down to zero once each secon…
72392 … (0xffff<<0) // This value counts down to zero once each 5 mse…
72395 … (0xffff<<0) // This value counts down to zero once each 250 m…
72398 … (0xff<<0) // This value counts down to zero once each secon…
72400 …s:RW DataWidth:0x20 // This value counts up once each second and rolls to zero each time it pa…
72402 …- Block Read Process Call or Block Read. If this field is 0 the SMBUS block will assume that first…
72414 …rt. This bit can be set at any time by the firmware or the driver in order to abort the transactio…
72416 …to a '1', the currently programmed SMBUS transaction will activate. Writing this bit as a '0' has …
72429 …rt. This bit can be set at any time by the firmware or the driver in order to abort the transactio…
72431 …to a '1', the currently programmed SMBUS transaction will activate. Writing this bit as a '0' has …
72434 … (0x1<<0) // When set enables Watchdog Timer to generate smbus event.
72436 … (0x1<<1) // When set enables Heartbeat Timer to generate smbus event.
72438 … (0x1<<2) // When set enables ASF Sensor Poll Timer to generate smbus event.
72440 … (0x1<<3) // When set enables Legacy Sensor Poll Timer to generate smbus event.
72442 … (0x1<<4) // When set enables Retransmit Timer to generate smbus event.
72446 … (0x1<<20) // When set enables hardware to generate smbus event…
72448 … (0x1<<21) // Enables SLAVE_RD_EVENT to generate smbus event.
72452 … (0x1<<23) // When set enables generation of a smbus event on slave START_BUSY 1 to 0 transition.
72454 … (0x1<<24) // Enables SLAVE_RX_EVENT to generate smbus event.
72456 … (0x1<<25) // When set enables SLAVE_RX_THRESHOLD_HIT to generate smbus event.
72458 … (0x1<<26) // When set enables SLAVE_RX_FIFO_FULL to generate smbus event.
72462 … (0x1<<28) // When set enables generation of a smbus event on master START_BUSY 1 to 0 transition.
72464 … (0x1<<29) // When set enables MASTER_RX_EVENT to generate smbus event.
72466 … (0x1<<30) // When set enables MASTER_RX_THRESHOLD_HIT to generate smbus event.
72468 … (0x1<<31) // When set enables MASTER_RX_FIFO_FULL to generate smbus event.
72471 … (0x1<<0) // This bit changes to '1' each time the WATCHDOG timer reaches zero. Writi…
72473 … (0x1<<1) // This bit changes to '1' each time the HEARTBEAT timer reaches zero. Writ…
72475 … (0x1<<2) // This bit changes to '1' each time the POLL_ASF timer reaches zero. Writi…
72477 … (0x1<<3) // This bit changes to '1' each time the POLL_LEGACY timer reaches zero. Wri…
72479 … (0x1<<4) // This bit changes to '1' each time the RETRANSMIT timer reaches zero. Writ…
72485 …e detected read transaction directed toward the SMBUS block. Writing a '1' to this position will c…
72489 …<23) // This bit is set when slave START_BUSY transitions from 1 to 0. Writing a '1' to this posit…
72491 …the slave receive FIFO holds at least one valid transaction. Writing a '1' to this position will c…
72493 … is set when the slave receive FIFO is equal to or larger than the Slave RX_FIFO_THRESHOLD. Writin…
72495 … // This bit is set when the slave receive FIFO become full. Writing a '1' to this position will c…
72499 …28) // This bit is set when master START_BUSY transitions from 1 to 0. Writing a '1' to this posit…
72501 …he master receive FIFO holds at least one valid transaction. Writing a '1' to this position will c…
72503 …s set when the master receive FIFO is equal to or larger than the Master RX_FIFO_THRESHOLD. Writin…
72505 …// This bit is set when the master receive FIFO become full. Writing a '1' to this position will c…
72508 …0xff<<0) // This is a software interface to the SMBUS Master Transmit FIFO. Software should use th…
72512 … (0x1<<31) // 0 - Byte other then last in an WMBUS transaction …
72515 …MSB first). This is a software interface to the SMBUS Master Receive FIFO. Software should use thi…
72524 …0xff<<0) // This is a software interface to the SMBUS Slave Transmit FIFO. Software should use thi…
72531 …(0xff<<0) // This is a software interface to the SMBUS Slave Receive FIFO. Software should use thi…
72540 …ld be set by firmware before ARP_EN0 bit is set. This bit is typically set to '1' based on the NVR…
72542 … bit should be set by firmware before ARP_EN0 bit is set. This bit is typically initialized to '0'.
72546 …ld be set by firmware before ARP_EN1 bit is set. This bit is typically set to '1' based on the NVR…
72548 … bit should be set by firmware before ARP_EN1 bit is set. This bit is typically initialized to '0'.
72624 … (0x1<<0) // Setting this bit to '1' will flush the p…
72626 … (0x1<<1) // Setting this bit to '1' will set the err…
72637 … (0x1<<0) // This bit indicates that the write to BMB has been complet…
72645 … (0x1<<0) // Setting this bit to '1' will indicate th…
72649 … (0x1<<4) // Setting this bit to '1' will flush the c…
72651 … (0x1<<5) // Setting this bit to '1' will clear all p…
72682 …DataWidth:0x20 // This location provides a location for the ROM contents to be read for debug po…
72684 … processor. This can be modified at any time and may be used for processor-to-processor communicat…
72700 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
72702 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
72704 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
72706 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
72708 … (0x1<<10) // Enable for input acknowledge to credit counter from …
72716 … (0x1<<14) // Enable for input ack to CCFC load credit cou…
72718 … (0x1<<15) // Enable for input ack to TCFC load credit cou…
72722 … (0x1<<17) // Enable for input ack to CCFC credit counter …
72724 … (0x1<<18) // Enable for input ack to TCFC credit counter …
72736 … (0x1<<0) // Enable for output request to pxp internal write f…
72738 … (0x1<<1) // Enable for output thread ready to the SEMI.
72742 … (0x1<<3) // Enable for output load request to CCFC.
72744 … (0x1<<4) // Enable for output load request to TCFC.
72746 … (0x1<<5) // Enable for output increment to CCFC activity counte…
72748 … (0x1<<6) // Enable for output decrement to TCFC activity counte…
72750 … (0x1<<7) // Enable for output data to pxp-HW interface in DM…
72752 … (0x1<<8) // Enable for output request to BRB interface in DMA…
72754 … (0x1<<9) // Enable for output write to int_ram in DMA_DST b…
72758 … (0x1<<11) // Enable for output write to pxp async in DMA_DST…
72760 … (0x1<<12) // Enable for output write to pxp in DMA_DST bloc…
72762 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
72764 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
72766 … (0x1<<15) // Enable for output external full to SEMI block.
72768 … (0x1<<16) // Enable for output done to async PXP host IF.
72770 … (0x1<<17) // Enable the output done (ack) to PRM.
72772 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
72774 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
72776 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
72779 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
72786 … (0x1<<0) // This bit should be set to disable the DMA exec…
72788 … (0x1<<1) // This bit should be set to disable the timers' …
72790 … (0x1<<2) // This bit should be set to disable the CCFC exe…
72792 … (0x1<<3) // This bit should be set to disable the TCFC exe…
72794 … (0x1<<4) // This bit should be set to disable the internal…
72796 … (0x1<<5) // This bit should be set to disable the SDM NOP …
72798 … (0x1<<6) // This bit should be set to disable the GRC mast…
72800 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processin…
72802 … (0x1<<8) // This bit should be set to disable the PRM inte…
72804 … (0x1<<9) // This bit should be set to disable the DORQ DPM…
72807 … (0x1<<0) // Signals an unknown address to the rf module.
72815 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72863 …M_E5 (0x1<<28) // Attempted to allocate a timer com…
72865 … (0x1<<29) // Last-cycle indication not …
72933 … (0x1<<0) // Signals an unknown address to the rf module.
72941 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
72989 …_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
72991 …E5 (0x1<<29) // Last-cycle indication not …
72996 … (0x1<<0) // Signals an unknown address to the rf module.
73004 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73052 …G_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
73054 …_E5 (0x1<<29) // Last-cycle indication not …
73094 …ataWidth:0x20 // Defines the number of system clock cycles that are used to define a timers cloc…
73096 …to assert a completion operation of choice; It includes the following completion fields: bits 19:1…
73100 …to the round robin arbiter used for all completion write requests in the completion manager: b0-P…
73101 …cess to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b…
73102 …s read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM …
73103 … to be read in the event of an inp_queue_error interrupt. It contains a vector with a bit per inp…
73104 …ion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async i…
73106 …s:RW DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface wi…
73107 … DataWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the in…
73108 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the TCFC activity co…
73109 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the CCFC activity co…
73110 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to the CM interface wit…
73111 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to a remote CM interfac…
73127 …to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_…
73130 … //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggre…
73158 … Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion…
73159 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
73186 …Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion…
73187 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
73199 … 0xf80e28UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
73200 … line) in the selected line (before shift).for selecting a line to output
73204 … 0xf82000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73206 … 0xf82400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73208 … 0xf82800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73210 … 0xf82c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73212 … 0xf83000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73214 … 0xf83400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73216 … 0xf83800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73218 … 0xf83c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73220 … 0xf84000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write access to the tim…
73241 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73243 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
73245 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73247 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73249 … (0x1<<10) // Enable for input acknowledge to credit counter from …
73257 … (0x1<<14) // Enable for input ack to CCFC load credit cou…
73259 … (0x1<<15) // Enable for input ack to TCFC load credit cou…
73263 … (0x1<<17) // Enable for input ack to CCFC credit counter …
73265 … (0x1<<18) // Enable for input ack to TCFC credit counter …
73277 … (0x1<<0) // Enable for output request to pxp internal write f…
73279 … (0x1<<1) // Enable for output thread ready to the SEMI.
73283 … (0x1<<3) // Enable for output load request to CCFC.
73285 … (0x1<<4) // Enable for output load request to TCFC.
73287 … (0x1<<5) // Enable for output increment to CCFC activity counte…
73289 … (0x1<<6) // Enable for output decrement to TCFC activity counte…
73291 … (0x1<<7) // Enable for output data to pxp-HW interface in DM…
73293 … (0x1<<8) // Enable for output request to BRB interface in DMA…
73295 … (0x1<<9) // Enable for output write to int_ram in DMA_DST b…
73299 … (0x1<<11) // Enable for output write to pxp async in DMA_DST…
73301 … (0x1<<12) // Enable for output write to pxp in DMA_DST bloc…
73303 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
73305 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
73307 … (0x1<<15) // Enable for output external full to SEMI block.
73309 … (0x1<<16) // Enable for output done to async PXP host IF.
73311 … (0x1<<17) // Enable the output done (ack) to PRM.
73313 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
73315 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
73317 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
73320 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
73327 … (0x1<<0) // This bit should be set to disable the DMA exec…
73329 … (0x1<<1) // This bit should be set to disable the timers' …
73331 … (0x1<<2) // This bit should be set to disable the CCFC exe…
73333 … (0x1<<3) // This bit should be set to disable the TCFC exe…
73335 … (0x1<<4) // This bit should be set to disable the internal…
73337 … (0x1<<5) // This bit should be set to disable the SDM NOP …
73339 … (0x1<<6) // This bit should be set to disable the GRC mast…
73341 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processin…
73343 … (0x1<<8) // This bit should be set to disable the PRM inte…
73345 … (0x1<<9) // This bit should be set to disable the DORQ DPM…
73348 … (0x1<<0) // Signals an unknown address to the rf module.
73356 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73404 …M_E5 (0x1<<28) // Attempted to allocate a timer com…
73406 … (0x1<<29) // Last-cycle indication not …
73474 … (0x1<<0) // Signals an unknown address to the rf module.
73482 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73530 …_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
73532 …E5 (0x1<<29) // Last-cycle indication not …
73537 … (0x1<<0) // Signals an unknown address to the rf module.
73545 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73593 …G_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
73595 …_E5 (0x1<<29) // Last-cycle indication not …
73631 …ataWidth:0x20 // Defines the number of system clock cycles that are used to define a timers cloc…
73633 …to assert a completion operation of choice; It includes the following completion fields: bits 19:1…
73637 …to the round robin arbiter used for all completion write requests in the completion manager: b0-P…
73638 …cess to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b…
73639 …s read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM …
73640 … to be read in the event of an inp_queue_error interrupt. It contains a vector with a bit per inp…
73641 …ion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async i…
73643 …s:RW DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface wi…
73644 … DataWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the in…
73645 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the TCFC activity co…
73646 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the CCFC activity co…
73647 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to the CM interface wit…
73648 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to a remote CM interfac…
73665 …to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_…
73668 … //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggre…
73696 … Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion…
73697 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
73724 …Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion…
73725 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
73737 … 0xf90e28UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
73738 … line) in the selected line (before shift).for selecting a line to output
73742 … 0xf92000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
73744 … 0xf92400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
73746 … 0xf92800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
73748 … 0xf92c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
73750 … 0xf93000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
73752 … 0xf93400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
73754 … 0xf93800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
73756 … 0xf93c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
73758 … 0xf94000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write access to the tim…
73779 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
73781 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
73783 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
73785 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
73787 … (0x1<<10) // Enable for input acknowledge to credit counter from …
73795 … (0x1<<14) // Enable for input ack to CCFC load credit cou…
73797 … (0x1<<15) // Enable for input ack to TCFC load credit cou…
73801 … (0x1<<17) // Enable for input ack to CCFC credit counter …
73803 … (0x1<<18) // Enable for input ack to TCFC credit counter …
73815 … (0x1<<0) // Enable for output request to pxp internal write f…
73817 … (0x1<<1) // Enable for output thread ready to the SEMI.
73821 … (0x1<<3) // Enable for output load request to CCFC.
73823 … (0x1<<4) // Enable for output load request to TCFC.
73825 … (0x1<<5) // Enable for output increment to CCFC activity counte…
73827 … (0x1<<6) // Enable for output decrement to TCFC activity counte…
73829 … (0x1<<7) // Enable for output data to pxp-HW interface in DM…
73831 … (0x1<<8) // Enable for output request to BRB interface in DMA…
73833 … (0x1<<9) // Enable for output write to int_ram in DMA_DST b…
73837 … (0x1<<11) // Enable for output write to pxp async in DMA_DST…
73839 … (0x1<<12) // Enable for output write to pxp in DMA_DST bloc…
73841 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
73843 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
73845 … (0x1<<15) // Enable for output external full to SEMI block.
73847 … (0x1<<16) // Enable for output done to async PXP host IF.
73849 … (0x1<<17) // Enable the output done (ack) to PRM.
73851 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
73853 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
73855 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
73858 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
73865 … (0x1<<0) // This bit should be set to disable the DMA exec…
73867 … (0x1<<1) // This bit should be set to disable the timers' …
73869 … (0x1<<2) // This bit should be set to disable the CCFC exe…
73871 … (0x1<<3) // This bit should be set to disable the TCFC exe…
73873 … (0x1<<4) // This bit should be set to disable the internal…
73875 … (0x1<<5) // This bit should be set to disable the SDM NOP …
73877 … (0x1<<6) // This bit should be set to disable the GRC mast…
73879 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processin…
73881 … (0x1<<8) // This bit should be set to disable the PRM inte…
73883 … (0x1<<9) // This bit should be set to disable the DORQ DPM…
73886 … (0x1<<0) // Signals an unknown address to the rf module.
73894 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
73942 …M_E5 (0x1<<28) // Attempted to allocate a timer com…
73944 … (0x1<<29) // Last-cycle indication not …
74012 … (0x1<<0) // Signals an unknown address to the rf module.
74020 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74068 …_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
74070 …E5 (0x1<<29) // Last-cycle indication not …
74075 … (0x1<<0) // Signals an unknown address to the rf module.
74083 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74131 …G_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
74133 …_E5 (0x1<<29) // Last-cycle indication not …
74193 …ataWidth:0x20 // Defines the number of system clock cycles that are used to define a timers cloc…
74195 …to assert a completion operation of choice; It includes the following completion fields: bits 19:1…
74199 …to the round robin arbiter used for all completion write requests in the completion manager: b0-P…
74200 …cess to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b…
74201 …s read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM …
74202 … to be read in the event of an inp_queue_error interrupt. It contains a vector with a bit per inp…
74203 …ion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async i…
74205 …s:RW DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface wi…
74206 … DataWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the in…
74207 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the TCFC activity co…
74208 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the CCFC activity co…
74209 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to the CM interface wit…
74210 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to a remote CM interfac…
74227 …to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_…
74230 … //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggre…
74258 … Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion…
74259 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
74286 …Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion…
74287 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
74299 … 0xfa0e28UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
74300 … line) in the selected line (before shift).for selecting a line to output
74304 … 0xfa2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74306 … 0xfa2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74308 … 0xfa2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74310 … 0xfa2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74312 … 0xfa3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74314 … 0xfa3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74316 … 0xfa3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74318 … 0xfa3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74320 … 0xfa4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write access to the tim…
74341 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74343 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
74345 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74347 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74349 … (0x1<<10) // Enable for input acknowledge to credit counter from …
74357 … (0x1<<14) // Enable for input ack to CCFC load credit cou…
74359 … (0x1<<15) // Enable for input ack to TCFC load credit cou…
74363 … (0x1<<17) // Enable for input ack to CCFC credit counter …
74365 … (0x1<<18) // Enable for input ack to TCFC credit counter …
74377 … (0x1<<0) // Enable for output request to pxp internal write f…
74379 … (0x1<<1) // Enable for output thread ready to the SEMI.
74383 … (0x1<<3) // Enable for output load request to CCFC.
74385 … (0x1<<4) // Enable for output load request to TCFC.
74387 … (0x1<<5) // Enable for output increment to CCFC activity counte…
74389 … (0x1<<6) // Enable for output decrement to TCFC activity counte…
74391 … (0x1<<7) // Enable for output data to pxp-HW interface in DM…
74393 … (0x1<<8) // Enable for output request to BRB interface in DMA…
74395 … (0x1<<9) // Enable for output write to int_ram in DMA_DST b…
74399 … (0x1<<11) // Enable for output write to pxp async in DMA_DST…
74401 … (0x1<<12) // Enable for output write to pxp in DMA_DST bloc…
74403 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
74405 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
74407 … (0x1<<15) // Enable for output external full to SEMI block.
74409 … (0x1<<16) // Enable for output done to async PXP host IF.
74411 … (0x1<<17) // Enable the output done (ack) to PRM.
74413 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
74415 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
74417 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
74420 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
74427 … (0x1<<0) // This bit should be set to disable the DMA exec…
74429 … (0x1<<1) // This bit should be set to disable the timers' …
74431 … (0x1<<2) // This bit should be set to disable the CCFC exe…
74433 … (0x1<<3) // This bit should be set to disable the TCFC exe…
74435 … (0x1<<4) // This bit should be set to disable the internal…
74437 … (0x1<<5) // This bit should be set to disable the SDM NOP …
74439 … (0x1<<6) // This bit should be set to disable the GRC mast…
74441 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processin…
74443 … (0x1<<8) // This bit should be set to disable the PRM inte…
74445 … (0x1<<9) // This bit should be set to disable the DORQ DPM…
74448 … (0x1<<0) // Signals an unknown address to the rf module.
74456 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74504 …M_E5 (0x1<<28) // Attempted to allocate a timer com…
74506 … (0x1<<29) // Last-cycle indication not …
74574 … (0x1<<0) // Signals an unknown address to the rf module.
74582 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74630 …_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
74632 …E5 (0x1<<29) // Last-cycle indication not …
74637 … (0x1<<0) // Signals an unknown address to the rf module.
74645 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
74693 …G_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
74695 …_E5 (0x1<<29) // Last-cycle indication not …
74735 …ataWidth:0x20 // Defines the number of system clock cycles that are used to define a timers cloc…
74737 …to assert a completion operation of choice; It includes the following completion fields: bits 19:1…
74741 …to the round robin arbiter used for all completion write requests in the completion manager: b0-P…
74742 …cess to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b…
74743 …s read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM …
74744 … to be read in the event of an inp_queue_error interrupt. It contains a vector with a bit per inp…
74745 …ion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async i…
74747 …s:RW DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface wi…
74748 … DataWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the in…
74749 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the TCFC activity co…
74750 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the CCFC activity co…
74751 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to the CM interface wit…
74752 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to a remote CM interfac…
74768 …to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_…
74771 … //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggre…
74799 … Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion…
74800 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
74827 …Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion…
74828 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
74840 … 0xfb0e28UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
74841 … line) in the selected line (before shift).for selecting a line to output
74845 … 0xfb2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
74847 … 0xfb2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
74849 … 0xfb2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
74851 … 0xfb2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
74853 … 0xfb3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
74855 … 0xfb3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
74857 … 0xfb3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
74859 … 0xfb3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
74861 … 0xfb4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write access to the tim…
74882 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
74884 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
74886 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
74888 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
74890 … (0x1<<10) // Enable for input acknowledge to credit counter from …
74898 … (0x1<<14) // Enable for input ack to CCFC load credit cou…
74900 … (0x1<<15) // Enable for input ack to TCFC load credit cou…
74904 … (0x1<<17) // Enable for input ack to CCFC credit counter …
74906 … (0x1<<18) // Enable for input ack to TCFC credit counter …
74918 … (0x1<<0) // Enable for output request to pxp internal write f…
74920 … (0x1<<1) // Enable for output thread ready to the SEMI.
74924 … (0x1<<3) // Enable for output load request to CCFC.
74926 … (0x1<<4) // Enable for output load request to TCFC.
74928 … (0x1<<5) // Enable for output increment to CCFC activity counte…
74930 … (0x1<<6) // Enable for output decrement to TCFC activity counte…
74932 … (0x1<<7) // Enable for output data to pxp-HW interface in DM…
74934 … (0x1<<8) // Enable for output request to BRB interface in DMA…
74936 … (0x1<<9) // Enable for output write to int_ram in DMA_DST b…
74940 … (0x1<<11) // Enable for output write to pxp async in DMA_DST…
74942 … (0x1<<12) // Enable for output write to pxp in DMA_DST bloc…
74944 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
74946 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
74948 … (0x1<<15) // Enable for output external full to SEMI block.
74950 … (0x1<<16) // Enable for output done to async PXP host IF.
74952 … (0x1<<17) // Enable the output done (ack) to PRM.
74954 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
74956 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
74958 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
74961 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
74968 … (0x1<<0) // This bit should be set to disable the DMA exec…
74970 … (0x1<<1) // This bit should be set to disable the timers' …
74972 … (0x1<<2) // This bit should be set to disable the CCFC exe…
74974 … (0x1<<3) // This bit should be set to disable the TCFC exe…
74976 … (0x1<<4) // This bit should be set to disable the internal…
74978 … (0x1<<5) // This bit should be set to disable the SDM NOP …
74980 … (0x1<<6) // This bit should be set to disable the GRC mast…
74982 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processin…
74984 … (0x1<<8) // This bit should be set to disable the PRM inte…
74986 … (0x1<<9) // This bit should be set to disable the DORQ DPM…
74989 … (0x1<<0) // Signals an unknown address to the rf module.
74997 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75045 …M_E5 (0x1<<28) // Attempted to allocate a timer com…
75047 … (0x1<<29) // Last-cycle indication not …
75115 … (0x1<<0) // Signals an unknown address to the rf module.
75123 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75171 …_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
75173 …E5 (0x1<<29) // Last-cycle indication not …
75178 … (0x1<<0) // Signals an unknown address to the rf module.
75186 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75234 …G_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
75236 …_E5 (0x1<<29) // Last-cycle indication not …
75304 …ataWidth:0x20 // Defines the number of system clock cycles that are used to define a timers cloc…
75306 …to assert a completion operation of choice; It includes the following completion fields: bits 19:1…
75310 …to the round robin arbiter used for all completion write requests in the completion manager: b0-P…
75311 …cess to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b…
75312 …s read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM …
75313 … to be read in the event of an inp_queue_error interrupt. It contains a vector with a bit per inp…
75314 …ion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async i…
75316 …s:RW DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface wi…
75317 … DataWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the in…
75318 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the TCFC activity co…
75319 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the CCFC activity co…
75320 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to the CM interface wit…
75321 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to a remote CM interfac…
75339 …to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_…
75342 … //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggre…
75370 … Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion…
75371 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
75398 …Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion…
75399 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
75411 … 0xfc0e28UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
75412 … line) in the selected line (before shift).for selecting a line to output
75416 … 0xfc2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75418 … 0xfc2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75420 … 0xfc2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75422 … 0xfc2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75424 … 0xfc3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75426 … 0xfc3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75428 … 0xfc3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75430 … 0xfc3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75432 … 0xfc4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write access to the tim…
75453 … (0x1<<6) // Enable for input done from pxp-HW interface in DMA_D…
75455 … (0x1<<7) // Enable for input full from pxp-HW interface in DMA_D…
75457 … (0x1<<8) // Enable for input data from pxp-HW interface in DMA_R…
75459 … (0x1<<9) // Enable for input ack from pxp-internal write for SD…
75461 … (0x1<<10) // Enable for input acknowledge to credit counter from …
75469 … (0x1<<14) // Enable for input ack to CCFC load credit cou…
75471 … (0x1<<15) // Enable for input ack to TCFC load credit cou…
75475 … (0x1<<17) // Enable for input ack to CCFC credit counter …
75477 … (0x1<<18) // Enable for input ack to TCFC credit counter …
75489 … (0x1<<0) // Enable for output request to pxp internal write f…
75491 … (0x1<<1) // Enable for output thread ready to the SEMI.
75495 … (0x1<<3) // Enable for output load request to CCFC.
75497 … (0x1<<4) // Enable for output load request to TCFC.
75499 … (0x1<<5) // Enable for output increment to CCFC activity counte…
75501 … (0x1<<6) // Enable for output decrement to TCFC activity counte…
75503 … (0x1<<7) // Enable for output data to pxp-HW interface in DM…
75505 … (0x1<<8) // Enable for output request to BRB interface in DMA…
75507 … (0x1<<9) // Enable for output write to int_ram in DMA_DST b…
75511 … (0x1<<11) // Enable for output write to pxp async in DMA_DST…
75513 … (0x1<<12) // Enable for output write to pxp in DMA_DST bloc…
75515 … (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
75517 … (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
75519 … (0x1<<15) // Enable for output external full to SEMI block.
75521 … (0x1<<16) // Enable for output done to async PXP host IF.
75523 … (0x1<<17) // Enable the output done (ack) to PRM.
75525 … (0x1<<18) // Enable for output message to CM in SDM_CM block.
75527 … (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
75529 … (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
75532 … (0x1<<0) // Enable for output command to qm in SDM_INP block.
75539 … (0x1<<0) // This bit should be set to disable the DMA exec…
75541 … (0x1<<1) // This bit should be set to disable the timers' …
75543 … (0x1<<2) // This bit should be set to disable the CCFC exe…
75545 … (0x1<<3) // This bit should be set to disable the TCFC exe…
75547 … (0x1<<4) // This bit should be set to disable the internal…
75549 … (0x1<<5) // This bit should be set to disable the SDM NOP …
75551 … (0x1<<6) // This bit should be set to disable the GRC mast…
75553 … (0x1<<7) // This bit should be set to disable the PXP-Async interface from processin…
75555 … (0x1<<8) // This bit should be set to disable the PRM inte…
75557 … (0x1<<9) // This bit should be set to disable the DORQ DPM…
75560 … (0x1<<0) // Signals an unknown address to the rf module.
75568 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75616 …M_E5 (0x1<<28) // Attempted to allocate a timer com…
75618 … (0x1<<29) // Last-cycle indication not …
75686 … (0x1<<0) // Signals an unknown address to the rf module.
75694 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75742 …_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
75744 …E5 (0x1<<29) // Last-cycle indication not …
75749 … (0x1<<0) // Signals an unknown address to the rf module.
75757 … (0x1<<4) // FIFO in PRM interface sub-module reported an er…
75805 …G_NUM_E5 (0x1<<28) // Attempted to allocate a timer com…
75807 …_E5 (0x1<<29) // Last-cycle indication not …
75847 …ataWidth:0x20 // Defines the number of system clock cycles that are used to define a timers cloc…
75849 …to assert a completion operation of choice; It includes the following completion fields: bits 19:1…
75853 …to the round robin arbiter used for all completion write requests in the completion manager: b0-P…
75854 …cess to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b…
75855 …s read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM …
75856 … to be read in the event of an inp_queue_error interrupt. It contains a vector with a bit per inp…
75857 …ion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async i…
75859 …s:RW DataWidth:0x3 // The initial number of messages that can be sent to the pxp interface wi…
75860 … DataWidth:0x2 // The initial number of messages that can be sent to the PCI-Switch on the in…
75861 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the TCFC activity co…
75862 …s:RW DataWidth:0x4 // The initial number of messages that can be sent to the CCFC activity co…
75863 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to the CM interface wit…
75864 …ess:RW DataWidth:0x4 // The initial number of cycles that can be sent to a remote CM interfac…
75881 …to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_…
75884 … //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggre…
75912 … Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion…
75913 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
75940 …Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion…
75941 …nager block. This FIFO is used to queue the completion parameters for all direct message completio…
75953 … 0xfd0e28UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
75954 … line) in the selected line (before shift).for selecting a line to output
75958 … 0xfd2000UL //Access:WB_R DataWidth:0x49 // Provides read-only access of the PXP-Async inpu…
75960 … 0xfd2400UL //Access:WB_R DataWidth:0x40 // Provides read-only access of the im…
75962 … 0xfd2800UL //Access:WB_R DataWidth:0x86 // Provides read-only access of the BR…
75964 … 0xfd2c00UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the PX…
75966 … 0xfd3000UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the in…
75968 … 0xfd3400UL //Access:WB_R DataWidth:0x51 // Provides read-only access of the DO…
75970 … 0xfd3800UL //Access:WB_R DataWidth:0x4b // Provides read-only access of the ex…
75972 … 0xfd3c00UL //Access:WB_R DataWidth:0x41 // Provides read-only access of the PR…
75974 … 0xfd4000UL //Access:WB DataWidth:0x3d // Provides memory-mapped read/write access to the tim…
75982 …alises specific states and statuses. To initialise the state - write 1 into register; to enable wo…
75985 … 0x1000040UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
75986 … line) in the selected line (before shift).for selecting a line to output
76026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76027 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76029 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76031 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76033 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76035 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76037 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76039 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76041 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76043 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76044 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76045 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76046 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76047 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76048 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76049 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76050 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76051 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76052 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76053 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76054 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76055 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76056 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76057 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76058 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76059 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76060 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76061 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76062 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76063 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76064 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76065 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76066 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76067 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76068 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76069 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76070 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76071 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76073 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76076 … (0x1<<0) // Signals an unknown address to the rf module.
76078 … (0x1<<1) // Write to full STORM input buf…
76082 … (0x1<<3) // Write to full MSDM input buff…
76086 … (0x1<<5) // Write to full XSDM input buff…
76090 … (0x1<<7) // Write to full YSDM input buff…
76094 … (0x1<<9) // Write to full USDM input buff…
76098 … (0x1<<11) // Write to full Msem input buff…
76102 … (0x1<<13) // Write to full Usem input buff…
76106 … (0x1<<15) // Write to full Ysem input buff…
76110 … (0x1<<17) // Write to fully External read …
76150 … (0x1<<0) // Signals an unknown address to the rf module.
76152 … (0x1<<1) // Write to full STORM input buf…
76156 … (0x1<<3) // Write to full MSDM input buff…
76160 … (0x1<<5) // Write to full XSDM input buff…
76164 … (0x1<<7) // Write to full YSDM input buff…
76168 … (0x1<<9) // Write to full USDM input buff…
76172 … (0x1<<11) // Write to full Msem input buff…
76176 … (0x1<<13) // Write to full Usem input buff…
76180 … (0x1<<15) // Write to full Ysem input buff…
76184 … (0x1<<17) // Write to fully External read …
76187 … (0x1<<0) // Signals an unknown address to the rf module.
76189 … (0x1<<1) // Write to full STORM input buf…
76193 … (0x1<<3) // Write to full MSDM input buff…
76197 … (0x1<<5) // Write to full XSDM input buff…
76201 … (0x1<<7) // Write to full YSDM input buff…
76205 … (0x1<<9) // Write to full USDM input buff…
76209 … (0x1<<11) // Write to full Msem input buff…
76213 … (0x1<<13) // Write to full Usem input buff…
76217 … (0x1<<15) // Write to full Ysem input buff…
76221 … (0x1<<17) // Write to fully External read …
76226 … (0x1<<1) // Write to full Dorq input buff…
76230 … (0x1<<3) // Write to full Pbf input buffe…
76234 … (0x1<<5) // Write to full TM input buffer.
76238 … (0x1<<7) // Write to full QM input buffer.
76242 … (0x1<<9) // Write to full QM input buffer.
76246 … (0x1<<11) // Write to full GRC input buffe…
76250 … (0x1<<13) // Write to full GRC input buffe…
76254 … (0x1<<15) // Write to full GRC input buffe…
76258 … (0x1<<17) // Write to full GRC input buffe…
76262 … (0x1<<19) // In-process Table overflo…
76328 … (0x1<<1) // Write to full Dorq input buff…
76332 … (0x1<<3) // Write to full Pbf input buffe…
76336 … (0x1<<5) // Write to full TM input buffer.
76340 … (0x1<<7) // Write to full QM input buffer.
76344 … (0x1<<9) // Write to full QM input buffer.
76348 … (0x1<<11) // Write to full GRC input buffe…
76352 … (0x1<<13) // Write to full GRC input buffe…
76356 … (0x1<<15) // Write to full GRC input buffe…
76360 … (0x1<<17) // Write to full GRC input buffe…
76364 … (0x1<<19) // In-process Table overflo…
76379 … (0x1<<1) // Write to full Dorq input buff…
76383 … (0x1<<3) // Write to full Pbf input buffe…
76387 … (0x1<<5) // Write to full TM input buffer.
76391 … (0x1<<7) // Write to full QM input buffer.
76395 … (0x1<<9) // Write to full QM input buffer.
76399 … (0x1<<11) // Write to full GRC input buffe…
76403 … (0x1<<13) // Write to full GRC input buffe…
76407 … (0x1<<15) // Write to full GRC input buffe…
76411 … (0x1<<17) // Write to full GRC input buffe…
76415 … (0x1<<19) // In-process Table overflo…
76442 … (0x1<<7) // Access to illegal PQ number in…
76476 …NUM (0x1<<7) // Access to illegal PQ number in…
76493 …QNUM (0x1<<7) // Access to illegal PQ number in…
76781 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
76783 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76784 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76785 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76786 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76787 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76788 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76789 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76790 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76791 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76792 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76793 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76794 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76795 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76796 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76797 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76798 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76799 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76800 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76801 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76802 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76803 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76804 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76805 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76806 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76807 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76816 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76817 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76818 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76819 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76820 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76821 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76822 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76823 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76824 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76825 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76826 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76827 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76828 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76829 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76830 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76831 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76832 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76833 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76834 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76835 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76836 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
76849 … to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
76850 … to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
76851 … to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
76852 … to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
76853 … to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
76854 … to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
76855 …to perform non-usual arbitration operation relative to usual once in a while. Two values have spec…
76856 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76857 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76858 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76859 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76860 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76861 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76862 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76863 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76864 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76865 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
76866 … 0x1000680UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
76868 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
76874 …he size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by …
76876 … 0x1000710UL //Access:R DataWidth:0x7 // Used to read the XX protecti…
76877 … 0x1000714UL //Access:R DataWidth:0x7 // Used to read XX protection L…
76878 …L //Access:RC DataWidth:0x7 // CAM occupancy sticky status. The write to the register is perf…
76879 …:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1-…
76880 …:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1-…
76881 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
76883 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
76888 …// Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt g…
76889 …// Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt g…
76890 …// Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt g…
76891 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
76897 …r of locked messages per LCID is above this threshold is one of conditions to start XxBypass for t…
76901 … //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't …
76905 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76906 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76907 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76908 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76909 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76910 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76911 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76912 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76913 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76914 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76915 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76916 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76917 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76918 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76919 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76920 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76921 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76922 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76923 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76924 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76925 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76926 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76927 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76928 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
76941 …dth:0x3 // The size of AGG Connection context region 0 in REGQ. Is used to determine the number…
76942 …to 320 LCIDs. Maximum context size per LCID is 24. Maximum number of LCIDs allowed at maximum cont…
76943 … 0x1000904UL //Access:RW DataWidth:0xa // [9]: PQ Type (0-Other PQ; 1-TX PQ); if bit[…
76944 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
76945 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
76946 … 0x1000a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
76947 … 0x1000a10UL //Access:R DataWidth:0x1 // In-process Table almost …
76969 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
76970 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
76971 …th:0x5 // QM output initial credit (XCM TX queues). Max credit available - 16.Write writes the …
76972 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
76975 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
76976 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
76977 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
76978 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
76979 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
76993 …to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC …
77008 …tive counter overflow/uder-run. Is reset on read. [0] - If set, there was under-run; [1] - If set,…
77017 …taWidth:0x5 // Debug read from MSEM Input stage buffer: number of reads to next information uni…
77018 …taWidth:0x6 // Debug read from USEM Input stage buffer: number of reads to next information uni…
77019 …taWidth:0x5 // Debug read from XSEM Input stage buffer: number of reads to next information uni…
77020 …ataWidth:0x6 // Debug read from PBF Input stage buffer: number of reads to next information uni…
77021 …taWidth:0x6 // Debug read from DORQ Input stage buffer: number of reads to next information uni…
77022 …taWidth:0x6 // Debug read from USDM Input stage buffer: number of reads to next information uni…
77023 …taWidth:0x6 // Debug read from XSDM Input stage buffer: number of reads to next information uni…
77024 …taWidth:0x6 // Debug read from YSDM Input stage buffer: number of reads to next information uni…
77025 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
77028 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
77030 …ess:R DataWidth:0x20 // Debug read from XSEM Input stage buffer with 32-bits granularity. Rea…
77032 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
77034 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
77036 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
77038 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
77040 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
77042 … // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LC…
77043 …to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset wit…
77044 …to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LC…
77047 …0x1001900UL //Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX prote…
77050 …to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connect…
77053 …to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstS…
77079 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77080 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77081 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77082 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77083 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77084 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77085 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77086 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77087 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77088 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77089 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77090 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77091 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77092 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77093 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77094 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77095 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77096 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77097 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77098 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77099 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77100 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77101 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77102 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
77103 …4UL //Access:RW DataWidth:0x4 // Agggregation connection context size to be read/written back…
77104 …80UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77105 …8UL //Access:RW DataWidth:0x4 // Agggregation connection context size to be read/written back…
77106 …84UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77107 …cUL //Access:RW DataWidth:0x4 // Agggregation connection context size to be read/written back…
77108 …88UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77109 …0UL //Access:RW DataWidth:0x4 // Agggregation connection context size to be read/written back…
77110 …8cUL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77111 …4UL //Access:RW DataWidth:0x4 // Agggregation connection context size to be read/written back…
77112 …90UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77113 …8UL //Access:RW DataWidth:0x4 // Agggregation connection context size to be read/written back…
77114 …94UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77115 …cUL //Access:RW DataWidth:0x4 // Agggregation connection context size to be read/written back…
77116 …98UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77117 …0UL //Access:RW DataWidth:0x4 // Agggregation connection context size to be read/written back…
77118 …9cUL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77119 …a0UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77120 …a4UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77121 …a8UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77122 …acUL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77123 …b0UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77124 …b4UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77125 …b8UL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77126 …bcUL //Access:RW DataWidth:0x4 // Aggregation connection context size to be read/written back…
77247 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77248 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77249 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77250 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77251 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77252 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77253 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77254 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77255 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77256 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77257 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77258 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77259 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77260 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77261 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77262 … Enables QIndex 2 and 0 merge in XCM per connection type. If 0 - use queue index 0, if 1 - use que…
77265 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
77266 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
77271 …taWidth:0x6 // Debug read from MSDM Input stage buffer: number of reads to next information uni…
77272 …taWidth:0x6 // Debug read from MSDM Input stage buffer: number of reads to next information uni…
77273 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
77281 …taWidth:0x6 // Debug read from YSEM Input stage buffer: number of reads to next information uni…
77282 …taWidth:0x6 // Debug read from YSEM Input stage buffer: number of reads to next information uni…
77283 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77284 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
77286 …cess:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanis…
77288 …to implement a QM active state counter update: [19:0]: PQ counter update value. [28:20] PQ number.…
77291 …alises specific states and statuses. To initialise the state - write 1 into register; to enable wo…
77292 … 0x1080040UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
77293 … line) in the selected line (before shift).for selecting a line to output
77333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77334 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77336 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77338 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
77340 … (0x1<<0) // Signals an unknown address to the rf module.
77342 … (0x1<<1) // Write to full STORM input buf…
77346 … (0x1<<3) // Write to full MSDM input buff…
77350 … (0x1<<5) // Write to full YSDM input buff…
77354 … (0x1<<7) // Write to full XYLD input buff…
77358 … (0x1<<9) // Write to full Msem input buff…
77362 … (0x1<<11) // Write to full Usem input buff…
77368 … (0x1<<14) // Write to fully External read …
77402 … (0x1<<0) // Signals an unknown address to the rf module.
77404 … (0x1<<1) // Write to full STORM input buf…
77408 … (0x1<<3) // Write to full MSDM input buff…
77412 … (0x1<<5) // Write to full YSDM input buff…
77416 … (0x1<<7) // Write to full XYLD input buff…
77420 … (0x1<<9) // Write to full Msem input buff…
77424 … (0x1<<11) // Write to full Usem input buff…
77430 … (0x1<<14) // Write to fully External read …
77433 … (0x1<<0) // Signals an unknown address to the rf module.
77435 … (0x1<<1) // Write to full STORM input buf…
77439 … (0x1<<3) // Write to full MSDM input buff…
77443 … (0x1<<5) // Write to full YSDM input buff…
77447 … (0x1<<7) // Write to full XYLD input buff…
77451 … (0x1<<9) // Write to full Msem input buff…
77455 … (0x1<<11) // Write to full Usem input buff…
77461 … (0x1<<14) // Write to fully External read …
77464 … (0x1<<0) // Write to full Pbf input buffe…
77468 … (0x1<<2) // Write to full QM input buffer.
77472 … (0x1<<4) // Write to full QM input buffer.
77476 … (0x1<<6) // Write to full GRC input buffe…
77480 … (0x1<<8) // Write to full GRC input buffe…
77484 … (0x1<<10) // Write to full GRC input buffe…
77488 … (0x1<<12) // Write to full GRC input buffe…
77492 … (0x1<<14) // In-process Table overflo…
77558 … (0x1<<0) // Write to full Pbf input buffe…
77562 … (0x1<<2) // Write to full QM input buffer.
77566 … (0x1<<4) // Write to full QM input buffer.
77570 … (0x1<<6) // Write to full GRC input buffe…
77574 … (0x1<<8) // Write to full GRC input buffe…
77578 … (0x1<<10) // Write to full GRC input buffe…
77582 … (0x1<<12) // Write to full GRC input buffe…
77586 … (0x1<<14) // In-process Table overflo…
77605 … (0x1<<0) // Write to full Pbf input buffe…
77609 … (0x1<<2) // Write to full QM input buffer.
77613 … (0x1<<4) // Write to full QM input buffer.
77617 … (0x1<<6) // Write to full GRC input buffe…
77621 … (0x1<<8) // Write to full GRC input buffe…
77625 … (0x1<<10) // Write to full GRC input buffe…
77629 … (0x1<<12) // Write to full GRC input buffe…
77633 … (0x1<<14) // In-process Table overflo…
77867 …0220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
77868 …0224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
77869 …0228UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
78022 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
78072 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78073 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78074 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78075 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78076 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78077 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78078 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78079 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78080 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78081 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78091 … to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
78092 … to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
78093 … to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
78094 … to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
78095 … to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
78096 … to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
78097 …to perform non-usual arbitration operation relative to usual once in a while. Two values have spec…
78098 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78099 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78100 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78101 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78102 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78103 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78104 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
78105 … 0x1080664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
78107 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78108 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
78116 …he size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by …
78118 … 0x1080710UL //Access:R DataWidth:0x7 // Used to read the XX protecti…
78119 … 0x1080714UL //Access:R DataWidth:0x7 // Used to read XX protection L…
78120 …L //Access:RC DataWidth:0x7 // CAM occupancy sticky status. The write to the register is perf…
78121 …:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1-…
78122 …:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1-…
78123 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
78125 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
78130 …// Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt g…
78131 …// Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt g…
78132 …// Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt g…
78133 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
78142 …r of locked messages per LCID is above this threshold is one of conditions to start XxBypass for t…
78146 … //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't …
78150 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78151 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78152 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78153 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78154 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78155 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78156 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78157 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78158 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78159 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78160 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78161 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78162 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78163 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78164 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78165 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78166 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78167 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78168 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78169 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78170 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78171 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78172 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78173 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
78178 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78179 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78180 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78181 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78182 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78183 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78184 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78185 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78205 …x10808c0UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
78206 …x10808c4UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
78207 …x10808c8UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
78208 …x10808ccUL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
78209 …x10808d0UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
78210 …x10808d4UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
78211 …x10808d8UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
78212 …x10808dcUL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
78213 …to 320 LCIDs. Maximum context size per LCID is 12. Maximum number of LCIDs allowed at maximum cont…
78214 …to 320 LTIDs. Maximum context size per LTID is 20. Maximum number of LTIDs allowed at maximum cont…
78219 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78220 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78221 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78222 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78223 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78224 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78225 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78226 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78227 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78228 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78229 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78230 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78231 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78232 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78233 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78242 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
78243 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
78244 … 0x1080a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
78245 … 0x1080a10UL //Access:R DataWidth:0x1 // In-process Table almost …
78269 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
78270 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
78271 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
78272 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
78273 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
78276 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
78277 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
78278 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
78289 …to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC …
78307 …taWidth:0x6 // Debug read from MSEM Input stage buffer: number of reads to next information uni…
78308 …taWidth:0x6 // Debug read from USEM Input stage buffer: number of reads to next information uni…
78309 …ataWidth:0x6 // Debug read from PBF Input stage buffer: number of reads to next information uni…
78310 …taWidth:0x6 // Debug read from YSDM Input stage buffer: number of reads to next information uni…
78311 …taWidth:0x5 // Debug read from XYLD Input stage buffer: number of reads to next information uni…
78312 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
78314 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
78316 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
78318 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
78320 … // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LC…
78321 …to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset wit…
78322 …to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LT…
78323 …to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LC…
78324 …to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID nee…
78330 …0x1081a00UL //Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX prote…
78333 …to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connect…
78336 …to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstS…
78338 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78339 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78340 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78341 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78342 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78343 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78344 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78345 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78346 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78347 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78348 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78349 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78350 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78351 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78352 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78353 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78354 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78355 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78356 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78357 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78358 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78359 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78360 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78361 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
78362 …0UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
78363 …40UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78364 …4UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
78365 …44UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78366 …8UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
78367 …48UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78368 …cUL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
78369 …4cUL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78370 …0UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
78371 …50UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78372 …4UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
78373 …54UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78374 …8UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
78375 …58UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78376 …cUL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
78377 …5cUL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78378 …60UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78379 …64UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78380 …68UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78381 …6cUL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78382 …70UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78383 …74UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78384 …78UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78385 …7cUL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
78508 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
78509 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
78514 …taWidth:0x6 // Debug read from MSDM Input stage buffer: number of reads to next information uni…
78515 …taWidth:0x6 // Debug read from MSDM Input stage buffer: number of reads to next information uni…
78516 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78517 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
78519 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78520 …ess:R DataWidth:0x20 // Debug read from XYLD Input stage buffer with 32-bits granularity. Rea…
78523 …taWidth:0x6 // Debug read from YSEM Input stage buffer: number of reads to next information uni…
78524 …taWidth:0x5 // Debug read from YSEM Input stage buffer: number of reads to next information uni…
78525 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78526 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
78529 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
78535 …cess:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanis…
78536 …cess:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanis…
78539 …alises specific states and statuses. To initialise the state - write 1 into register; to enable wo…
78540 … 0x1100040UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
78541 … line) in the selected line (before shift).for selecting a line to output
78550 … (0x1<<0) // Signals an unknown address to the rf module.
78552 … (0x1<<1) // Write to full STORM input buf…
78556 … (0x1<<3) // Write to full PSDM input buff…
78562 … (0x1<<6) // Write to fully External read …
78564 … (0x1<<7) // Write to full YPLD input buff…
78588 … (0x1<<0) // Signals an unknown address to the rf module.
78590 … (0x1<<1) // Write to full STORM input buf…
78594 … (0x1<<3) // Write to full PSDM input buff…
78600 … (0x1<<6) // Write to fully External read …
78602 … (0x1<<7) // Write to full YPLD input buff…
78607 … (0x1<<0) // Signals an unknown address to the rf module.
78609 … (0x1<<1) // Write to full STORM input buf…
78613 … (0x1<<3) // Write to full PSDM input buff…
78619 … (0x1<<6) // Write to fully External read …
78621 … (0x1<<7) // Write to full YPLD input buff…
78626 … (0x1<<2) // Write to full GRC input buffe…
78628 … (0x1<<0) // Write to full GRC input buffe…
78634 … (0x1<<4) // Write to full GRC input buffe…
78636 … (0x1<<2) // Write to full GRC input buffe…
78642 … (0x1<<6) // Write to full GRC input buffe…
78644 … (0x1<<4) // Write to full GRC input buffe…
78650 … (0x1<<8) // Write to full GRC input buffe…
78652 … (0x1<<6) // Write to full GRC input buffe…
78658 …K2 (0x1<<10) // In-process Table overflo…
78660 … (0x1<<8) // In-process Table overflo…
78674 … (0x1<<0) // Write to full Pbf input buffe…
78732 …2 (0x1<<2) // Write to full GRC input buffe…
78734 … (0x1<<0) // Write to full GRC input buffe…
78740 …2 (0x1<<4) // Write to full GRC input buffe…
78742 … (0x1<<2) // Write to full GRC input buffe…
78748 …2 (0x1<<6) // Write to full GRC input buffe…
78750 … (0x1<<4) // Write to full GRC input buffe…
78756 …2 (0x1<<8) // Write to full GRC input buffe…
78758 … (0x1<<6) // Write to full GRC input buffe…
78764 …BB_K2 (0x1<<10) // In-process Table overflo…
78766 …_E5 (0x1<<8) // In-process Table overflo…
78780 … (0x1<<0) // Write to full Pbf input buffe…
78785 …K2 (0x1<<2) // Write to full GRC input buffe…
78787 … (0x1<<0) // Write to full GRC input buffe…
78793 …K2 (0x1<<4) // Write to full GRC input buffe…
78795 … (0x1<<2) // Write to full GRC input buffe…
78801 …K2 (0x1<<6) // Write to full GRC input buffe…
78803 … (0x1<<4) // Write to full GRC input buffe…
78809 …K2 (0x1<<8) // Write to full GRC input buffe…
78811 … (0x1<<6) // Write to full GRC input buffe…
78817 …_BB_K2 (0x1<<10) // In-process Table overflo…
78819 …L_E5 (0x1<<8) // In-process Table overflo…
78833 …2 (0x1<<0) // Write to full Pbf input buffe…
78934 …0210UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
78935 …0210UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
78936 …0210UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
78937 …0214UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
78938 …0214UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
78939 …0214UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
78998 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
79003 … to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
79004 … to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
79005 … to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
79006 … to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
79007 … to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
79008 … to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
79009 …to perform non-usual arbitration operation relative to usual once in a while. Two values have spec…
79010 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79011 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79012 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
79013 … 0x110063cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
79015 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
79020 …he size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by …
79022 … 0x1100710UL //Access:R DataWidth:0x3 // Used to read the XX protecti…
79023 … 0x1100714UL //Access:R DataWidth:0x2 // Used to read XX protection L…
79024 …L //Access:RC DataWidth:0x2 // CAM occupancy sticky status. The write to the register is perf…
79025 …:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1-…
79026 …:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1-…
79027 … DataWidth:0x2 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
79029 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
79034 …// Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt g…
79035 …// Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt g…
79036 …// Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt g…
79037 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
79042 … //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't …
79052 …to 320 LCIDs. Maximum context size per LCID is 20. Maximum number of LCIDs allowed at maximum cont…
79053 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
79054 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
79055 … 0x1100a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
79056 … 0x1100a10UL //Access:R DataWidth:0x1 // In-process Table almost …
79060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
79063 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
79068 …to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC …
79074 …taWidth:0x5 // Debug read from PSEM Input stage buffer: number of reads to next information uni…
79075 …ataWidth:0x6 // Debug read from PBF Input stage buffer: number of reads to next information uni…
79076 …ess:R DataWidth:0x20 // Debug read from PSEM Input stage buffer with 32-bits granularity. Rea…
79079 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
79081 … // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LC…
79082 …to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LC…
79083 …0x1101500UL //Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX prote…
79085 …to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connect…
79087 …to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstS…
79089 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79090 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79091 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79092 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79093 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79094 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79095 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79096 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79097 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79098 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79099 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79100 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79101 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79102 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79103 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79104 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79105 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79106 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79107 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79108 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79109 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79110 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79111 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79112 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
79115 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
79116 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
79121 …taWidth:0x6 // Debug read from PSDM Input stage buffer: number of reads to next information uni…
79122 …taWidth:0x6 // Debug read from PSDM Input stage buffer: number of reads to next information uni…
79123 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79124 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
79127 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
79130 …taWidth:0x5 // Debug read from YPLD Input stage buffer: number of reads to next information uni…
79131 …ess:R DataWidth:0x20 // Debug read from YPLD Input stage buffer with 32-bits granularity. Rea…
79133 …cess:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanis…
79135 …alises specific states and statuses. To initialise the state - write 1 into register; to enable wo…
79136 … 0x1180040UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
79137 … line) in the selected line (before shift).for selecting a line to output
79177 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79178 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79179 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79186 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79187 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79188 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79189 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79190 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79191 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79192 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79193 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79194 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79195 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79196 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79197 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79198 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79199 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
79201 … (0x1<<0) // Signals an unknown address to the rf module.
79203 … (0x1<<1) // Write to full STORM input buf…
79207 … (0x1<<3) // Write to full MSDM input buff…
79211 … (0x1<<3) // Write to full TSDM input buff…
79213 … (0x1<<5) // Write to full TSDM input buff…
79219 … (0x1<<7) // Write to full PSDM input buff…
79223 … (0x1<<5) // Write to full Msem input buff…
79225 … (0x1<<9) // Write to full Msem input buff…
79231 … (0x1<<7) // Write to full Ysem input buff…
79233 … (0x1<<11) // Write to full Ysem input buff…
79237 … (0x1<<13) // Write to fully External read …
79279 … (0x1<<0) // Signals an unknown address to the rf module.
79281 … (0x1<<1) // Write to full STORM input buf…
79285 … (0x1<<3) // Write to full MSDM input buff…
79289 …2 (0x1<<3) // Write to full TSDM input buff…
79291 … (0x1<<5) // Write to full TSDM input buff…
79297 … (0x1<<7) // Write to full PSDM input buff…
79301 …2 (0x1<<5) // Write to full Msem input buff…
79303 … (0x1<<9) // Write to full Msem input buff…
79309 …2 (0x1<<7) // Write to full Ysem input buff…
79311 … (0x1<<11) // Write to full Ysem input buff…
79315 … (0x1<<13) // Write to fully External read …
79318 … (0x1<<0) // Signals an unknown address to the rf module.
79320 … (0x1<<1) // Write to full STORM input buf…
79324 … (0x1<<3) // Write to full MSDM input buff…
79328 …K2 (0x1<<3) // Write to full TSDM input buff…
79330 … (0x1<<5) // Write to full TSDM input buff…
79336 … (0x1<<7) // Write to full PSDM input buff…
79340 …K2 (0x1<<5) // Write to full Msem input buff…
79342 … (0x1<<9) // Write to full Msem input buff…
79348 …K2 (0x1<<7) // Write to full Ysem input buff…
79350 … (0x1<<11) // Write to full Ysem input buff…
79354 … (0x1<<13) // Write to fully External read …
79359 … (0x1<<1) // Write to full Dorq input buff…
79363 … (0x1<<3) // Write to full Pbf input buffe…
79367 … (0x1<<5) // Write to full PTLD input buff…
79371 … (0x1<<7) // Write to full TM input buffer.
79375 … (0x1<<9) // Write to full QM input buffer.
79379 … (0x1<<11) // Write to full QM input buffer.
79383 … (0x1<<13) // Write to full GRC input buffe…
79387 … (0x1<<15) // Write to full GRC input buffe…
79391 … (0x1<<17) // Write to full GRC input buffe…
79395 … (0x1<<19) // Write to full GRC input buffe…
79399 … (0x1<<21) // In-process Table overflo…
79421 … (0x1<<5) // Write to full Pbf input buffe…
79497 … (0x1<<1) // Write to full Dorq input buff…
79501 … (0x1<<3) // Write to full Pbf input buffe…
79505 … (0x1<<5) // Write to full PTLD input buff…
79509 … (0x1<<7) // Write to full TM input buffer.
79513 … (0x1<<9) // Write to full QM input buffer.
79517 … (0x1<<11) // Write to full QM input buffer.
79521 … (0x1<<13) // Write to full GRC input buffe…
79525 … (0x1<<15) // Write to full GRC input buffe…
79529 … (0x1<<17) // Write to full GRC input buffe…
79533 … (0x1<<19) // Write to full GRC input buffe…
79537 … (0x1<<21) // In-process Table overflo…
79559 … (0x1<<5) // Write to full Pbf input buffe…
79566 … (0x1<<1) // Write to full Dorq input buff…
79570 … (0x1<<3) // Write to full Pbf input buffe…
79574 … (0x1<<5) // Write to full PTLD input buff…
79578 … (0x1<<7) // Write to full TM input buffer.
79582 … (0x1<<9) // Write to full QM input buffer.
79586 … (0x1<<11) // Write to full QM input buffer.
79590 … (0x1<<13) // Write to full GRC input buffe…
79594 … (0x1<<15) // Write to full GRC input buffe…
79598 … (0x1<<17) // Write to full GRC input buffe…
79602 … (0x1<<19) // Write to full GRC input buffe…
79606 … (0x1<<21) // In-process Table overflo…
79628 …2 (0x1<<5) // Write to full Pbf input buffe…
79982 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
80024 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80025 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80026 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80027 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80028 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80029 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80030 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80031 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80032 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80033 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80034 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80035 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80036 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80037 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80038 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80039 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80040 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80041 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80042 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80043 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80053 … to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
80054 … to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
80055 … to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
80056 … to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
80057 … to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
80058 … to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
80059 …to perform non-usual arbitration operation relative to usual once in a while. Two values have spec…
80060 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80061 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80062 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80063 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80064 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80065 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
80066 … 0x1180664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
80068 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80069 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
80077 …he size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by …
80079 … 0x1180710UL //Access:R DataWidth:0x7 // Used to read the XX protecti…
80080 … 0x1180714UL //Access:R DataWidth:0x7 // Used to read XX protection L…
80081 …L //Access:RC DataWidth:0x7 // CAM occupancy sticky status. The write to the register is perf…
80082 …:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1-…
80083 …:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1-…
80084 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
80086 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
80091 …// Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt g…
80092 …// Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt g…
80093 …// Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt g…
80094 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
80103 …r of locked messages per LCID is above this threshold is one of conditions to start XxBypass for t…
80107 … //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't …
80111 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80112 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80113 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80114 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80115 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80116 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80117 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80118 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80119 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80120 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80121 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80122 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80123 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80124 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80125 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80126 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80127 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80128 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80129 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80130 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80131 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80132 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80133 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80134 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
80139 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80140 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80141 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80142 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80143 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80144 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80145 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80146 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80166 …x11808c0UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
80167 …x11808c4UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
80168 …x11808c8UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
80169 …x11808ccUL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
80170 …x11808d0UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
80171 …x11808d4UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
80172 …x11808d8UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
80173 …x11808dcUL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
80174 …to 320 LCIDs. Maximum context size per LCID is 26. Maximum number of LCIDs allowed at maximum cont…
80175 …to 320 LTIDs. Maximum context size per LTID is 12. Maximum number of LTIDs allowed at maximum cont…
80180 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80181 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80182 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80183 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80184 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80185 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80194 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
80195 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
80196 … 0x1180a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
80197 … 0x1180a10UL //Access:R DataWidth:0x1 // In-process Table almost …
80223 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
80224 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
80225 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
80226 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
80229 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
80230 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
80231 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
80242 …to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC …
80259 …taWidth:0x5 // Debug read from TSEM Input stage buffer: number of reads to next information uni…
80260 …taWidth:0x6 // Debug read from MSEM Input stage buffer: number of reads to next information uni…
80261 …ataWidth:0x6 // Debug read from PRS Input stage buffer: number of reads to next information uni…
80262 …ataWidth:0x6 // Debug read from PBF Input stage buffer: number of reads to next information uni…
80263 …taWidth:0x6 // Debug read from DORQ Input stage buffer: number of reads to next information uni…
80264 …ess:R DataWidth:0x20 // Debug read from TSEM Input stage buffer with 32-bits granularity. Rea…
80267 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
80269 …cess:R DataWidth:0x20 // Debug read from PRS Input stage buffer with 32-bits granularity. Rea…
80271 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
80273 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
80275 … // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LC…
80276 …to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset wit…
80277 …to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LT…
80278 …to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LC…
80279 …to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID nee…
80285 …0x1181600UL //Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX prote…
80288 …to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connect…
80291 …to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstS…
80317 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80318 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80319 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80320 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80321 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80322 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80323 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80324 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80325 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80326 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80327 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80328 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80329 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80330 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80331 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80332 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80333 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80334 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80335 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80336 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80337 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80338 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80339 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80340 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
80341 …0UL //Access:RW DataWidth:0x3 // Agggregation connection context size to be read/written back…
80342 …80UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80343 …4UL //Access:RW DataWidth:0x3 // Agggregation connection context size to be read/written back…
80344 …84UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80345 …8UL //Access:RW DataWidth:0x3 // Agggregation connection context size to be read/written back…
80346 …88UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80347 …cUL //Access:RW DataWidth:0x3 // Agggregation connection context size to be read/written back…
80348 …8cUL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80349 …0UL //Access:RW DataWidth:0x3 // Agggregation connection context size to be read/written back…
80350 …90UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80351 …4UL //Access:RW DataWidth:0x3 // Agggregation connection context size to be read/written back…
80352 …94UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80353 …8UL //Access:RW DataWidth:0x3 // Agggregation connection context size to be read/written back…
80354 …98UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80355 …cUL //Access:RW DataWidth:0x3 // Agggregation connection context size to be read/written back…
80356 …9cUL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80357 …a0UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80358 …a4UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80359 …a8UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80360 …acUL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80361 …b0UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80362 …b4UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80363 …b8UL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80364 …bcUL //Access:RW DataWidth:0x3 // Aggregation connection context size to be read/written back…
80487 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
80488 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
80493 …taWidth:0x6 // Debug read from TSDM Input stage buffer: number of reads to next information uni…
80494 …taWidth:0x6 // Debug read from TSDM Input stage buffer: number of reads to next information uni…
80495 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80496 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
80499 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
80502 …taWidth:0x6 // Debug read from PSDM Input stage buffer: number of reads to next information uni…
80503 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
80506 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
80509 …taWidth:0x6 // Debug read from MSDM Input stage buffer: number of reads to next information uni…
80510 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
80518 …taWidth:0x6 // Debug read from YSEM Input stage buffer: number of reads to next information uni…
80519 …taWidth:0x6 // Debug read from YSEM Input stage buffer: number of reads to next information uni…
80520 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80521 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
80524 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
80527 …taWidth:0x5 // Debug read from PTLD Input stage buffer: number of reads to next information uni…
80528 …ess:R DataWidth:0x20 // Debug read from PTLD Input stage buffer with 32-bits granularity. Rea…
80530 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80531 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80532 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80533 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80534 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80535 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80536 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80537 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80538 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80539 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80540 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80541 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80542 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80543 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80544 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80545 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80546 …cess:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanis…
80549 …alises specific states and statuses. To initialise the state - write 1 into register; to enable wo…
80550 … 0x1200040UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
80551 … line) in the selected line (before shift).for selecting a line to output
80591 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80592 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80593 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80594 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80595 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80596 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
80598 … (0x1<<0) // Signals an unknown address to the rf module.
80600 … (0x1<<1) // Write to full STORM input buf…
80604 … (0x1<<3) // Write to full MSDM input buff…
80608 … (0x1<<5) // Write to full YSDM input buff…
80612 … (0x1<<7) // Write to full TSDM input buff…
80616 … (0x1<<9) // Write to full PSDM input buff…
80620 … (0x1<<7) // Write to full USDM input buff…
80622 … (0x1<<11) // Write to full USDM input buff…
80628 … (0x1<<9) // Write to full TMLD input buff…
80630 … (0x1<<13) // Write to full TMLD input buff…
80636 … (0x1<<11) // Write to full Usem input buff…
80638 … (0x1<<15) // Write to full Usem input buff…
80644 … (0x1<<13) // Write to full Ysem input buff…
80646 … (0x1<<17) // Write to full Ysem input buff…
80650 … (0x1<<19) // Write to fully External read …
80708 … (0x1<<0) // Signals an unknown address to the rf module.
80710 … (0x1<<1) // Write to full STORM input buf…
80714 … (0x1<<3) // Write to full MSDM input buff…
80718 … (0x1<<5) // Write to full YSDM input buff…
80722 … (0x1<<7) // Write to full TSDM input buff…
80726 … (0x1<<9) // Write to full PSDM input buff…
80730 …2 (0x1<<7) // Write to full USDM input buff…
80732 … (0x1<<11) // Write to full USDM input buff…
80738 …2 (0x1<<9) // Write to full TMLD input buff…
80740 … (0x1<<13) // Write to full TMLD input buff…
80746 … (0x1<<11) // Write to full Usem input buff…
80748 … (0x1<<15) // Write to full Usem input buff…
80754 … (0x1<<13) // Write to full Ysem input buff…
80756 … (0x1<<17) // Write to full Ysem input buff…
80760 … (0x1<<19) // Write to fully External read …
80763 … (0x1<<0) // Signals an unknown address to the rf module.
80765 … (0x1<<1) // Write to full STORM input buf…
80769 … (0x1<<3) // Write to full MSDM input buff…
80773 … (0x1<<5) // Write to full YSDM input buff…
80777 … (0x1<<7) // Write to full TSDM input buff…
80781 … (0x1<<9) // Write to full PSDM input buff…
80785 …K2 (0x1<<7) // Write to full USDM input buff…
80787 … (0x1<<11) // Write to full USDM input buff…
80793 …K2 (0x1<<9) // Write to full TMLD input buff…
80795 … (0x1<<13) // Write to full TMLD input buff…
80801 …2 (0x1<<11) // Write to full Usem input buff…
80803 … (0x1<<15) // Write to full Usem input buff…
80809 …2 (0x1<<13) // Write to full Ysem input buff…
80811 … (0x1<<17) // Write to full Ysem input buff…
80815 … (0x1<<19) // Write to fully External read …
80820 … (0x1<<1) // Write to full Pbf input buffe…
80824 … (0x1<<3) // Write to full QM input buffer.
80828 … (0x1<<5) // Write to full QM input buffer.
80832 … (0x1<<7) // Write to full GRC input buffe…
80836 … (0x1<<9) // Write to full GRC input buffe…
80840 … (0x1<<11) // Write to full GRC input buffe…
80844 … (0x1<<13) // Write to full GRC input buffe…
80848 … (0x1<<15) // In-process Table overflo…
80926 … (0x1<<1) // Write to full Pbf input buffe…
80930 … (0x1<<3) // Write to full QM input buffer.
80934 … (0x1<<5) // Write to full QM input buffer.
80938 … (0x1<<7) // Write to full GRC input buffe…
80942 … (0x1<<9) // Write to full GRC input buffe…
80946 … (0x1<<11) // Write to full GRC input buffe…
80950 … (0x1<<13) // Write to full GRC input buffe…
80954 … (0x1<<15) // In-process Table overflo…
80979 … (0x1<<1) // Write to full Pbf input buffe…
80983 … (0x1<<3) // Write to full QM input buffer.
80987 … (0x1<<5) // Write to full QM input buffer.
80991 … (0x1<<7) // Write to full GRC input buffe…
80995 … (0x1<<9) // Write to full GRC input buffe…
80999 … (0x1<<11) // Write to full GRC input buffe…
81003 … (0x1<<13) // Write to full GRC input buffe…
81007 … (0x1<<15) // In-process Table overflo…
81185 …0220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
81186 …0220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
81187 …0224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
81188 …0224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
81283 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
81333 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81334 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81335 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81336 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81337 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81338 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81339 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81340 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81341 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81342 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81352 … to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
81353 … to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
81354 … to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
81355 … to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
81356 … to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
81357 … to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
81358 …to perform non-usual arbitration operation relative to usual once in a while. Two values have spec…
81359 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81360 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81361 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81362 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81363 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81364 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81365 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81366 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
81367 … 0x120066cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
81369 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81370 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
81378 …he size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by …
81380 … 0x1200710UL //Access:R DataWidth:0x7 // Used to read the XX protecti…
81381 … 0x1200714UL //Access:R DataWidth:0x7 // Used to read XX protection L…
81382 …L //Access:RC DataWidth:0x7 // CAM occupancy sticky status. The write to the register is perf…
81383 …:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1-…
81384 …:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1-…
81385 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
81387 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
81392 …// Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt g…
81393 …// Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt g…
81394 …// Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt g…
81395 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
81404 …r of locked messages per LCID is above this threshold is one of conditions to start XxBypass for t…
81408 … //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't …
81412 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81413 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81414 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81415 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81416 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81417 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81418 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81419 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81420 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81421 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81422 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81423 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81424 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81425 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81426 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81427 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81428 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81429 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81430 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81431 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81432 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81433 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81434 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81435 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
81440 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81441 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81442 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81443 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81444 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81445 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81446 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81447 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81467 …x12008c0UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
81468 …x12008c4UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
81469 …x12008c8UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
81470 …x12008ccUL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
81471 …x12008d0UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
81472 …x12008d4UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
81473 …x12008d8UL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
81474 …x12008dcUL //Access:RW DataWidth:0x2 // Aggregation task context size to be read/written back…
81475 …to 320 LCIDs. Maximum context size per LCID is 20. Maximum number of LCIDs allowed at maximum cont…
81476 …to 320 LTIDs. Maximum context size per LTID is 20. Maximum number of LTIDs allowed at maximum cont…
81481 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81482 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81483 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81484 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81485 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81486 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81487 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81488 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81497 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
81498 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
81499 … 0x1200a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
81500 … 0x1200a10UL //Access:R DataWidth:0x1 // In-process Table almost …
81524 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
81525 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
81526 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
81527 …1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the i…
81528 …th:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the i…
81531 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
81532 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
81533 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
81534 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
81545 …to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC …
81562 …taWidth:0x5 // Debug read from MSEM Input stage buffer: number of reads to next information uni…
81563 …taWidth:0x6 // Debug read from USEM Input stage buffer: number of reads to next information uni…
81564 …ataWidth:0x6 // Debug read from PBF Input stage buffer: number of reads to next information uni…
81565 …taWidth:0x6 // Debug read from USDM Input stage buffer: number of reads to next information uni…
81566 …taWidth:0x6 // Debug read from YSDM Input stage buffer: number of reads to next information uni…
81567 …taWidth:0x5 // Debug read from TMLD Input stage buffer: number of reads to next information uni…
81568 …ess:R DataWidth:0x20 // Debug read from MSEM Input stage buffer with 32-bits granularity. Rea…
81571 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
81573 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
81575 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
81577 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
81579 … // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LC…
81580 …to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset wit…
81581 …to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LT…
81582 …to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LC…
81583 …to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID nee…
81589 …0x1201a00UL //Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX prote…
81592 …to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connect…
81595 …to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstS…
81597 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81598 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81599 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81600 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81601 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81602 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81603 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81604 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81605 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81606 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81607 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81608 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81609 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81610 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81611 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81612 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81613 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81614 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81615 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81616 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81617 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81618 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81619 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81620 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
81621 …0UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back…
81622 …40UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81623 …4UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back…
81624 …44UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81625 …8UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back…
81626 …48UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81627 …cUL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back…
81628 …4cUL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81629 …0UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back…
81630 …50UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81631 …4UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back…
81632 …54UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81633 …8UL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back…
81634 …58UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81635 …cUL //Access:RW DataWidth:0x1 // Agggregation connection context size to be read/written back…
81636 …5cUL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81637 …60UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81638 …64UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81639 …68UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81640 …6cUL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81641 …70UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81642 …74UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81643 …78UL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81644 …7cUL //Access:RW DataWidth:0x1 // Aggregation connection context size to be read/written back…
81765 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81766 …ess:R DataWidth:0x20 // Debug read from TMLD Input stage buffer with 32-bits granularity. Rea…
81770 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
81773 …taWidth:0x6 // Debug read from TSDM Input stage buffer: number of reads to next information uni…
81774 …ess:R DataWidth:0x20 // Debug read from TSDM Input stage buffer with 32-bits granularity. Rea…
81777 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
81780 …taWidth:0x6 // Debug read from PSDM Input stage buffer: number of reads to next information uni…
81781 …ess:R DataWidth:0x20 // Debug read from PSDM Input stage buffer with 32-bits granularity. Rea…
81785 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
81786 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
81791 …taWidth:0x6 // Debug read from MSDM Input stage buffer: number of reads to next information uni…
81792 …taWidth:0x6 // Debug read from MSDM Input stage buffer: number of reads to next information uni…
81793 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81794 …ess:R DataWidth:0x20 // Debug read from MSDM Input stage buffer with 32-bits granularity. Rea…
81802 …taWidth:0x6 // Debug read from YSEM Input stage buffer: number of reads to next information uni…
81803 …taWidth:0x5 // Debug read from YSEM Input stage buffer: number of reads to next information uni…
81804 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81805 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
81808 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81809 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81810 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81811 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81812 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81813 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81814 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81815 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81816 …cess:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanis…
81817 …cess:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanis…
81820 …alises specific states and statuses. To initialise the state - write 1 into register; to enable wo…
81821 … 0x1280040UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST
81822 … 0x1280044UL //Access:RW DataWidth:0x8 // command to CPU BIST
81823 … 0x1280048UL //Access:RW DataWidth:0x8 // address to CPU BIST
81825 … 0x1280050UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
81826 … line) in the selected line (before shift).for selecting a line to output
81866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81867 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81868 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81869 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81870 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81871 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81872 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81873 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81874 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81875 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81876 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81877 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81878 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81879 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81880 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81881 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
81883 … (0x1<<0) // Signals an unknown address to the rf module.
81885 … (0x1<<1) // Write to full STORM input buf…
81889 … (0x1<<3) // Write to full XSDM input buff…
81893 … (0x1<<5) // Write to full YSDM input buff…
81897 … (0x1<<7) // Write to full USDM input buff…
81901 … (0x1<<9) // Write to full RDIF input buff…
81905 … (0x1<<11) // Write to full TDIF input buff…
81909 … (0x1<<13) // Write to full MULD input buff…
81913 … (0x1<<15) // Write to full Ysem input buff…
81917 … (0x1<<17) // Write to fully External read …
81919 … (0x1<<15) // Write to full YULD input buff…
81965 … (0x1<<0) // Signals an unknown address to the rf module.
81967 … (0x1<<1) // Write to full STORM input buf…
81971 … (0x1<<3) // Write to full XSDM input buff…
81975 … (0x1<<5) // Write to full YSDM input buff…
81979 … (0x1<<7) // Write to full USDM input buff…
81983 … (0x1<<9) // Write to full RDIF input buff…
81987 … (0x1<<11) // Write to full TDIF input buff…
81991 … (0x1<<13) // Write to full MULD input buff…
81995 … (0x1<<15) // Write to full Ysem input buff…
81999 … (0x1<<17) // Write to fully External read …
82001 … (0x1<<15) // Write to full YULD input buff…
82006 … (0x1<<0) // Signals an unknown address to the rf module.
82008 … (0x1<<1) // Write to full STORM input buf…
82012 … (0x1<<3) // Write to full XSDM input buff…
82016 … (0x1<<5) // Write to full YSDM input buff…
82020 … (0x1<<7) // Write to full USDM input buff…
82024 … (0x1<<9) // Write to full RDIF input buff…
82028 … (0x1<<11) // Write to full TDIF input buff…
82032 … (0x1<<13) // Write to full MULD input buff…
82036 … (0x1<<15) // Write to full Ysem input buff…
82040 … (0x1<<17) // Write to fully External read …
82042 …2 (0x1<<15) // Write to full YULD input buff…
82049 … (0x1<<0) // Write to full Dorq input buff…
82051 … (0x1<<1) // Write to full Dorq input buff…
82057 … (0x1<<2) // Write to full Pbf input buffe…
82059 … (0x1<<3) // Write to full Pbf input buffe…
82065 … (0x1<<4) // Write to full TM input buffer.
82067 … (0x1<<5) // Write to full TM input buffer.
82073 … (0x1<<6) // Write to full QM input buffer.
82075 … (0x1<<7) // Write to full QM input buffer.
82081 … (0x1<<8) // Write to full QM input buffer.
82083 … (0x1<<9) // Write to full QM input buffer.
82089 … (0x1<<10) // Write to full GRC input buffe…
82091 … (0x1<<11) // Write to full GRC input buffe…
82097 … (0x1<<12) // Write to full GRC input buffe…
82099 … (0x1<<13) // Write to full GRC input buffe…
82105 … (0x1<<14) // Write to full GRC input buffe…
82107 … (0x1<<15) // Write to full GRC input buffe…
82113 … (0x1<<16) // Write to full GRC input buffe…
82115 … (0x1<<17) // Write to full GRC input buffe…
82121 …K2 (0x1<<18) // In-process Table overflo…
82123 … (0x1<<19) // In-process Table overflo…
82287 …2 (0x1<<0) // Write to full Dorq input buff…
82289 … (0x1<<1) // Write to full Dorq input buff…
82295 … (0x1<<2) // Write to full Pbf input buffe…
82297 … (0x1<<3) // Write to full Pbf input buffe…
82303 … (0x1<<4) // Write to full TM input buffer.
82305 … (0x1<<5) // Write to full TM input buffer.
82311 …2 (0x1<<6) // Write to full QM input buffer.
82313 … (0x1<<7) // Write to full QM input buffer.
82319 …2 (0x1<<8) // Write to full QM input buffer.
82321 … (0x1<<9) // Write to full QM input buffer.
82327 … (0x1<<10) // Write to full GRC input buffe…
82329 … (0x1<<11) // Write to full GRC input buffe…
82335 … (0x1<<12) // Write to full GRC input buffe…
82337 … (0x1<<13) // Write to full GRC input buffe…
82343 … (0x1<<14) // Write to full GRC input buffe…
82345 … (0x1<<15) // Write to full GRC input buffe…
82351 … (0x1<<16) // Write to full GRC input buffe…
82353 … (0x1<<17) // Write to full GRC input buffe…
82359 …BB_K2 (0x1<<18) // In-process Table overflo…
82361 …E5 (0x1<<19) // In-process Table overflo…
82406 …K2 (0x1<<0) // Write to full Dorq input buff…
82408 … (0x1<<1) // Write to full Dorq input buff…
82414 …2 (0x1<<2) // Write to full Pbf input buffe…
82416 … (0x1<<3) // Write to full Pbf input buffe…
82422 … (0x1<<4) // Write to full TM input buffer.
82424 … (0x1<<5) // Write to full TM input buffer.
82430 …K2 (0x1<<6) // Write to full QM input buffer.
82432 … (0x1<<7) // Write to full QM input buffer.
82438 …K2 (0x1<<8) // Write to full QM input buffer.
82440 … (0x1<<9) // Write to full QM input buffer.
82446 …2 (0x1<<10) // Write to full GRC input buffe…
82448 … (0x1<<11) // Write to full GRC input buffe…
82454 …2 (0x1<<12) // Write to full GRC input buffe…
82456 … (0x1<<13) // Write to full GRC input buffe…
82462 …2 (0x1<<14) // Write to full GRC input buffe…
82464 … (0x1<<15) // Write to full GRC input buffe…
82470 …2 (0x1<<16) // Write to full GRC input buffe…
82472 … (0x1<<17) // Write to full GRC input buffe…
82478 …_BB_K2 (0x1<<18) // In-process Table overflo…
82480 …_E5 (0x1<<19) // In-process Table overflo…
82680 …0220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
82681 …0220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
82682 …0224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
82683 …0224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next wri…
82808 …Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other sign…
82850 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82851 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82852 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82853 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82854 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82855 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82856 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82857 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82858 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82859 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82860 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82861 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82862 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82863 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82864 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82865 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82866 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82867 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
82882 … to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
82883 … to group priority 1. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
82884 … to group priority 2. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
82885 … to group priority 3. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
82886 … to group priority 4. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
82887 … to group priority 5. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - …
82888 …to perform non-usual arbitration operation relative to usual once in a while. Two values have spec…
82889 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82890 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82891 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82892 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82893 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82894 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82895 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82896 …4UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82897 …8UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82898 …cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82899 …0UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward.
82900 … 0x1280684UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 -…
82902 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82903 …- Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg…
82911 …he size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by …
82913 … 0x1280710UL //Access:R DataWidth:0x7 // Used to read the XX protecti…
82914 … 0x1280714UL //Access:R DataWidth:0x7 // Used to read XX protection L…
82915 …L //Access:RC DataWidth:0x7 // CAM occupancy sticky status. The write to the register is perf…
82916 …:0x1 // Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1-…
82917 …:0x1 // Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1-…
82918 … DataWidth:0x7 // Xx non-locked LCIDs threshold (maximum value). Participates in blocking decis…
82920 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
82925 …// Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt g…
82926 …// Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt g…
82927 …// Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt g…
82928 …to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usua…
82937 …r of locked messages per LCID is above this threshold is one of conditions to start XxBypass for t…
82941 … //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't …
82945 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82946 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82947 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82948 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82949 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82950 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82951 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82952 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82953 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82954 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82955 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82956 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82957 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82958 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82959 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82960 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82961 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82962 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82963 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82964 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82965 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82966 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82967 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82968 …W DataWidth:0x5 // Xx Bypass messages upper bound (per connection) - used to restrict number …
82973 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
82974 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
82975 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
82976 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
82977 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
82978 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
82979 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
82980 …Width:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83000 …x12808c0UL //Access:RW DataWidth:0x3 // Aggregation task context size to be read/written back…
83001 …x12808c4UL //Access:RW DataWidth:0x3 // Aggregation task context size to be read/written back…
83002 …x12808c8UL //Access:RW DataWidth:0x3 // Aggregation task context size to be read/written back…
83003 …x12808ccUL //Access:RW DataWidth:0x3 // Aggregation task context size to be read/written back…
83004 …x12808d0UL //Access:RW DataWidth:0x3 // Aggregation task context size to be read/written back…
83005 …x12808d4UL //Access:RW DataWidth:0x3 // Aggregation task context size to be read/written back…
83006 …x12808d8UL //Access:RW DataWidth:0x3 // Aggregation task context size to be read/written back…
83007 …x12808dcUL //Access:RW DataWidth:0x3 // Aggregation task context size to be read/written back…
83008 …to 320 LCIDs. Maximum context size per LCID is 24. Maximum number of LCIDs allowed at maximum cont…
83009 …to 320 LTIDs. Maximum context size per LTID is 12. Maximum number of LTIDs allowed at maximum cont…
83014 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83015 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83016 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83017 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83018 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83019 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83020 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83021 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83022 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83031 … // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.…
83032 … // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_A…
83033 … 0x1280a0cUL //Access:R DataWidth:0x4 // In-process Table fill le…
83034 … 0x1280a10UL //Access:R DataWidth:0x1 // In-process Table almost …
83060 …s:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the …
83061 …s:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the …
83062 … QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 1…
83063 …RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the …
83066 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
83067 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
83068 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
83069 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
83070 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
83071 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
83072 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
83073 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
83074 …//Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at …
83090 …to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC …
83114 …taWidth:0x5 // Debug read from USEM Input stage buffer: number of reads to next information uni…
83115 …ataWidth:0x6 // Debug read from PBF Input stage buffer: number of reads to next information uni…
83116 …taWidth:0x6 // Debug read from DORQ Input stage buffer: number of reads to next information uni…
83117 …taWidth:0x6 // Debug read from RDIF Input stage buffer: number of reads to next information uni…
83118 …taWidth:0x6 // Debug read from TDIF Input stage buffer: number of reads to next information uni…
83119 …taWidth:0x6 // Debug read from USDM Input stage buffer: number of reads to next information uni…
83120 …taWidth:0x6 // Debug read from XSDM Input stage buffer: number of reads to next information uni…
83121 …taWidth:0x6 // Debug read from YSDM Input stage buffer: number of reads to next information uni…
83122 …taWidth:0x5 // Debug read from MULD Input stage buffer: number of reads to next information uni…
83123 …taWidth:0x6 // Debug read from YULD Input stage buffer: number of reads to next information uni…
83124 …ess:R DataWidth:0x20 // Debug read from USEM Input stage buffer with 32-bits granularity. Rea…
83127 …cess:R DataWidth:0x20 // Debug read from PBF Input stage buffer with 32-bits granularity. Rea…
83129 …ess:R DataWidth:0x20 // Debug read from DORQ Input stage buffer with 32-bits granularity. Rea…
83131 …ess:R DataWidth:0x20 // Debug read from RDIF Input stage buffer with 32-bits granularity. Rea…
83133 …ess:R DataWidth:0x20 // Debug read from TDIF Input stage buffer with 32-bits granularity. Rea…
83135 …ess:R DataWidth:0x20 // Debug read from USDM Input stage buffer with 32-bits granularity. Rea…
83137 …ess:R DataWidth:0x20 // Debug read from XSDM Input stage buffer with 32-bits granularity. Rea…
83139 …ess:R DataWidth:0x20 // Debug read from YSDM Input stage buffer with 32-bits granularity. Rea…
83141 …ess:R DataWidth:0x20 // Debug read from YULD Input stage buffer with 32-bits granularity. Rea…
83143 … // Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LC…
83144 …to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset wit…
83145 …to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LT…
83146 …to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LC…
83147 …to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID nee…
83153 …0x1281900UL //Access:R DataWidth:0xa // Debug only. Read only access to LCID CAM in XX prote…
83156 …to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connect…
83159 …to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstS…
83185 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83186 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83187 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83188 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83189 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83190 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83191 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83192 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83193 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83194 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83195 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83196 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83197 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83198 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83199 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83200 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83201 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83202 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83203 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83204 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83205 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83206 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83207 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83208 …Width:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specifi…
83209 …0UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
83210 …80UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83211 …4UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
83212 …84UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83213 …8UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
83214 …88UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83215 …cUL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
83216 …8cUL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83217 …0UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
83218 …90UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83219 …4UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
83220 …94UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83221 …8UL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
83222 …98UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83223 …cUL //Access:RW DataWidth:0x2 // Agggregation connection context size to be read/written back…
83224 …9cUL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83225 …a0UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83226 …a4UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83227 …a8UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83228 …acUL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83229 …b0UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83230 …b4UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83231 …b8UL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83232 …bcUL //Access:RW DataWidth:0x2 // Aggregation connection context size to be read/written back…
83353 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83354 …ess:R DataWidth:0x20 // Debug read from MULD Input stage buffer with 32-bits granularity. Rea…
83362 …taWidth:0x6 // Debug read from YSEM Input stage buffer: number of reads to next information uni…
83363 …ess:R DataWidth:0x20 // Debug read from YSEM Input stage buffer with 32-bits granularity. Rea…
83365 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83366 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83367 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83368 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83369 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83370 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83371 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83372 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83373 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83374 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83375 … // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue ind…
83376 …cess:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanis…
83380 … (0x1<<0) // Full input from external IF to LS input enable.
83384 … (0x1<<2) // FIC input enable bit used to enable/disable messa…
83386 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disable ackno…
83392 …2 (0x1<<6) // Data input enable to RAM.
83398 … (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
83405 … (0x1<<2) // FOC output otuput enable bit used to enable/disable messa…
83409 …K2 (0x1<<4) // Data output enable to RAM.
83411 … (0x1<<5) // Stall output enable bit used to enable/disable the o…
83424 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
83435 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
83438 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
83440 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
83442 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
83444 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
83446 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
83449 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
83451 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
83453 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
83455 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83458 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
83460 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
83462 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
83464 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
83471 …en exceeded, then the Arbiter3 will select with strict priority the threads assigned to Affinity A.
83478 …en exceeded, then the Arbiter4 will select with strict priority the threads assigned to Affinity B.
83481 … (0x1<<0) // Enable DRA Write to transactions towards…
83483 … (0x1<<1) // Enable DRA Write to transactions towards…
83485 … (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
83487 … (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Affic…
83490 … (0x1<<0) // Signals an unknown address to the rf module.
83492 … (0x1<<1) // Last from FIC is not equal to length on any one of…
83494 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83522 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83526 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
83570 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83728 … (0x1<<0) // Signals an unknown address to the rf module.
83730 … (0x1<<1) // Last from FIC is not equal to length on any one of…
83732 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83760 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83764 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
83808 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83847 … (0x1<<0) // Signals an unknown address to the rf module.
83849 … (0x1<<1) // Last from FIC is not equal to length on any one of…
83851 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
83879 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
83883 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
83927 … (0x1<<11) // Signals an unknown address in the fast-memory window.
83966 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
84036 … (0x1<<3) // There was an attempt to make an external loa…
84038 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
84040 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
84042 … (0x1<<6) // There was an attempt to release a thread tha…
84044 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84048 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
84052 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
84054 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
84148 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
84218 … (0x1<<3) // There was an attempt to make an external loa…
84220 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
84222 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
84224 … (0x1<<6) // There was an attempt to release a thread tha…
84226 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84230 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
84234 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
84236 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
84239 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
84309 … (0x1<<3) // There was an attempt to make an external loa…
84311 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
84313 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
84315 … (0x1<<6) // There was an attempt to release a thread tha…
84317 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84321 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
84325 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
84327 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
84356 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84358 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84364 … (0x1<<17) // Error when trying to release a lock which…
84366 …ROR_E5 (0x1<<18) // Trying to acquire a lock which…
84368 …RROR_E5 (0x1<<19) // Trying to relinquish a key whi…
84372 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
84382 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
84384 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
84386 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
84388 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
84390 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
84482 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84484 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84490 … (0x1<<17) // Error when trying to release a lock which…
84492 …_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
84494 …H_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
84498 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
84508 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
84510 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
84512 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
84514 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
84516 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
84545 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
84547 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
84553 … (0x1<<17) // Error when trying to release a lock which…
84555 …T_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
84557 …SH_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
84561 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
84571 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
84573 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
84575 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
84577 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
84579 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
84628 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
84629 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
84630 …:0xf0 // This read-only register provides a vector of bits having an error indication per VF whe…
84633 …:0x10 // This read-only register provides a vector of bits having an error indication per PF whe…
84634 …44UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
84635 …PRAM address to be used for the handler in the event that the PRAM address retrieved from the inte…
84637 … 0x1400450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
84638 … 0x1400450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
84640 …L //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activ…
84641 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
84642 …the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode.…
84643 …to a thread address section passive buffer may occur simultaneously with read (as long that no coh…
84644 … 0x1400468UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
84645 … 0x1400580UL //Access:WB_R DataWidth:0x80 // Used for debugging to read/write to/from the FIC …
84647 …h:0x6 // Per-FIC interface register array defines minimum number of cycles in the FIC interface…
84649 …-through" mode for the FIC interface. In this mode, the FIC interface will not require that the av…
84650 …to count the number of FIC messages that have been received on any FIC interface and were allowed …
84653 … allows the DRA read operation to start even when there are not enough credits on all the particip…
84656 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
84658 … 0x1400900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buf…
84659 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84660 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
84662 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
84664 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
84667 …0x1400b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
84674 …1400b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
84675 …m message reuired for the FOC transfer to start. The values define in this register represents the…
84677 …ter array of registers provides read/write access to the head pointers assigned to each of the thr…
84679 …ect) register array of registers provides read/write access to the tail pointers assigned to each …
84681 …ccess:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to …
84683 …to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is b…
84685 …1400e00UL //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enabl…
84686 …400e08UL //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enabl…
84687 …on when the PFNum is chosen to control this selection. The value of this register is added to PFNu…
84691 …1008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM).
84696 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
84697 …in FIC0 A queue. If FIC0 message is received and number of threads equals to the configured value…
84698 …in FIC0 X queue. If FIC0 message is received and number of threads equals to the configured value…
84699 …in FIC0 B queue. If FIC0 message is received and number of threads equals to the configured value…
84700 … in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value…
84701 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
84714 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84717 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
84720 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
84721 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
84728 … DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold c…
84733 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
84738 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
84744 …value of threads interrupt counter; when it gets this value then interrupt to will be send if thre…
84749 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
84751 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
84754 …ataWidth:0x5 // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
84756 …to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the cor…
84758 …0x140142cUL //Access:RW DataWidth:0x1 // Enable performance monitor statistics sent to SEM_PD.
84760 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84761 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84762 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84763 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84764 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84765 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84766 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84767 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84768 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84769 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84770 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84771 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
84772 …alue (according to passive_buffer_performance_mon_stat value) of threads that are waiting for read…
84777 … 0x1401528UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
84778 … line) in the selected line (before shift).for selecting a line to output
84782 … 0x1408000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
84784 …dth:0x1e // Interrupt table read/write access. This register is intended to be written only when…
84786 …1000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of t…
84788 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
84793 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84794 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
84803 … (0x1<<0) // Full input from external IF to LS input enable.
84807 … (0x1<<2) // FIC input enable bit used to enable/disable messa…
84809 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disable ackno…
84815 …2 (0x1<<6) // Data input enable to RAM.
84821 … (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
84828 … (0x1<<2) // FOC output otuput enable bit used to enable/disable messa…
84832 …K2 (0x1<<4) // Data output enable to RAM.
84834 … (0x1<<5) // Stall output enable bit used to enable/disable the o…
84847 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
84858 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
84861 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
84863 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
84865 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
84867 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
84869 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
84872 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
84874 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
84876 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
84878 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84881 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
84883 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
84885 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
84887 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
84894 …en exceeded, then the Arbiter3 will select with strict priority the threads assigned to Affinity A.
84901 …en exceeded, then the Arbiter4 will select with strict priority the threads assigned to Affinity B.
84904 … (0x1<<0) // Enable DRA Write to transactions towards…
84906 … (0x1<<1) // Enable DRA Write to transactions towards…
84908 … (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
84910 … (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Affic…
84913 … (0x1<<0) // Signals an unknown address to the rf module.
84915 … (0x1<<1) // Last from FIC is not equal to length on any one of…
84917 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
84945 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
84949 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
84993 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85151 … (0x1<<0) // Signals an unknown address to the rf module.
85153 … (0x1<<1) // Last from FIC is not equal to length on any one of…
85155 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85183 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85187 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
85231 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85270 … (0x1<<0) // Signals an unknown address to the rf module.
85272 … (0x1<<1) // Last from FIC is not equal to length on any one of…
85274 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
85302 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85306 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
85350 … (0x1<<11) // Signals an unknown address in the fast-memory window.
85389 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
85459 … (0x1<<3) // There was an attempt to make an external loa…
85461 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
85463 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
85465 … (0x1<<6) // There was an attempt to release a thread tha…
85467 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85471 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
85475 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
85477 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
85571 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
85641 … (0x1<<3) // There was an attempt to make an external loa…
85643 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
85645 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
85647 … (0x1<<6) // There was an attempt to release a thread tha…
85649 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85653 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
85657 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
85659 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
85662 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
85732 … (0x1<<3) // There was an attempt to make an external loa…
85734 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
85736 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
85738 … (0x1<<6) // There was an attempt to release a thread tha…
85740 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
85744 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
85748 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
85750 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
85779 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85781 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85787 … (0x1<<17) // Error when trying to release a lock which…
85789 …ROR_E5 (0x1<<18) // Trying to acquire a lock which…
85791 …RROR_E5 (0x1<<19) // Trying to relinquish a key whi…
85795 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
85805 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
85807 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
85809 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
85811 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
85813 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
85905 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85907 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85913 … (0x1<<17) // Error when trying to release a lock which…
85915 …_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
85917 …H_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
85921 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
85931 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
85933 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
85935 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
85937 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
85939 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
85968 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
85970 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
85976 … (0x1<<17) // Error when trying to release a lock which…
85978 …T_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
85980 …SH_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
85984 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
85994 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
85996 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
85998 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
86000 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
86002 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
86051 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
86052 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
86053 …:0xf0 // This read-only register provides a vector of bits having an error indication per VF whe…
86056 …:0x10 // This read-only register provides a vector of bits having an error indication per PF whe…
86057 …44UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
86058 …PRAM address to be used for the handler in the event that the PRAM address retrieved from the inte…
86060 … 0x1500450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
86061 … 0x1500450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
86063 …L //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activ…
86064 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
86065 …the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode.…
86066 …to a thread address section passive buffer may occur simultaneously with read (as long that no coh…
86067 … 0x1500468UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
86068 … 0x1500580UL //Access:WB_R DataWidth:0x80 // Used for debugging to read/write to/from the FIC …
86070 …h:0x6 // Per-FIC interface register array defines minimum number of cycles in the FIC interface…
86072 …-through" mode for the FIC interface. In this mode, the FIC interface will not require that the av…
86073 …to count the number of FIC messages that have been received on any FIC interface and were allowed …
86076 … allows the DRA read operation to start even when there are not enough credits on all the particip…
86079 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
86081 … 0x1500900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buf…
86082 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86083 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
86085 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
86087 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
86090 …0x1500b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
86097 …1500b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
86098 …m message reuired for the FOC transfer to start. The values define in this register represents the…
86100 …ter array of registers provides read/write access to the head pointers assigned to each of the thr…
86102 …ect) register array of registers provides read/write access to the tail pointers assigned to each …
86104 …ccess:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to …
86106 …to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is b…
86108 …1500e00UL //Access:RW DataWidth:0xe // Provides access to the thread ordering queue pop-enabl…
86109 …500e08UL //Access:RW DataWidth:0xe // Provides access to the thread ordering queue wake-enabl…
86110 …on when the PFNum is chosen to control this selection. The value of this register is added to PFNu…
86114 …1008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM).
86119 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
86120 …in FIC0 A queue. If FIC0 message is received and number of threads equals to the configured value…
86121 …in FIC0 X queue. If FIC0 message is received and number of threads equals to the configured value…
86122 …in FIC0 B queue. If FIC0 message is received and number of threads equals to the configured value…
86123 … in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value…
86124 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
86137 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86140 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
86143 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
86144 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
86151 … DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold c…
86156 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
86161 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
86167 …value of threads interrupt counter; when it gets this value then interrupt to will be send if thre…
86172 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
86174 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
86177 …ataWidth:0x5 // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
86179 …to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the cor…
86181 …0x150142cUL //Access:RW DataWidth:0x1 // Enable performance monitor statistics sent to SEM_PD.
86183 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86184 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86185 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86186 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86187 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86188 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86189 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86190 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86191 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86192 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86193 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86194 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
86195 …alue (according to passive_buffer_performance_mon_stat value) of threads that are waiting for read…
86200 … 0x1501528UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
86201 … line) in the selected line (before shift).for selecting a line to output
86205 … 0x1508000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
86207 …dth:0x1e // Interrupt table read/write access. This register is intended to be written only when…
86209 …1000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of t…
86211 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
86216 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86217 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
86227 … (0x1<<0) // Full input from external IF to LS input enable.
86231 … (0x1<<2) // FIC input enable bit used to enable/disable messa…
86233 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disable ackno…
86239 …2 (0x1<<6) // Data input enable to RAM.
86245 … (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
86252 … (0x1<<2) // FOC output otuput enable bit used to enable/disable messa…
86256 …K2 (0x1<<4) // Data output enable to RAM.
86258 … (0x1<<5) // Stall output enable bit used to enable/disable the o…
86271 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
86282 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
86285 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
86287 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
86289 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
86291 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
86293 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
86296 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
86298 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
86300 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
86302 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86305 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
86307 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
86309 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
86311 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
86318 …en exceeded, then the Arbiter3 will select with strict priority the threads assigned to Affinity A.
86325 …en exceeded, then the Arbiter4 will select with strict priority the threads assigned to Affinity B.
86328 … (0x1<<0) // Enable DRA Write to transactions towards…
86330 … (0x1<<1) // Enable DRA Write to transactions towards…
86332 … (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
86334 … (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Affic…
86337 … (0x1<<0) // Signals an unknown address to the rf module.
86339 … (0x1<<1) // Last from FIC is not equal to length on any one of…
86341 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86369 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86373 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
86417 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86575 … (0x1<<0) // Signals an unknown address to the rf module.
86577 … (0x1<<1) // Last from FIC is not equal to length on any one of…
86579 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86607 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86611 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
86655 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86694 … (0x1<<0) // Signals an unknown address to the rf module.
86696 … (0x1<<1) // Last from FIC is not equal to length on any one of…
86698 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
86726 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86730 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
86774 … (0x1<<11) // Signals an unknown address in the fast-memory window.
86813 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
86883 … (0x1<<3) // There was an attempt to make an external loa…
86885 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
86887 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
86889 … (0x1<<6) // There was an attempt to release a thread tha…
86891 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
86895 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
86899 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
86901 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
86995 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
87065 … (0x1<<3) // There was an attempt to make an external loa…
87067 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
87069 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
87071 … (0x1<<6) // There was an attempt to release a thread tha…
87073 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87077 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
87081 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
87083 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
87086 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
87156 … (0x1<<3) // There was an attempt to make an external loa…
87158 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
87160 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
87162 … (0x1<<6) // There was an attempt to release a thread tha…
87164 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87168 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
87172 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
87174 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
87203 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87205 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87211 … (0x1<<17) // Error when trying to release a lock which…
87213 …ROR_E5 (0x1<<18) // Trying to acquire a lock which…
87215 …RROR_E5 (0x1<<19) // Trying to relinquish a key whi…
87219 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
87229 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
87231 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
87233 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
87235 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
87237 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
87329 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87331 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87337 … (0x1<<17) // Error when trying to release a lock which…
87339 …_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
87341 …H_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
87345 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
87355 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
87357 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
87359 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
87361 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
87363 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
87392 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
87394 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
87400 … (0x1<<17) // Error when trying to release a lock which…
87402 …T_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
87404 …SH_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
87408 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
87418 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
87420 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
87422 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
87424 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
87426 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
87473 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
87474 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
87475 …:0xf0 // This read-only register provides a vector of bits having an error indication per VF whe…
87478 …:0x10 // This read-only register provides a vector of bits having an error indication per PF whe…
87479 …44UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
87480 …PRAM address to be used for the handler in the event that the PRAM address retrieved from the inte…
87482 … 0x1600450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
87483 … 0x1600450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
87485 …L //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activ…
87486 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
87487 …the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode.…
87488 …to a thread address section passive buffer may occur simultaneously with read (as long that no coh…
87489 … 0x1600468UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
87490 … 0x1600580UL //Access:WB_R DataWidth:0x80 // Used for debugging to read/write to/from the FIC …
87492 …h:0x6 // Per-FIC interface register array defines minimum number of cycles in the FIC interface…
87493 …-through" mode for the FIC interface. In this mode, the FIC interface will not require that the av…
87494 …to count the number of FIC messages that have been received on any FIC interface and were allowed …
87497 … allows the DRA read operation to start even when there are not enough credits on all the particip…
87500 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
87502 … 0x1600900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buf…
87503 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87504 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
87506 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
87508 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
87511 …0x1600b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
87518 …1600b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
87519 …m message reuired for the FOC transfer to start. The values define in this register represents the…
87521 …ter array of registers provides read/write access to the head pointers assigned to each of the thr…
87523 …ect) register array of registers provides read/write access to the tail pointers assigned to each …
87525 …ccess:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to …
87527 …to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is b…
87529 …1600e00UL //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue pop-enabl…
87530 …600e08UL //Access:RW DataWidth:0x4 // Provides access to the thread ordering queue wake-enabl…
87531 …on when the PFNum is chosen to control this selection. The value of this register is added to PFNu…
87535 …1008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM).
87540 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
87541 …in FIC0 A queue. If FIC0 message is received and number of threads equals to the configured value…
87542 …in FIC0 X queue. If FIC0 message is received and number of threads equals to the configured value…
87543 …in FIC0 B queue. If FIC0 message is received and number of threads equals to the configured value…
87544 … in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value…
87545 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
87557 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87560 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
87563 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
87564 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
87570 … DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold c…
87575 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
87580 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
87586 …value of threads interrupt counter; when it gets this value then interrupt to will be send if thre…
87591 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
87593 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
87596 …ataWidth:0x5 // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
87598 …to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the cor…
87600 …0x160142cUL //Access:RW DataWidth:0x1 // Enable performance monitor statistics sent to SEM_PD.
87602 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87603 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87604 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87605 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87606 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87607 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87608 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87609 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87610 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87611 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87612 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87613 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
87614 …alue (according to passive_buffer_performance_mon_stat value) of threads that are waiting for read…
87619 … 0x1601528UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
87620 … line) in the selected line (before shift).for selecting a line to output
87624 … 0x1608000UL //Access:WB_R DataWidth:0x4a // Provides read-only access of the ex…
87626 …dth:0x1e // Interrupt table read/write access. This register is intended to be written only when…
87628 …1000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of t…
87630 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
87635 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87636 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
87646 … (0x1<<0) // Full input from external IF to LS input enable.
87650 … (0x1<<2) // FIC input enable bit used to enable/disable messa…
87652 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disable ackno…
87658 …2 (0x1<<6) // Data input enable to RAM.
87664 … (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
87671 … (0x1<<2) // FOC output otuput enable bit used to enable/disable messa…
87675 …K2 (0x1<<4) // Data output enable to RAM.
87677 … (0x1<<5) // Stall output enable bit used to enable/disable the o…
87690 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
87701 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
87704 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
87706 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
87708 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
87710 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
87712 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
87715 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
87717 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
87719 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
87721 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87724 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
87726 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
87728 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
87730 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
87737 …en exceeded, then the Arbiter3 will select with strict priority the threads assigned to Affinity A.
87744 …en exceeded, then the Arbiter4 will select with strict priority the threads assigned to Affinity B.
87747 … (0x1<<0) // Enable DRA Write to transactions towards…
87749 … (0x1<<1) // Enable DRA Write to transactions towards…
87751 … (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
87753 … (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Affic…
87756 … (0x1<<0) // Signals an unknown address to the rf module.
87758 … (0x1<<1) // Last from FIC is not equal to length on any one of…
87760 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
87788 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
87792 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
87836 … (0x1<<11) // Signals an unknown address in the fast-memory window.
87994 … (0x1<<0) // Signals an unknown address to the rf module.
87996 … (0x1<<1) // Last from FIC is not equal to length on any one of…
87998 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88026 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88030 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
88074 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88113 … (0x1<<0) // Signals an unknown address to the rf module.
88115 … (0x1<<1) // Last from FIC is not equal to length on any one of…
88117 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
88145 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88149 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
88193 … (0x1<<11) // Signals an unknown address in the fast-memory window.
88232 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
88302 … (0x1<<3) // There was an attempt to make an external loa…
88304 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
88306 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
88308 … (0x1<<6) // There was an attempt to release a thread tha…
88310 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88314 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
88318 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
88320 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
88414 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
88484 … (0x1<<3) // There was an attempt to make an external loa…
88486 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
88488 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
88490 … (0x1<<6) // There was an attempt to release a thread tha…
88492 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88496 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
88500 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
88502 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
88505 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
88575 … (0x1<<3) // There was an attempt to make an external loa…
88577 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
88579 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
88581 … (0x1<<6) // There was an attempt to release a thread tha…
88583 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
88587 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
88591 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
88593 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
88622 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88624 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88630 … (0x1<<17) // Error when trying to release a lock which…
88632 …ROR_E5 (0x1<<18) // Trying to acquire a lock which…
88634 …RROR_E5 (0x1<<19) // Trying to relinquish a key whi…
88638 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
88648 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
88650 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
88652 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
88654 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
88656 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
88748 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88750 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88756 … (0x1<<17) // Error when trying to release a lock which…
88758 …_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
88760 …H_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
88764 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
88774 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
88776 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
88778 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
88780 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
88782 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
88811 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
88813 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
88819 … (0x1<<17) // Error when trying to release a lock which…
88821 …T_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
88823 …SH_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
88827 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
88837 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
88839 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
88841 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
88843 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
88845 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
88892 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
88893 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
88894 …:0xf0 // This read-only register provides a vector of bits having an error indication per VF whe…
88897 …:0x10 // This read-only register provides a vector of bits having an error indication per PF whe…
88898 …44UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
88899 …PRAM address to be used for the handler in the event that the PRAM address retrieved from the inte…
88901 … 0x1700450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
88902 … 0x1700450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
88904 …L //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activ…
88905 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
88906 …the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode.…
88907 …to a thread address section passive buffer may occur simultaneously with read (as long that no coh…
88908 … 0x1700468UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
88909 … 0x1700580UL //Access:WB_R DataWidth:0x80 // Used for debugging to read/write to/from the FIC …
88911 …h:0x6 // Per-FIC interface register array defines minimum number of cycles in the FIC interface…
88912 …-through" mode for the FIC interface. In this mode, the FIC interface will not require that the av…
88913 …to count the number of FIC messages that have been received on any FIC interface and were allowed …
88916 … allows the DRA read operation to start even when there are not enough credits on all the particip…
88919 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
88921 … 0x1700900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buf…
88922 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88923 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
88925 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
88927 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
88930 …0x1700b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
88937 …1700b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
88938 …m message reuired for the FOC transfer to start. The values define in this register represents the…
88940 …ter array of registers provides read/write access to the head pointers assigned to each of the thr…
88942 …ect) register array of registers provides read/write access to the tail pointers assigned to each …
88944 …ccess:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to …
88946 …to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is b…
88948 …1700e00UL //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enabl…
88949 …700e08UL //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enabl…
88950 …on when the PFNum is chosen to control this selection. The value of this register is added to PFNu…
88954 …1008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM).
88959 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
88960 …in FIC0 A queue. If FIC0 message is received and number of threads equals to the configured value…
88961 …in FIC0 X queue. If FIC0 message is received and number of threads equals to the configured value…
88962 …in FIC0 B queue. If FIC0 message is received and number of threads equals to the configured value…
88963 … in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value…
88964 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
88976 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
88979 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
88982 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
88983 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
88989 … DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold c…
88994 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
88999 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
89005 …value of threads interrupt counter; when it gets this value then interrupt to will be send if thre…
89010 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
89012 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
89015 …ataWidth:0x5 // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
89017 …to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the cor…
89019 …0x170142cUL //Access:RW DataWidth:0x1 // Enable performance monitor statistics sent to SEM_PD.
89021 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89022 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89023 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89024 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89025 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89026 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89027 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89028 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89029 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89030 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89031 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89032 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
89033 …alue (according to passive_buffer_performance_mon_stat value) of threads that are waiting for read…
89038 … 0x1701528UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
89039 … line) in the selected line (before shift).for selecting a line to output
89043 … 0x1708000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
89045 …dth:0x1e // Interrupt table read/write access. This register is intended to be written only when…
89047 …1000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of t…
89049 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
89054 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89055 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
89064 … (0x1<<0) // Full input from external IF to LS input enable.
89068 … (0x1<<2) // FIC input enable bit used to enable/disable messa…
89070 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disable ackno…
89076 …2 (0x1<<6) // Data input enable to RAM.
89082 … (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
89089 … (0x1<<2) // FOC output otuput enable bit used to enable/disable messa…
89093 …K2 (0x1<<4) // Data output enable to RAM.
89095 … (0x1<<5) // Stall output enable bit used to enable/disable the o…
89108 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
89119 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
89122 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
89124 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
89126 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
89128 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
89130 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
89133 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
89135 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
89137 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
89139 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89142 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
89144 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
89146 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
89148 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
89155 …en exceeded, then the Arbiter3 will select with strict priority the threads assigned to Affinity A.
89162 …en exceeded, then the Arbiter4 will select with strict priority the threads assigned to Affinity B.
89165 … (0x1<<0) // Enable DRA Write to transactions towards…
89167 … (0x1<<1) // Enable DRA Write to transactions towards…
89169 … (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
89171 … (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Affic…
89174 … (0x1<<0) // Signals an unknown address to the rf module.
89176 … (0x1<<1) // Last from FIC is not equal to length on any one of…
89178 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89206 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89210 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
89254 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89412 … (0x1<<0) // Signals an unknown address to the rf module.
89414 … (0x1<<1) // Last from FIC is not equal to length on any one of…
89416 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89444 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89448 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
89492 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89531 … (0x1<<0) // Signals an unknown address to the rf module.
89533 … (0x1<<1) // Last from FIC is not equal to length on any one of…
89535 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
89563 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89567 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
89611 … (0x1<<11) // Signals an unknown address in the fast-memory window.
89650 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
89720 … (0x1<<3) // There was an attempt to make an external loa…
89722 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
89724 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
89726 … (0x1<<6) // There was an attempt to release a thread tha…
89728 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89732 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
89736 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
89738 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
89832 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
89902 … (0x1<<3) // There was an attempt to make an external loa…
89904 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
89906 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
89908 … (0x1<<6) // There was an attempt to release a thread tha…
89910 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
89914 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
89918 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
89920 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
89923 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
89993 … (0x1<<3) // There was an attempt to make an external loa…
89995 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
89997 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
89999 … (0x1<<6) // There was an attempt to release a thread tha…
90001 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90005 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
90009 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
90011 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
90040 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90042 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90048 … (0x1<<17) // Error when trying to release a lock which…
90050 …ROR_E5 (0x1<<18) // Trying to acquire a lock which…
90052 …RROR_E5 (0x1<<19) // Trying to relinquish a key whi…
90056 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
90066 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
90068 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
90070 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
90072 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
90074 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
90166 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90168 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90174 … (0x1<<17) // Error when trying to release a lock which…
90176 …_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
90178 …H_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
90182 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
90192 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
90194 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
90196 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
90198 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
90200 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
90229 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
90231 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
90237 … (0x1<<17) // Error when trying to release a lock which…
90239 …T_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
90241 …SH_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
90245 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
90255 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
90257 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
90259 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
90261 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
90263 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
90374 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
90375 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
90376 …:0xf0 // This read-only register provides a vector of bits having an error indication per VF whe…
90379 …:0x10 // This read-only register provides a vector of bits having an error indication per PF whe…
90380 …44UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
90381 …PRAM address to be used for the handler in the event that the PRAM address retrieved from the inte…
90383 … 0x1800450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
90384 … 0x1800450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
90386 …L //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activ…
90387 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
90388 …the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode.…
90389 …to a thread address section passive buffer may occur simultaneously with read (as long that no coh…
90390 … 0x1800468UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
90391 … 0x1800580UL //Access:WB_R DataWidth:0x80 // Used for debugging to read/write to/from the FIC …
90393 …h:0x6 // Per-FIC interface register array defines minimum number of cycles in the FIC interface…
90394 …-through" mode for the FIC interface. In this mode, the FIC interface will not require that the av…
90395 …to count the number of FIC messages that have been received on any FIC interface and were allowed …
90398 … allows the DRA read operation to start even when there are not enough credits on all the particip…
90401 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
90403 … 0x1800900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buf…
90404 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90405 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
90407 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
90409 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
90412 …0x1800b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
90419 …1800b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
90420 …m message reuired for the FOC transfer to start. The values define in this register represents the…
90422 …ter array of registers provides read/write access to the head pointers assigned to each of the thr…
90424 …ect) register array of registers provides read/write access to the tail pointers assigned to each …
90426 …ccess:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to …
90428 …to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is b…
90430 …1800e00UL //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue pop-enabl…
90431 …800e08UL //Access:RW DataWidth:0x18 // Provides access to the thread ordering queue wake-enabl…
90432 …on when the PFNum is chosen to control this selection. The value of this register is added to PFNu…
90436 …1008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM).
90441 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
90442 …in FIC0 A queue. If FIC0 message is received and number of threads equals to the configured value…
90443 …in FIC0 X queue. If FIC0 message is received and number of threads equals to the configured value…
90444 …in FIC0 B queue. If FIC0 message is received and number of threads equals to the configured value…
90445 … in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value…
90446 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
90458 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90461 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
90464 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
90465 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
90471 … DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold c…
90476 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
90481 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
90487 …value of threads interrupt counter; when it gets this value then interrupt to will be send if thre…
90492 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
90494 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
90497 …ataWidth:0x5 // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
90499 …to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the cor…
90501 …0x180142cUL //Access:RW DataWidth:0x1 // Enable performance monitor statistics sent to SEM_PD.
90503 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90504 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90505 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90506 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90507 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90508 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90509 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90510 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90511 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90512 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90513 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90514 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
90515 …alue (according to passive_buffer_performance_mon_stat value) of threads that are waiting for read…
90520 … 0x1801528UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
90521 … line) in the selected line (before shift).for selecting a line to output
90525 … 0x1808000UL //Access:WB_R DataWidth:0x4d // Provides read-only access of the ex…
90527 …dth:0x1e // Interrupt table read/write access. This register is intended to be written only when…
90529 …1000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of t…
90531 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
90536 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90537 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
90547 … (0x1<<0) // Full input from external IF to LS input enable.
90551 … (0x1<<2) // FIC input enable bit used to enable/disable messa…
90553 … (0x1<<3) // FOC acknowledge input enable bit used to enable/disable ackno…
90559 …2 (0x1<<6) // Data input enable to RAM.
90565 … (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
90572 … (0x1<<2) // FOC output otuput enable bit used to enable/disable messa…
90576 …K2 (0x1<<4) // Data output enable to RAM.
90578 … (0x1<<5) // Stall output enable bit used to enable/disable the o…
90591 … PB WR arbiter should have strict priority: 000 - None, 001 - FIC, 010 - DRA RD A, 011 - DRA RD B,…
90602 … PB WR arbiter should have strict priority: 000 - None, 001 - FOC, 010 - DRA RD A, 011 - DRA RD B,…
90605 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-A source.
90607 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for FIC1-a (if exist) source.
90609 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-A source.
90611 … (0xf<<12) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-A source.
90613 …ce of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1, 4 - …
90616 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-X source.
90618 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-X source.
90620 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-X source.
90622 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90625 … (0xf<<0) // Passive Buffer Queue Arbiter WRR weight value for FIC0-B source.
90627 … (0xf<<4) // Passive Buffer Queue Arbiter WRR weight value for PRIO0-B source.
90629 … (0xf<<8) // Passive Buffer Queue Arbiter WRR weight value for PRIO1-B source.
90631 …e source of the PB WR arbiter should have strict priority: 0 - None, 1 - FIC0, 2- Prio0, 3 - Prio1.
90638 …en exceeded, then the Arbiter3 will select with strict priority the threads assigned to Affinity A.
90645 …en exceeded, then the Arbiter4 will select with strict priority the threads assigned to Affinity B.
90648 … (0x1<<0) // Enable DRA Write to transactions towards…
90650 … (0x1<<1) // Enable DRA Write to transactions towards…
90652 … (0x1<<2) // When set, there may only be a single thread pending to run for each storm.
90654 … (0x1<<3) // When set, the Affintiy field of the thread is set to CoreA (regardless to the Affic…
90657 … (0x1<<0) // Signals an unknown address to the rf module.
90659 … (0x1<<1) // Last from FIC is not equal to length on any one of…
90661 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90689 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90693 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
90737 … (0x1<<11) // Signals an unknown address in the fast-memory window.
90895 … (0x1<<0) // Signals an unknown address to the rf module.
90897 … (0x1<<1) // Last from FIC is not equal to length on any one of…
90899 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
90927 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
90931 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
90975 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91014 … (0x1<<0) // Signals an unknown address to the rf module.
91016 … (0x1<<1) // Last from FIC is not equal to length on any one of…
91018 … (0x1<<2) // FIC length > 44 register-quads on any one of t…
91046 …1<<14) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91050 …finity field is not "Storm A". (Error since FIC1 messages can only be designated to run on Storm A)
91094 … (0x1<<11) // Signals an unknown address in the fast-memory window.
91133 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
91203 … (0x1<<3) // There was an attempt to make an external loa…
91205 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
91207 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
91209 … (0x1<<6) // There was an attempt to release a thread tha…
91211 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91215 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
91219 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
91221 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
91315 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
91385 … (0x1<<3) // There was an attempt to make an external loa…
91387 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
91389 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
91391 … (0x1<<6) // There was an attempt to release a thread tha…
91393 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91397 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
91401 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
91403 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
91406 … (0x1<<0) // Both Storm are simultaneously trying to access the VFC.
91476 … (0x1<<3) // There was an attempt to make an external loa…
91478 …was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to re…
91480 … (0x1<<5) // There was an attempt to release a thread that was already un-al…
91482 … (0x1<<6) // There was an attempt to release a thread tha…
91484 …x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID enco…
91488 … (0x1<<9) // Indicates that the Storm attempted to send a FIN command w…
91492 … (0x1<<11) // Indicates that there was an attempt to pop from a thread or…
91494 …to pop the currently-running thread onto a thread- order queue when it was not at the head of the …
91523 …_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91525 …_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91531 … (0x1<<17) // Error when trying to release a lock which…
91533 …ROR_E5 (0x1<<18) // Trying to acquire a lock which…
91535 …RROR_E5 (0x1<<19) // Trying to relinquish a key whi…
91539 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
91549 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
91551 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
91553 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
91555 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
91557 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
91649 …R_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91651 …R_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91657 … (0x1<<17) // Error when trying to release a lock which…
91659 …_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
91661 …H_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
91665 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
91675 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
91677 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
91679 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
91681 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
91683 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
91712 …OR_A_E5 (0x1<<13) // Pre-fetch FIFO error of S…
91714 …OR_B_E5 (0x1<<14) // Pre-fetch FIFO error of S…
91720 … (0x1<<17) // Error when trying to release a lock which…
91722 …T_ERROR_E5 (0x1<<18) // Trying to acquire a lock which…
91724 …SH_ERROR_E5 (0x1<<19) // Trying to relinquish a key whi…
91728 … (0x1<<21) // Error when both Storm are stalled due to lock block (may indi…
91738 … (0x1<<26) // BAR IOR of STORM_A remapping causes two different IORs to be mapped to the same rang…
91740 … (0x1<<27) // BAR IOR of STORM_B remapping causes two different IORs to be mapped to the same rang…
91742 … (0x1<<28) // BAR IOR remmap of STORM_A indication causes IORs are mapped to out of range IORs.
91744 … (0x1<<29) // BAR IOR remap of STORM_B indication causes IORs are mapped to out of range IORs.
91746 … (0x1<<30) // This error indicates on an unalligned wire access to PRAM via SDM.
91793 …-split register provides read/clear access to the VF error received from the SDM for a DMA transfe…
91794 …-split register provides read/clear access to the PF error received from the SDM for a DMA transfe…
91795 …:0xf0 // This read-only register provides a vector of bits having an error indication per VF whe…
91798 …:0x10 // This read-only register provides a vector of bits having an error indication per PF whe…
91799 …44UL //Access:RW DataWidth:0x1 // Clear stall signal sent from local storm to external storms.
91800 …PRAM address to be used for the handler in the event that the PRAM address retrieved from the inte…
91802 … 0x1900450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
91803 … 0x1900450UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
91805 …L //Access:RW DataWidth:0x1 // When set, this bit is used to allow low-power mode to be activ…
91806 …dth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.
91807 …the SDM DMA write to passive buffer. 00 - Use mask vector mode. 01 - Use write on sleep sate mode.…
91808 …to a thread address section passive buffer may occur simultaneously with read (as long that no coh…
91809 … 0x1900468UL //Access:R DataWidth:0x20 // Used to read the GPI input s…
91810 … 0x1900580UL //Access:WB_R DataWidth:0x80 // Used for debugging to read/write to/from the FIC …
91812 …h:0x6 // Per-FIC interface register array defines minimum number of cycles in the FIC interface…
91813 …-through" mode for the FIC interface. In this mode, the FIC interface will not require that the av…
91814 …to count the number of FIC messages that have been received on any FIC interface and were allowed …
91817 … allows the DRA read operation to start even when there are not enough credits on all the particip…
91820 … foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:…
91822 … 0x1900900UL //Access:RW DataWidth:0x1 // When set, an attempt to write to the passive buf…
91823 …ss:R DataWidth:0x5 // Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91824 …:R DataWidth:0x5 // Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-…
91826 …-dimensional register array is used to define each of four arbitration schemes used by the main DR…
91828 …gister array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].
91831 …0x1900b04UL //Access:R DataWidth:0x20 // Thread error low indication. Represents threads 31 -0
91838 …1900b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32
91839 …m message reuired for the FOC transfer to start. The values define in this register represents the…
91841 …ter array of registers provides read/write access to the head pointers assigned to each of the thr…
91843 …ect) register array of registers provides read/write access to the tail pointers assigned to each …
91845 …ccess:RW DataWidth:0x1 // This vector provides read-only access to the empty bit assigned to …
91847 …to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is b…
91849 …1900e00UL //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue pop-enabl…
91850 …900e08UL //Access:RW DataWidth:0x10 // Provides access to the thread ordering queue wake-enabl…
91851 …on when the PFNum is chosen to control this selection. The value of this register is added to PFNu…
91855 …1008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM).
91860 …ss:RW DataWidth:0x2 // 00 - No stall. 01 - Only SEMI's Stroms will be stalled on any unmasked…
91861 …in FIC0 A queue. If FIC0 message is received and number of threads equals to the configured value…
91862 …in FIC0 X queue. If FIC0 message is received and number of threads equals to the configured value…
91863 …in FIC0 B queue. If FIC0 message is received and number of threads equals to the configured value…
91864 … in FIC1 A queue. If FIC1 message is received and number of threads equals to the configured value…
91865 …Width:0x1 // 0 - No external stall is asserted when Storm's breakpoint is set (either by PRAM a…
91877 … // DBG FAST SYNC FIFO is empty in sem_slow_ls_sync. Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91880 …- 0, FIC0_FIFO_A - 1, FIC1_FIFO_A - 2, WAKE_FIFO_PRIO_A - 3, WAKE_FIFO_PRI1_A - 4, FIC0_FIFO_X - …
91883 …UL //Access:R DataWidth:0x2 // FIC pre fetch FIFO empty indication. Bit0 - FIC0, BIT1 - FIC1.
91884 …DataWidth:0x2 // External Store pre fetch FIFO empty indication. Bit0 - Storm_A, BIT1 - Strom_B.
91890 … DataWidth:0x1 // DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold c…
91895 …taWidth:0x2 // EXT_STORE FIFO is full in sem_slow_ls_ext. Bit0 - Core A FIFO. Bit1 - Core B FIF…
91900 … // DBG FAST SYNC FIFO is full in sem_slow_ls_sync.Bit0 - FOR debug FIFO of Core A. Bit1 - FOR …
91906 …value of threads interrupt counter; when it gets this value then interrupt to will be send if thre…
91911 …- indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mo…
91913 …-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug c…
91916 …ataWidth:0x5 // In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.
91918 …to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the cor…
91920 …0x190142cUL //Access:RW DataWidth:0x1 // Enable performance monitor statistics sent to SEM_PD.
91922 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91923 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91924 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91925 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91926 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91927 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91928 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91929 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91930 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91931 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91932 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91933 … //Access:RC DataWidth:0x6 // Report maximum/current value (according to passive_buffer_perfo…
91934 …alue (according to passive_buffer_performance_mon_stat value) of threads that are waiting for read…
91939 … 0x1901528UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output
91940 … line) in the selected line (before shift).for selecting a line to output
91944 … 0x1908000UL //Access:WB_R DataWidth:0x4c // Provides read-only access of the ex…
91946 …dth:0x1e // Interrupt table read/write access. This register is intended to be written only when…
91948 …1000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of t…
91950 …- state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10…
91955 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…
91956 …-bit vectors provides a bit per register-quad, used to define the register-quad locations that sho…