Lines Matching +full:0 +full:x000000
39 #define CRC_MAGIC_VALUE 0xDEBB20E3
40 #define CRC32_POLYNOMIAL 0xEDB88320
56 #define NVM_MAGIC_VALUE 0x669955aa
75 NVM_TYPE_TIM1 = 0x01,
76 NVM_TYPE_TIM2 = 0x02,
77 NVM_TYPE_MIM1 = 0x03,
78 NVM_TYPE_MIM2 = 0x04,
79 NVM_TYPE_MBA = 0x05,
80 NVM_TYPE_MODULES_PN = 0x06,
81 NVM_TYPE_VPD = 0x07,
82 NVM_TYPE_MFW_TRACE1 = 0x08,
83 NVM_TYPE_MFW_TRACE2 = 0x09,
84 NVM_TYPE_NVM_CFG1 = 0x0a,
85 NVM_TYPE_L2B = 0x0b,
86 NVM_TYPE_DIR1 = 0x0c,
87 NVM_TYPE_EAGLE_FW1 = 0x0d,
88 NVM_TYPE_FALCON_FW1 = 0x0e,
89 NVM_TYPE_PCIE_FW1 = 0x0f,
90 NVM_TYPE_HW_SET = 0x10,
91 NVM_TYPE_LIM = 0x11,
92 NVM_TYPE_AVS_FW1 = 0x12,
93 NVM_TYPE_DIR2 = 0x13,
94 NVM_TYPE_CCM = 0x14,
95 NVM_TYPE_EAGLE_FW2 = 0x15,
96 NVM_TYPE_FALCON_FW2 = 0x16,
97 NVM_TYPE_PCIE_FW2 = 0x17,
98 NVM_TYPE_AVS_FW2 = 0x18,
99 NVM_TYPE_INIT_HW = 0x19,
100 NVM_TYPE_DEFAULT_CFG= 0x1a,
101 NVM_TYPE_MDUMP = 0x1b,
102 NVM_TYPE_NVM_META = 0x1c,
103 NVM_TYPE_ISCSI_CFG = 0x1d,
104 NVM_TYPE_FCOE_CFG = 0x1f,
105 NVM_TYPE_ETH_PHY_FW1 = 0x20,
106 NVM_TYPE_ETH_PHY_FW2 = 0x21,
107 NVM_TYPE_BDN = 0x22,
108 NVM_TYPE_8485X_PHY_FW = 0x23,
109 NVM_TYPE_PUB_KEY = 0x24,
110 NVM_TYPE_RECOVERY = 0x25,
111 NVM_TYPE_PLDM = 0x26,
112 NVM_TYPE_UPK1 = 0x27,
113 NVM_TYPE_UPK2 = 0x28,
114 NVM_TYPE_MASTER_KC = 0x29,
115 NVM_TYPE_BACKUP_KC = 0x2a,
116 NVM_TYPE_ROM_TEST = 0xf0,
186 #define NVM_DIR_NEXT_MFW_MASK 0x00000001
187 #define NVM_DIR_SEQ_MASK 0xfffffffe
192 } while (0)
212 #define DIR_ID_1 (0)
216 #define MFW_BUNDLE_1 (0)
220 #define FLASH_PAGE_SIZE 0x1000
225 #define FPGA_MIM_MAX_SIZE (0x3E000) /* 250Kb */
234 …(NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ?GET_MIM_MAX_SIZE(is_asic, is_e4) : 0))
237 #define EMUL_NVM_FIXED_AREA_SIZE() (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(0, 0))
239 #define E5_MASTER_KEY_CHAIN_ADDR 0x1000
240 #define E5_BACKUP_KEY_CHAIN_ADDR ((0x20000 << (REG_READ(0, MCP_REG_NVM_CFG4) & 0x7)) - 0x1000)
248 …* +-------------------+ 0x000000 * +-------------------+ 0x000000 …
255 …* +-------------------+ 0x000014 * | | …
257 …* +-------------------+ 0x000040 * +-------------------+ 0x001000 …
259 …* +-------------------+ 0x002000 * +-------------------+ 0x002000 …
261 …* +-------------------+ 0x003000 * +-------------------+ 0x003000 …
263 …* +-------------------+ 0x004000 * +-------------------+ 0x004000 …
265 …* +-------------------+ 0x130000 * +-------------------+ 0x130000 …
267 …* +-------------------+ 0x25C000 * +-------------------+ 0x25C000 …
275 …* | optic_modules | * +-------------------+ Flash end - 0x1000 …
277 …* +-------------------+ 0x400000 * +-------------------+ Flash end …
282 struct legacy_bootstrap_region bootstrap; /* 0x000000 (0x000014) */
283 u8 rsrv[NVM_RSV_SIZE]; /* 0x000014 (0x00002c) */
284 u8 lim_image[LIM_MAX_SIZE]; /* 0x000040 (0x001fc0) */
285 union nvm_dir_union dir[MAX_MFW_BUNDLES]; /* 0x002000 (0x001000)x2 */
286 /* MIM1_IMAGE 0x004000 (0x12c000) */
287 /* MIM2_IMAGE 0x130000 (0x12c000) */
289 }; /* 0x134 */
291 #define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f))))
311 #define POR_RESET_TYPE (1 << 0)