Lines Matching +full:done +full:- +full:gpios
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
69 { "qcom,spi-qup-v1.1.1", QCOM_SPI_HW_QPI_V1_1 },
70 { "qcom,spi-qup-v2.1.1", QCOM_SPI_HW_QPI_V2_1 },
71 { "qcom,spi-qup-v2.2.1", QCOM_SPI_HW_QPI_V2_2 },
88 if (sc->cs_pins[cs] == NULL) {
89 device_printf(sc->sc_dev,
112 gpio_pin_set_active(sc->cs_pins[cs], pinactive);
113 gpio_pin_is_active(sc->cs_pins[cs], &pinactive);
128 device_printf(sc->sc_dev,
130 goto done;
137 if (sc->transfer.active == false) {
138 device_printf(sc->sc_dev,
141 goto done;
145 if (sc->intr.error) {
146 sc->intr.error = false;
147 device_printf(sc->sc_dev, "ERROR: intr\n");
150 if (sc->intr.do_rx) {
151 sc->intr.do_rx = false;
154 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO)
159 device_printf(sc->sc_dev,
161 goto done;
164 if (sc->intr.do_tx) {
165 sc->intr.do_tx = false;
175 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO)
180 device_printf(sc->sc_dev,
182 goto done;
189 * set the done flag here.
191 if (sc->intr.done) {
192 sc->intr.done = false;
193 sc->transfer.done = true;
195 "%s: transfer done\n", __func__);
199 done:
201 "%s: done\n", __func__);
212 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
220 * Allocate GPIOs if provided in the SPI controller block.
225 * and then use GPIOs for the later ones.
231 * And finally, iterating over the cs-gpios list to allocate GPIOs
234 * their properties are (and look for "spi-cs-high".)
243 node = ofw_bus_get_node(sc->sc_dev);
244 for (idx = 0; idx < nitems(sc->cs_pins); idx++) {
245 err = gpio_pin_get_by_ofw_propidx(sc->sc_dev, node,
246 "cs-gpios", idx, &sc->cs_pins[idx]);
248 err = gpio_pin_setflags(sc->cs_pins[idx],
251 device_printf(sc->sc_dev,
262 gpio_pin_set_active(sc->cs_pins[idx], 1);
263 gpio_pin_is_active(sc->cs_pins[idx], &tmp);
266 device_printf(sc->sc_dev,
268 sc->cs_pins[idx] = NULL;
276 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
277 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
280 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
290 sc->sc_dev = dev;
295 sc->hw_version =
296 ofw_bus_search_compatible(dev, compat_data)->ocd_data;
298 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
301 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
303 if (!sc->sc_mem_res) {
310 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
312 if (!sc->sc_irq_res) {
318 ret = bus_setup_intr(dev, sc->sc_irq_res,
320 NULL, qcom_spi_intr, sc, &sc->sc_irq_h);
330 ret = clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core);
336 ret = clk_get_by_ofw_name(dev, 0, "iface", &sc->clk_iface);
344 ret = clk_enable(sc->clk_core);
350 ret = clk_enable(sc->clk_iface);
358 * Read optional spi-max-frequency
360 if (OF_getencprop(ofw_bus_get_node(dev), "spi-max-frequency",
362 sc->config.max_frequency = val;
364 sc->config.max_frequency = SPI_MAX_RATE;
367 * Read optional cs-select
369 if (OF_getencprop(ofw_bus_get_node(dev), "cs-select",
371 sc->config.cs_select = val;
373 sc->config.cs_select = 0;
376 * Read optional num-cs
378 if (OF_getencprop(ofw_bus_get_node(dev), "num-cs",
380 sc->config.num_cs = val;
382 sc->config.num_cs = SPI_NUM_CHIPSELECTS;
399 sc->config.input_block_size,
400 sc->config.output_block_size);
402 sc->config.input_fifo_size,
403 sc->config.output_fifo_size);
423 sc->spibus = device_add_child(dev, "spibus", -1);
425 /* We're done, so shut down the interface clock for now */
426 device_printf(dev, "DONE: shutting down interface clock for now\n");
427 clk_disable(sc->clk_iface);
435 if (sc->sc_irq_h)
436 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
437 if (sc->sc_mem_res)
438 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
439 if (sc->sc_irq_res)
440 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
441 if (sc->clk_core) {
442 clk_disable(sc->clk_core);
443 clk_release(sc->clk_core);
445 if (sc->clk_iface) {
446 clk_disable(sc->clk_iface);
447 clk_release(sc->clk_iface);
450 if (sc->cs_pins[i] != NULL)
451 gpio_pin_release(sc->cs_pins[i]);
453 mtx_destroy(&sc->sc_mtx);
462 * size. The QUP hardware supports doing multi-phase transactions
464 * not yet being done here.
476 device_printf(sc->sc_dev,
489 device_printf(sc->sc_dev,
496 sc->transfer.tx_buf = tx_buf;
497 sc->transfer.tx_len = tx_len;
498 sc->transfer.rx_buf = rx_buf;
499 sc->transfer.rx_len = rx_len;
500 sc->transfer.done = false;
501 sc->transfer.active = false;
504 * Loop until the full transfer set is done.
510 while (sc->transfer.tx_offset < sc->transfer.tx_len) {
513 * it also finishing a sub-transfer and we're
517 sc->transfer.active = false;
522 sc->transfer.tx_offset, sc->transfer.tx_len,
523 sc->transfer.rx_offset, sc->transfer.rx_len);
528 * Otherwise the second sub-transfer that we queue up
534 device_printf(sc->sc_dev,
536 goto done;
539 bzero(&sc->intr, sizeof(sc->intr));
540 sc->transfer.done = false;
544 * sub-transfer will be.
548 device_printf(sc->sc_dev,
551 goto done;
560 device_printf(sc->sc_dev,
563 goto done;
572 device_printf(sc->sc_dev,
575 goto done;
581 device_printf(sc->sc_dev,
584 goto done;
590 device_printf(sc->sc_dev,
593 goto done;
596 ret = qcom_spi_hw_setup_spi_config(sc, sc->state.frequency,
599 device_printf(sc->sc_dev,
602 goto done;
608 device_printf(sc->sc_dev,
611 goto done;
616 device_printf(sc->sc_dev,
619 goto done;
623 * Setup is done; reset the controller and start the PIO
631 sc->transfer.active = true;
634 device_printf(sc->sc_dev,
636 goto done;
644 device_printf(sc->sc_dev,
646 goto done;
654 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO)
659 device_printf(sc->sc_dev,
661 goto done;
669 device_printf(sc->sc_dev,
671 goto done;
677 * sub-transfer) or timeout.
680 while (ret == 0 && sc->transfer.done == false) {
683 ret = msleep(sc, &sc->sc_mtx, 0, "qcom_spi", 0);
686 done:
702 sc->transfer.active = false;
725 cmd->tx_cmd_sz, cmd->rx_cmd_sz,
726 cmd->tx_data_sz, cmd->rx_data_sz);
733 while (sc->sc_busy == true)
734 mtx_sleep(sc, &sc->sc_mtx, 0, "qcom_spi_wait", 0);
739 sc->sc_busy = true;
741 sc->state.cs_high = !! (cs_val & SPIBUS_CS_HIGH);
742 sc->state.frequency = clock_val;
746 * with the driver lock held, as the SPI lock is non-sleepable
757 ret = clk_set_freq(sc->clk_iface, sc->state.frequency, 0);
759 device_printf(sc->sc_dev,
761 sc->state.frequency);
764 clk_enable(sc->clk_iface);
773 device_printf(sc->sc_dev,
775 goto done;
779 if (sc->cs_pins[cs_val & ~SPIBUS_CS_HIGH] == NULL)
787 ret = qcom_spi_transfer_pio_block(sc, mode_val, cmd->tx_cmd,
788 cmd->tx_cmd_sz, cmd->rx_cmd, cmd->rx_cmd_sz);
790 device_printf(sc->sc_dev,
792 goto done;
798 if (cmd->tx_data_sz > 0) {
799 ret = qcom_spi_transfer_pio_block(sc, mode_val, cmd->tx_data,
800 cmd->tx_data_sz, cmd->rx_data, cmd->rx_data_sz);
802 device_printf(sc->sc_dev,
805 goto done;
809 done:
810 /* De-assert GPIO/CS */
811 if (sc->cs_pins[cs_val & ~SPIBUS_CS_HIGH] == NULL)
818 * across a clk API as that's a sleep lock and we're non-sleepable.
823 clk_disable(sc->clk_iface);
827 * We're done; so mark the bus as not busy and wakeup
830 sc->sc_busy = false;
842 bus_generic_detach(sc->sc_dev);
844 if (sc->sc_irq_h)
845 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
847 if (sc->clk_iface) {
848 clk_disable(sc->clk_iface);
849 clk_release(sc->clk_iface);
851 if (sc->clk_core) {
852 clk_disable(sc->clk_core);
853 clk_release(sc->clk_core);
857 if (sc->cs_pins[i] != NULL)
858 gpio_pin_release(sc->cs_pins[i]);
861 if (sc->sc_mem_res)
862 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
863 if (sc->sc_irq_res)
864 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
866 mtx_destroy(&sc->sc_mtx);