Lines Matching +full:0 +full:x170

9 #define ADF_BANK_INT_SRC_SEL_MASK 0x44UL
10 #define ADF_RING_CSR_RING_CONFIG 0x1000
11 #define ADF_RING_CSR_RING_LBASE 0x1040
12 #define ADF_RING_CSR_RING_UBASE 0x1080
13 #define ADF_RING_CSR_RING_HEAD 0x0C0
14 #define ADF_RING_CSR_RING_TAIL 0x100
15 #define ADF_RING_CSR_E_STAT 0x14C
16 #define ADF_RING_CSR_INT_FLAG 0x170
17 #define ADF_RING_CSR_INT_SRCSEL 0x174
18 #define ADF_RING_CSR_INT_COL_CTL 0x180
19 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
20 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
21 #define ADF_RING_CSR_INT_COL_EN 0x17C
22 #define ADF_RING_CSR_ADDR_OFFSET 0x100000
23 #define ADF_RING_BUNDLE_SIZE 0x2000
28 #define ADF_WQM_CSR_RPRESETCTL_RESET BIT(0)
29 #define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3))
30 #define ADF_WQM_CSR_RPRESETSTS_STATUS BIT(0)
33 #define ADF_WQM_CSR_RPRESETCTL_SHIFT 0
36 #define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3))
37 #define ADF_WQM_CSR_RPRESETSTS_SHIFT 0
38 #define ADF_WQM_CSR_RPRESETSTS_MASK (BIT(0))
42 	((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6)
66 		u32 l_base = 0, u_base = 0;                                    \
79 	} while (0)
96 	addr = (u64)l_base & 0x00000000FFFFFFFFULL;  in read_base_gen4()
97 	addr |= (u64)u_base << 32 & 0xFFFFFFFF00000000ULL;  in read_base_gen4()
142 #define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C
160 #define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL
161 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000
162 #define ADF_SSMWDTL_OFFSET 0x54
163 #define ADF_SSMWDTH_OFFSET 0x5C
164 #define ADF_SSMWDTPKEL_OFFSET 0x58
165 #define ADF_SSMWDTPKEH_OFFSET 0x60