Lines Matching full:bank
32 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
34 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD + \
36 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
38 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL + \
40 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
42 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_E_STAT)
43 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
45 (ADF_RING_BUNDLE_SIZE * (bank)) + \
50 read_base(struct resource *csr_base_addr, u32 bank, u32 ring) in read_base() argument
56 (ADF_RING_BUNDLE_SIZE * bank) + in read_base()
59 (ADF_RING_BUNDLE_SIZE * bank) + in read_base()
68 #define READ_CSR_RING_BASE(csr_base_addr, bank, ring) \ argument
69 read_base(csr_base_addr, bank, ring)
71 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
77 (ADF_RING_BUNDLE_SIZE * (bank)) + \
81 (ADF_RING_BUNDLE_SIZE * (bank)) + \
86 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ argument
88 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_HEAD + \
91 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ argument
93 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_RING_TAIL + \
96 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ argument
98 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_FLAG, \
100 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ argument
103 (ADF_RING_BUNDLE_SIZE * (bank)) + \
107 (ADF_RING_BUNDLE_SIZE * (bank)) + \
111 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ argument
113 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_COL_EN, \
115 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ argument
117 (ADF_RING_BUNDLE_SIZE * (bank)) + ADF_RING_CSR_INT_COL_CTL, \
119 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ argument
121 (ADF_RING_BUNDLE_SIZE * (bank)) + \