Lines Matching +full:0 +full:x170

10 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
11 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
12 #define ADF_RING_CSR_RING_CONFIG 0x000
13 #define ADF_RING_CSR_RING_LBASE 0x040
14 #define ADF_RING_CSR_RING_UBASE 0x080
15 #define ADF_RING_CSR_RING_HEAD 0x0C0
16 #define ADF_RING_CSR_RING_TAIL 0x100
17 #define ADF_RING_CSR_E_STAT 0x14C
18 #define ADF_RING_CSR_INT_FLAG 0x170
19 #define ADF_RING_CSR_INT_SRCSEL 0x174
20 #define ADF_RING_CSR_INT_SRCSEL_2 0x178
21 #define ADF_RING_CSR_INT_COL_EN 0x17C
22 #define ADF_RING_CSR_INT_COL_CTL 0x180
23 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
24 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
25 #define ADF_RING_CSR_ADDR_OFFSET 0x0
26 #define ADF_RING_BUNDLE_SIZE 0x1000
28 #define ADF_GEN2_TX_RINGS_MASK 0xFF
31 	(((addr) >> 6) & (GENMASK_ULL(63, 0) << (size)))
62 	addr = (uint64_t)l_base & 0x00000000FFFFFFFFULL;  in read_base()
63 	addr |= (uint64_t)u_base << 32 & 0xFFFFFFFF00000000ULL;  in read_base()
73 		u32 l_base = 0, u_base = 0;                                    \
74 		l_base = (u32)((value)&0xFFFFFFFF);                            \
75 		u_base = (u32)(((value)&0xFFFFFFFF00000000ULL) >> 32);         \
84 	} while (0)
110 	} while (0)
126 #define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190)
127 #define AE2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310)
151 #define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574)
152 #define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578)
153 #define ADF_MAILBOX_BASE_OFFSET 0x20970
156 #define ADF_ARB_OFFSET 0x30000
157 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
158 #define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))
159 #define ADF_ARB_REG_SLOT 0x1000
160 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
183 #define ADF_GEN2_AE_CTX_ENABLES(i) ((i)*0x1000 + 0x20818)
184 #define ADF_GEN2_AE_MISC_CONTROL(i) ((i)*0x1000 + 0x20960)
187 #define ADF_GEN2_UERRSSMSH(i) ((i)*0x4000 + 0x18)
188 #define ADF_GEN2_CERRSSMSH(i) ((i)*0x4000 + 0x10)