Lines Matching +full:layer +full:- +full:base +full:- +full:offset
2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
35 /* TestBase needed to have the 'Multi-Data fetch disable' feature */
39 (bitptr)&(((STRUCT_TYPE *)0)->FEILD)
43 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ argument
44 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
46 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ argument
47 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
49 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ argument
50 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
52 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ argument
53 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
55 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ argument
56 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
57 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF);
59 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ argument
60 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
61 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
62 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
63 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF);
65 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ argument
66 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
67 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
69 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ argument
70 (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
71 (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
72 (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
73 (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
81 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ argument
82 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
83 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF);
85 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ argument
86 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
87 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
88 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
89 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF);
91 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ argument
92 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
93 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
95 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ argument
96 (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
97 (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
98 (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
99 (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
101 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ argument
102 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
104 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ argument
105 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
107 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ argument
108 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
110 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ argument
111 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
561 ---------------------------------------------------------------------
566 /*--------------------------------------------------------------------
729 ---------------------------------------------------------------------
744 * Constants defined for LL Layer starts *
874 /* bit31-28 - request type
875 bit27-16 - reserved
876 bit15-10 - SATA ATAP
877 bit9-8 - direction
878 bit7 - AUTO
879 bit6 - reserved
880 bit5 - EXT
881 bit4 - MSG
882 bit3-0 - Initiator, target or task mode (1 to 8)
898 /* bit definition - AUTO mode */
901 /* request type - not bit difination */
1063 #define AGSA_PHY_MAX_LINK_RATE_MASK 0x0000000F /* bits 0-3 */
1070 #define AGSA_PHY_MODE_MASK 0x00000030 /* bits 4-5 */
1074 /* control spin-up hold */
1087 /* Rate (link-rate) */
1088 #define AGSA_DEV_INFO_RATE_MASK 0x0000000F /* bits 0-3 */
1095 #define AGSA_DEV_INFO_DEV_TYPE_MASK 0x000000E0 /* bits 5-7 */
1186 * Constants defined for LL Layer ends *
1192 * Constants defined for OS Layer starts *
1252 #define OSSA_REGISTER_ACCESS_TIMEOUT 0x02 /* Register access has been timed-out. Thi…
1255 … 0x04 /* Attempted to execute SAS diagnostic command on an invalid/out-of-range PHY. */
1355 #define OSSA_FLASH_UPDATE_OFFSET_ERR 0x03 /**< flag indicates fw flash offset erro…
1392 …DEBUG_PRINT_INVALID_NUMBER 0xFFFFFFFF /**< the number won't be printed by OS layer */
1530 Bits 16-23: Allowable Cipher Mode(ACM)
1632 * Constants defined for OS Layer ends *
1644 * also known as handles, which are used to store OS Layer-specific and
1645 * LL Layer-specific contexts. Only the handle specific to a layer can
1646 * be modified by the layer. The other layer's handle must be returned
1649 * A layer's handle is typically typecast to an instance of a layer-specific
1650 * data structure. The layer can use its handle to point to any data type
1658 void *osData; /**< Pointer-sized value used internally by the OS Layer */
1659 void *sdkData; /**< Pointer-sized value used internally by the LL Layer */
1664 * The agsaRoot_t data structure is used to hold pointer-sized values for
1668 * element is set by the LL Layer in the saHwInitialize()
1669 * function and returned to the OS Layer in the agsaRoot_t data
1677 * It holds pointer-sized values used internally by each of the LL and
1688 * SAS port or SATA port. It holds pointer-sized values used
1691 * When connected to other SAS end-devices or expanders, each instance of
1692 * agsaPortContext_t represents a SAS local narrow-port or
1693 * wide-port.
1705 * initiator. The OS Layer is responsible for allocating and
1706 * managing agsaIORequest_t structures. The LL Layer uses each
1727 bit31-30:reserved
1732 … bit25: delay for SATA Head-of-Line blocking detection timeout
1733 bit24-00:reserved */
1826 * Dword0 Bits 0-11: ALIGN_RATE(ALNR). Align Insertion rate is 2 in every
1830 * Dword1 Bits 0 -11: STP_ALIGN_RATE(STPALNR) Align Insertion rate is 2 in
1834 * Dword2 Bits 0-7: SSP_FRAME_RATE(SSPFRMR) The number of idle DWords
1858 7 : SPC GSM register at [MEMBASE-III SHIFT = 0x00_0000]
1859 8 : SPC GSM register at [MEMBASE-III SHIFT = 0x05_0000]
1860 9 : BDMA GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1861 10: PCIe APP GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1862 11: PCIe PHY GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1863 12: PCIe CORE GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1864 13: OSSP GSM register at [MEMBASE-III SHIFT = 0x02_0000]
1865 14: SSPA GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1866 15: SSPA GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1867 16: HSST GSM register at [MEMBASE-III SHIFT = 0x02_0000]
1868 17: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1869 18: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1870 19: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1871 20: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1872 21: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1873 22: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1874 23: MBIC IOP GSM register at [MEMBASE-III SHIFT = 0x06_0000]
1875 24: MBIC AAP1 GSM register at [MEMBASE-III SHIFT = 0x07_0000]
1876 25: SPBC GSM register at [MEMBASE-III SHIFT = 0x09_0000]
1877 26: GSM GSM register at [MEMBASE-III SHIFT = 0x70_0000]
2054 bit31-19 reserved
2058 bit15-08 maximum number of OQ
2059 bit07-00 maximum number of IQ */
2062 bit07-04 reserved
2063 bit03-00 HDA setting */
2080 bit02-00 state of host and controller
2081 bit16-03 reserved
2082 bit31-16 detail of error based on error state */
2085 bit32 tickCount0; /* tick count in second for internal CPU-0 */
2086 bit32 tickCount1; /* tick count in second for internal CPU-1 */
2087 bit32 tickCount2; /* tick count in second for internal CPU-2 */
2141 bit32 gpioEventLevelChangePart1; /* GPIEVCHANGE (pins 11-0) */
2142 bit32 gpioEventLevelChangePart2; /* GPIEVCHANGE (pins 23-20) */
2143 bit32 gpioEventRisingEdgePart1; /* GPIEVRISE (pins 11-0) */
2144 bit32 gpioEventRisingEdgePart2; /* GPIEVRISE (pins 23-20) */
2145 bit32 gpioEventFallingEdgePart1; /* GPIEVALL (pins 11-0) */
2146 bit32 gpioEventFallingEdgePart2; /* GPIEVALL (pins 23-20) */
2184 * These fields constitute SGPIO configuration register 1, as defined by SFF-8485 spec
2205 /**< b31-b8 reserved */
2206 /**< b16-b19 SSC Disable */
2207 /**< b15-b8 phy analog setup index */
2210 /**< b5-b4 SAS/SATA mode, bit4 - SAS, bit5 - SATA, 11b - Auto mode */
2211 /**< b3-b0 Max. Link Rate, bit0 - 1.5Gb/s, bit1 - 3.0Gb/s,
2212 bit2 - 6.0Gb/s, bit3 - reserved */
2219 * This profile page is used to read or set the SNW-3 PHY capabilities of a
2222 * The format of the 32-bit SNW3 is the same as defined in the SAS 2
2323 bit32 numberOfEventRegClients; /**< Maximum number of OS Layer clients for the event
2332 bit32 fatalErrorInterruptVector:8; /**< 2-9 Fatal Error Interrupt Vector */
2333 bit32 max_MSI_InterruptVectors:8; /**< 10-18 Maximum MSI Interrupt Vectors */
2334 bit32 max_MSIX_InterruptVectors:8; /**< 18-25 Maximum MSIX Interrupt Vectors */
2337 …bit32 hostDirectAccessMode:2; /**< 28-29 HDA mode: 00b - HDA SoftReset, 01b - HDA Normal */
2359 bit32 sallDebugLevel; /**< Low Layer debug level */
2400 bit32 interruptVectorIndex:8; /* MSI/MSI-X interrupt vector index. For MSI, when
2404 For MSI-X, this field is the index to the
2405 MSI-X Table Structure. */
2477 /** \brief specify the controller Event Log for the SAS/SATA LL Layer
2490 /* Log Option - bit3-0 */
2498 /** \brief specify the SAS Diagnostic Parameters for the SAS/SATA LL Layer
2515 /** \brief for the SAS/SATA LL Layer
2527 /** \brief specify the memory allocation requirement for the SAS/SATA LL Layer
2567 /* Bit 6-7: reserved
2568 Bit 4-5: Two-bit flag to specify a SSP/SMP, or directly attached SATA or STP device
2572 Bit 0-3: Connection Rate field when opening the device.
2585 1b: enable SAS TLR (Transport Layer Retry).
2586 0b: disable SAS TLR (Transport Layer Retry).
2592 Bit 2-3: Reserved
2593 Bit 4-11: Zero-based PHY identifier. This field is used only if bits 4-5 in devType_S_Rate are set …
2594 which indicates a directly-attached SATA drive.
2595 Bit 12-15: Reserved
2596 Bit 16-19 : Maximum Connection Number. This field specifies the maximum number of connections that
2608 Bit 22-31: Reserved
2627 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo)
2630 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi)
2633 (((devInfo)->devType_S_Rate & 0xC0) >> 5)
2636 *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32)
2639 *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32)
2659 by SATA-II. This field is valid only
2685 /* b4-7: reserved */
2691 /* b4-7: reserved */
2708 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT)
2711 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT)
2714 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT)
2717 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT)
2720 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT)
2723 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT)
2726 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SATA_BIT) == SA_SASDEV_SATA_BIT)
2743 /** \brief data structure used to pass information about the scatter-gather list to the LL Layer
2746 * of (min, max) = (1, 10), and are 16-byte aligned. Although
2748 * incremented in TBD-byte increments. Refer the hardware
2762 * scatter-gather list (ESGL) to the LL Layer
2765 * extended scatter-gather list (ESGL) to the LL Layer.
2771 * 16-byte aligned. Refer the hardware documentation for more
2832 #define DIF_FLAG_BITS_ACTION 0x00000007 /* 0-2*/
2898 bit16 flag; /**< bit1-0 TLR as SAS specification
2899 bit31-2 reserved */
2942 …bit32 sspInitiatorReqAddrUpper32; /**< The upper 32 bits of the 64-bit physical …
2943 …bit32 sspInitiatorReqAddrLower32; /**< The lower 32 bits of the 64-bit physical …
2957 * length of the data to be received or sent, an offset into the
2959 * scatter-gather buffers.
2966 Bit 0-1: Transport Layer Retry setting for other phase:
2971 Bit 2-3: Transport Layer Retry setting for data phase:
2982 Bits 6-15 : Reserved.
2989 bit32 offset; /**< Specifies the offset into the overall data block member
2996 #define SSP_OPTION_BITS 0x3F /**< bit5-AGR, bit4-RDF bit3,2-RTE, bit1,0-AN */
2997 #define SSP_OPTION_ODS 0x8000 /**< bit15-ODS */
3028 bit32 respBufUpper; /**< Upper 32 bit of physical address of OS Layer
3032 bit32 respBufLower; /**< Lower 32 bit of physical address of OS Layer
3036 bit32 respOption; /**< Bit 0-1: ACK and NAK retry option:
3043 #define RESP_OPTION_BITS 0x3 /** bit0-1 */
3061 bit32 outFrameAddrUpper32; /**< The upper 32 bits of the 64-bit physical
3063 bit32 outFrameAddrLower32; /**< The lower 32 bits of the 64-bit physical
3067 bit32 inFrameAddrUpper32; /**< The upper 32 bits of the 64-bit phsical address
3069 bit32 inFrameAddrLower32; /**< The lower 32 bits of the 64-bit phsical address
3087 Bits 2-31: Reserved
3136 b7-1: reserved
3137 b0: AGSA-STP-CLOSE-CLEAR-AFFILIATION */
3426 * Manual PMC-2080222 or PM8008/PM8009/PM8018 Tachyon SPCv/SPCve/SPCv+ Programmers Manual
3427 * PMC-2091148/PMC-2102373.
3434 bit32 offset; member
3605 #define PCIBAR0 0 /**< PCI Base Address 0 */
3606 #define PCIBAR1 1 /**< PCI Base Address 1 */
3607 #define PCIBAR2 2 /**< PCI Base Address 2 */
3608 #define PCIBAR3 3 /**< PCI Base Address 3 */
3609 #define PCIBAR4 4 /**< PCI Base Address 4 */
3610 #define PCIBAR5 5 /**< PCI Base Address 5 */
3612 /** \brief describe an element of SPC-SPCV converter
3621 bit32 Offset; /* */ member
3820 * The OS Layer Functions Declarations start *
3826 * The OS Layer Functions Declarations end *
3832 * The LL Layer Functions Declarations start *
3882 PM8001/PM8008/PM8009/PM8018 sTSDK Low-Level Architecture Specification
3909 #define OSSA_ENCRYPT_AES_BIST_ERR 0x41 /* Built-In Test Failure */
3910 #define OSSA_ENCRYPT_KWP_BIST_FAILURE 0x42 /* Built-In Test Failed on Key Wrap Engine */
3952 * The LL Layer Functions Declarations end *