Lines Matching +full:bus +full:- +full:range
1 /*-
42 #include <sys/bus.h>
50 #include <machine/bus.h>
71 static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
73 static void generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
97 sc->dev = dev;
108 sc->coherent ? BUS_DMA_COHERENT : 0, /* flags */
110 &sc->dmat);
119 (void)bus_dma_tag_set_domain(sc->dmat, domain);
121 if ((sc->quirks & PCIE_CUSTOM_CONFIG_SPACE_QUIRK) == 0) {
123 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
125 if (sc->res == NULL) {
133 error = bus_map_resource(dev, SYS_RES_MEMORY, sc->res, &req,
139 rman_set_mapping(sc->res, &map);
143 sc->has_pmem = false;
144 sc->pmem_rman.rm_type = RMAN_ARRAY;
147 sc->pmem_rman.rm_descr = strdup(buf, M_DEVBUF);
149 sc->mem_rman.rm_type = RMAN_ARRAY;
152 sc->mem_rman.rm_descr = strdup(buf, M_DEVBUF);
154 sc->io_rman.rm_type = RMAN_ARRAY;
157 sc->io_rman.rm_descr = strdup(buf, M_DEVBUF);
160 error = rman_init(&sc->pmem_rman);
166 error = rman_init(&sc->mem_rman);
172 error = rman_init(&sc->io_rman);
179 phys_base = sc->ranges[tuple].phys_base;
180 pci_base = sc->ranges[tuple].pci_base;
181 size = sc->ranges[tuple].size;
184 continue; /* empty range element */
185 switch (FLAG_TYPE(sc->ranges[tuple].flags)) {
187 sc->has_pmem = true;
190 rm = &sc->pmem_rman;
195 rm = &sc->mem_rman;
200 rm = &sc->io_rman;
213 "failed to set resource for range %d: %d\n", tuple,
217 sc->ranges[tuple].rid = rid;
218 sc->ranges[tuple].res = bus_alloc_resource_any(dev,
220 if (sc->ranges[tuple].res == NULL) {
222 "failed to allocate resource for range %d\n", tuple);
225 error = rman_manage_region(rm, pci_base, pci_base + size - 1);
236 rman_fini(&sc->mem_rman);
238 rman_fini(&sc->pmem_rman);
240 free(__DECONST(char *, sc->io_rman.rm_descr), M_DEVBUF);
241 free(__DECONST(char *, sc->mem_rman.rm_descr), M_DEVBUF);
242 free(__DECONST(char *, sc->pmem_rman.rm_descr), M_DEVBUF);
243 if (sc->res != NULL)
244 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res);
246 bus_dma_tag_destroy(sc->dmat);
263 rid = sc->ranges[tuple].rid;
264 if (sc->ranges[tuple].size == 0) {
265 MPASS(sc->ranges[tuple].res == NULL);
266 continue; /* empty range element */
269 MPASS(rid != -1);
270 switch (FLAG_TYPE(sc->ranges[tuple].flags)) {
278 if (sc->ranges[tuple].res != NULL)
280 sc->ranges[tuple].res);
283 rman_fini(&sc->io_rman);
284 rman_fini(&sc->mem_rman);
285 rman_fini(&sc->pmem_rman);
286 free(__DECONST(char *, sc->io_rman.rm_descr), M_DEVBUF);
287 free(__DECONST(char *, sc->mem_rman.rm_descr), M_DEVBUF);
288 free(__DECONST(char *, sc->pmem_rman.rm_descr), M_DEVBUF);
289 if (sc->res != NULL)
290 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res);
291 bus_dma_tag_destroy(sc->dmat);
297 generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
305 if ((bus < sc->bus_start) || (bus > sc->bus_end))
310 if ((sc->quirks & PCIE_ECAM_DESIGNWARE_QUIRK) && bus == 0 && slot > 0)
313 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
317 data = bus_read_1(sc->res, offset);
320 data = le16toh(bus_read_2(sc->res, offset));
323 data = le32toh(bus_read_4(sc->res, offset));
333 generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
340 if ((bus < sc->bus_start) || (bus > sc->bus_end))
346 offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
350 bus_write_1(sc->res, offset, val);
353 bus_write_2(sc->res, offset, htole16(val));
356 bus_write_4(sc->res, offset, htole32(val));
367 return (31); /* max slots per bus acc. to standard */
379 *result = sc->bus_start;
382 *result = sc->ecam;
406 return (&sc->io_rman);
408 if (sc->has_pmem && (flags & RF_PREFETCHABLE) != 0)
409 return (&sc->pmem_rman);
410 return (&sc->mem_rman);
427 return (pci_domain_release_bus(sc->ecam, child, res));
454 pci_base = sc->ranges[i].pci_base;
455 size = sc->ranges[i].size;
457 continue; /* empty range element */
462 switch (FLAG_TYPE(sc->ranges[i].flags)) {
475 return (&sc->ranges[i]);
484 struct pcie_range *range;
490 range = generic_pcie_containing_range(dev, type, start, start);
491 if (range == NULL)
493 *new_start = start - range->pci_base + range->phys_base;
496 /* No translation for non-memory types */
515 res = pci_domain_alloc_bus(sc->ecam, child, rid, start, end,
544 return (pci_domain_activate_bus(sc->ecam, child, r));
562 return (pci_domain_deactivate_bus(sc->ecam, child, r));
580 return (pci_domain_adjust_bus(sc->ecam, child, res, start,
597 struct pcie_range *range;
621 range = generic_pcie_containing_range(dev, type, rman_get_start(r),
623 if (range == NULL || range->res == NULL)
626 args.offset = start - range->pci_base;
628 return (bus_map_resource(dev, range->res, &args, map));
635 struct pcie_range *range;
649 range = generic_pcie_containing_range(dev, type, rman_get_start(r),
651 if (range == NULL || range->res == NULL)
653 return (bus_unmap_resource(dev, range->res, map));
662 return (sc->dmat);