Lines Matching refs:dinfo
458 struct pci_devinfo *dinfo = NULL;
460 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
461 if ((dinfo->cfg.domain == domain) &&
462 (dinfo->cfg.bus == bus) &&
463 (dinfo->cfg.slot == slot) &&
464 (dinfo->cfg.func == func)) {
469 return (dinfo != NULL ? dinfo->cfg.dev : NULL);
477 struct pci_devinfo *dinfo;
479 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
480 if ((dinfo->cfg.vendor == vendor) &&
481 (dinfo->cfg.device == device)) {
482 return (dinfo->cfg.dev);
492 struct pci_devinfo *dinfo;
494 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
495 if (dinfo->cfg.baseclass == class &&
496 dinfo->cfg.subclass == subclass) {
497 return (dinfo->cfg.dev);
507 struct pci_devinfo *dinfo;
510 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
512 if (from != dinfo->cfg.dev)
517 if (dinfo->cfg.baseclass == class &&
518 dinfo->cfg.subclass == subclass) {
519 return (dinfo->cfg.dev);
1381 struct pci_devinfo *dinfo = device_get_ivars(child);
1382 pcicfgregs *cfg = &dinfo->cfg;
1399 struct pci_devinfo *dinfo = device_get_ivars(child);
1400 pcicfgregs *cfg = &dinfo->cfg;
1420 struct pci_devinfo *dinfo = device_get_ivars(dev);
1421 pcicfgregs *cfg = &dinfo->cfg;
1518 struct pci_devinfo *dinfo = device_get_ivars(child);
1519 pcicfgregs *cfg = &dinfo->cfg;
1601 struct pci_devinfo *dinfo = device_get_ivars(child);
1602 pcicfgregs *cfg = &dinfo->cfg;
1638 struct pci_devinfo *dinfo = device_get_ivars(child);
1639 pcicfgregs *cfg = &dinfo->cfg;
1670 struct pci_devinfo *dinfo = device_get_ivars(dev);
1671 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1687 struct pci_devinfo *dinfo = device_get_ivars(child);
1688 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1712 struct pci_devinfo *dinfo = device_get_ivars(dev);
1713 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1731 struct pci_devinfo *dinfo = device_get_ivars(dev);
1732 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1750 struct pci_devinfo *dinfo = device_get_ivars(dev);
1751 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1768 struct pci_devinfo *dinfo = device_get_ivars(dev);
1769 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1802 struct pci_devinfo *dinfo = device_get_ivars(child);
1803 pcicfgregs *cfg = &dinfo->cfg;
1812 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1829 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1836 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1857 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1863 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1879 rle = resource_list_find(&dinfo->resources,
1917 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1977 struct pci_devinfo *dinfo = device_get_ivars(child);
1978 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2023 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2035 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2074 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
2098 struct pci_devinfo *dinfo = device_get_ivars(child);
2099 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2113 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2128 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2151 struct pci_devinfo *dinfo = device_get_ivars(child);
2152 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2162 struct pci_devinfo *dinfo = device_get_ivars(child);
2163 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2173 struct pci_devinfo *dinfo = device_get_ivars(child);
2174 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2187 struct pci_devinfo *dinfo = device_get_ivars(dev);
2188 struct pcicfg_ht *ht = &dinfo->cfg.ht;
2212 struct pci_devinfo *dinfo = device_get_ivars(dev);
2216 cap = dinfo->cfg.pcie.pcie_location;
2227 struct pci_devinfo *dinfo = device_get_ivars(dev);
2231 cap = dinfo->cfg.pcie.pcie_location;
2243 struct pci_devinfo *dinfo = device_get_ivars(dev);
2247 cap = dinfo->cfg.pcie.pcie_location;
2259 struct pci_devinfo *dinfo = device_get_ivars(dev);
2263 cap = dinfo->cfg.pcie.pcie_location;
2281 struct pci_devinfo *dinfo = device_get_ivars(dev);
2284 cap = dinfo->cfg.pcie.pcie_location;
2297 struct pci_devinfo *dinfo = device_get_ivars(dev);
2300 cap = dinfo->cfg.pcie.pcie_location;
2317 struct pci_devinfo *dinfo = device_get_ivars(dev);
2321 cap = dinfo->cfg.pcie.pcie_location;
2342 struct pci_devinfo *dinfo = device_get_ivars(child);
2343 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2369 struct pci_devinfo *dinfo = device_get_ivars(child);
2370 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2389 struct pci_devinfo *dinfo = device_get_ivars(dev);
2390 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2415 struct pci_devinfo *dinfo = device_get_ivars(dev);
2416 pcicfgregs *cfg = &dinfo->cfg;
2434 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
2442 dinfo->cfg.msi.msi_addr = addr;
2443 dinfo->cfg.msi.msi_data = data;
2584 struct pci_devinfo *dinfo = device_get_ivars(child);
2585 pcicfgregs *cfg = &dinfo->cfg;
2595 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2645 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2703 struct pci_devinfo *dinfo = device_get_ivars(child);
2704 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2722 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2739 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2757 struct pci_devinfo *dinfo = device_get_ivars(child);
2758 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2768 pci_freecfg(struct pci_devinfo *dinfo)
2775 if (dinfo->cfg.vpd.vpd_reg)
2776 vpd_free(&dinfo->cfg.vpd);
2778 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2781 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2782 free(dinfo, M_DEVBUF);
2798 struct pci_devinfo *dinfo = device_get_ivars(child);
2799 pcicfgregs *cfg = &dinfo->cfg;
2870 struct pci_devinfo *dinfo = device_get_ivars(child);
2871 pcicfgregs *cfg = &dinfo->cfg;
2983 pci_print_verbose(struct pci_devinfo *dinfo)
2987 pcicfgregs *cfg = &dinfo->cfg;
3055 struct pci_devinfo *dinfo;
3065 dinfo = device_get_ivars(dev);
3066 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
3131 struct pci_devinfo *dinfo;
3135 dinfo = device_get_ivars(dev);
3136 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
3152 struct pci_devinfo *dinfo;
3155 dinfo = device_get_ivars(dev);
3156 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
3166 struct pci_devinfo *dinfo;
3168 dinfo = device_get_ivars(dev);
3169 return (STAILQ_FIRST(&dinfo->cfg.maps));
3181 struct pci_devinfo *dinfo;
3184 dinfo = device_get_ivars(dev);
3185 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
3189 if ((dinfo->cfg.flags & PCICFG_VF) != 0) {
3192 iov = dinfo->cfg.iov;
3199 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
3208 struct pci_devinfo *dinfo;
3211 dinfo = device_get_ivars(dev);
3216 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
3224 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
3226 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
3233 struct pci_devinfo *dinfo;
3237 dinfo = device_get_ivars(dev);
3238 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
3239 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
3488 struct pci_devinfo *dinfo = device_get_ivars(dev);
3489 pcicfgregs *cfg = &dinfo->cfg;
3530 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
3821 struct pci_devinfo *dinfo;
3827 dinfo = device_get_ivars(child);
3828 cfg = &dinfo->cfg;
3829 rl = &dinfo->resources;
3872 struct pci_devinfo *dinfo;
3876 dinfo = device_get_ivars(dev);
3877 iov = dinfo->cfg.iov;
3908 struct pci_devinfo *dinfo;
3910 dinfo = device_get_ivars(dev);
3912 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
3924 struct pci_devinfo *dinfo;
3934 dinfo = device_get_ivars(dev);
3935 rl = &dinfo->resources;
3939 iov = dinfo->cfg.iov;
3942 if (dinfo->cfg.ea.ea_location == 0)
3945 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
4041 struct pci_devinfo *dinfo;
4048 dinfo = device_get_ivars(dev);
4049 cfg = &dinfo->cfg;
4050 rl = &dinfo->resources;
4129 struct pci_devinfo *dinfo;
4131 dinfo = pci_read_device(pcib, dev, domain, busno, slot, func);
4132 if (dinfo != NULL)
4133 pci_add_child(dev, dinfo);
4135 return (dinfo);
4143 struct pci_devinfo *dinfo;
4155 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0);
4156 if (dinfo != NULL && pci_enable_ari)
4157 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev);
4317 struct pci_devinfo *dinfo = device_get_ivars(dev);
4321 if (dinfo->cfg.pcie.pcie_location == 0)
4351 pci_add_child_clear_aer(device_t dev, struct pci_devinfo *dinfo)
4357 if (dinfo->cfg.pcie.pcie_location != 0 &&
4358 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) {
4359 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4363 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4370 pci_printf(&dinfo->cfg,
4399 pci_printf(&dinfo->cfg,
4416 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4420 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4426 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
4430 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY);
4431 device_set_ivars(dev, dinfo);
4432 resource_list_init(&dinfo->resources);
4433 pci_cfg_save(dev, dinfo, 0);
4434 pci_cfg_restore(dev, dinfo);
4435 pci_print_verbose(dinfo);
4439 pci_child_added(dinfo->cfg.dev);
4442 pci_add_child_clear_aer(dev, dinfo);
4444 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev);
4578 struct pci_devinfo *dinfo;
4582 dinfo = device_get_ivars(child);
4588 pci_cfg_save(child, dinfo, 0);
4604 rle = resource_list_find(&dinfo->resources,
4617 struct pci_devinfo *dinfo;
4623 dinfo = device_get_ivars(child);
4624 pci_cfg_restore(child, dinfo);
4626 pci_cfg_save(child, dinfo, 1);
4635 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
4708 struct pci_devinfo *dinfo;
4720 dinfo = device_get_ivars(child);
4721 pci_print_verbose(dinfo);
4723 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
4724 pci_cfg_restore(child, dinfo);
4735 struct pci_devinfo *dinfo;
4766 dinfo = device_get_ivars(child);
4767 if (dinfo->cfg.msi.msi_alloc > 0) {
4768 if (dinfo->cfg.msi.msi_addr == 0) {
4769 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
4775 dinfo->cfg.msi.msi_addr = addr;
4776 dinfo->cfg.msi.msi_data = data;
4778 if (dinfo->cfg.msi.msi_handlers == 0)
4779 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
4780 dinfo->cfg.msi.msi_data);
4781 dinfo->cfg.msi.msi_handlers++;
4783 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
4785 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
4787 mte = &dinfo->cfg.msix.msix_table[rid - 1];
4789 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
4845 struct pci_devinfo *dinfo;
4866 dinfo = device_get_ivars(child);
4867 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
4870 if (dinfo->cfg.msi.msi_alloc > 0) {
4871 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
4873 if (dinfo->cfg.msi.msi_handlers == 0)
4875 dinfo->cfg.msi.msi_handlers--;
4876 if (dinfo->cfg.msi.msi_handlers == 0)
4879 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
4881 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
4883 mte = &dinfo->cfg.msix.msix_table[rid - 1];
4901 struct pci_devinfo *dinfo;
4905 dinfo = device_get_ivars(child);
4906 rl = &dinfo->resources;
5074 struct pci_devinfo *dinfo;
5077 dinfo = device_get_ivars(child);
5078 rl = &dinfo->resources;
5086 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
5087 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
5088 if (dinfo->cfg.msi.msi_alloc != 0)
5089 pci_printf(&dinfo->cfg, "Device leaked %d MSI "
5090 "vectors\n", dinfo->cfg.msi.msi_alloc);
5092 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X "
5093 "vectors\n", dinfo->cfg.msix.msix_alloc);
5097 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
5099 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
5101 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n");
5103 pci_cfg_save(child, dinfo, 1);
5236 struct pci_devinfo *dinfo;
5239 dinfo = device_get_ivars(child);
5240 cfg = &dinfo->cfg;
5327 struct pci_devinfo *dinfo;
5329 dinfo = device_get_ivars(child);
5333 dinfo->cfg.intpin = value;
5368 struct pci_devinfo *dinfo;
5382 dinfo = STAILQ_FIRST(devlist_head);
5383 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
5384 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
5387 if (dinfo->cfg.dev)
5388 name = device_get_name(dinfo->cfg.dev);
5390 p = &dinfo->conf;
5394 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
5411 struct pci_devinfo *dinfo = device_get_ivars(child);
5412 struct resource_list *rl = &dinfo->resources;
5445 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
5454 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
5525 struct pci_devinfo *dinfo;
5534 dinfo = device_get_ivars(child);
5535 rl = &dinfo->resources;
5536 cfg = &dinfo->cfg;
5597 struct pci_devinfo *dinfo;
5605 dinfo = device_get_ivars(child);
5606 if (dinfo->cfg.flags & PCICFG_VF) {
5627 struct pci_devinfo *dinfo;
5634 dinfo = device_get_ivars(child);
5635 cfg = &dinfo->cfg;
5666 rl = &dinfo->resources;
5673 struct pci_devinfo *dinfo;
5679 dinfo = device_get_ivars(child);
5681 if (dinfo->cfg.flags & PCICFG_VF) {
5704 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
5721 struct pci_devinfo *dinfo;
5727 dinfo = device_get_ivars(child);
5729 if (dinfo->cfg.flags & PCICFG_VF) {
5751 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
5762 struct pci_devinfo *dinfo;
5768 dinfo = device_get_ivars(child);
5769 if (dinfo->cfg.flags & PCICFG_VF) {
5791 struct pci_devinfo *dinfo;
5797 dinfo = device_get_ivars(child);
5798 if (dinfo->cfg.flags & PCICFG_VF) {
5820 struct pci_devinfo *dinfo;
5825 dinfo = device_get_ivars(child);
5826 if (dinfo->cfg.flags & PCICFG_VF) {
5847 struct pci_devinfo *dinfo;
5849 dinfo = device_get_ivars(child);
5850 rl = &dinfo->resources;
5867 pci_printf(&dinfo->cfg,
5881 pci_freecfg(dinfo);
5887 struct pci_devinfo *dinfo;
5894 dinfo = device_get_ivars(child);
5895 rl = &dinfo->resources;
5917 struct pci_devinfo *dinfo = device_get_ivars(child);
5919 return (&dinfo->resources);
5953 struct pci_devinfo *dinfo = device_get_ivars(child);
5954 pcicfgregs *cfg = &dinfo->cfg;
5995 struct pci_devinfo *dinfo = device_get_ivars(child);
5996 pcicfgregs *cfg = &dinfo->cfg;
6015 struct pci_devinfo *dinfo;
6018 dinfo = device_get_ivars(child);
6019 cfg = &dinfo->cfg;
6048 struct pci_devinfo *dinfo = device_get_ivars(child);
6049 pcicfgregs *cfg = &dinfo->cfg;
6132 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
6138 cfg = &dinfo->cfg.pcie;
6168 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
6170 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
6171 dinfo->cfg.pcix.pcix_command, 2);
6175 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
6188 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
6189 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
6190 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
6191 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
6192 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
6193 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
6194 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
6196 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
6197 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
6201 dinfo->cfg.bridge.br_seclat, 1);
6203 dinfo->cfg.bridge.br_subbus, 1);
6205 dinfo->cfg.bridge.br_secbus, 1);
6207 dinfo->cfg.bridge.br_pribus, 1);
6209 dinfo->cfg.bridge.br_control, 2);
6213 dinfo->cfg.bridge.br_seclat, 1);
6215 dinfo->cfg.bridge.br_subbus, 1);
6217 dinfo->cfg.bridge.br_secbus, 1);
6219 dinfo->cfg.bridge.br_pribus, 1);
6221 dinfo->cfg.bridge.br_control, 2);
6226 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE)
6227 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
6232 if (dinfo->cfg.pcie.pcie_location != 0)
6233 pci_cfg_restore_pcie(dev, dinfo);
6234 if (dinfo->cfg.pcix.pcix_location != 0)
6235 pci_cfg_restore_pcix(dev, dinfo);
6238 if (dinfo->cfg.msi.msi_location != 0)
6240 if (dinfo->cfg.msix.msix_location != 0)
6244 if (dinfo->cfg.iov != NULL)
6245 pci_iov_cfg_restore(dev, dinfo);
6250 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
6256 cfg = &dinfo->cfg.pcie;
6288 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
6290 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
6291 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
6295 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
6307 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
6308 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
6309 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
6310 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
6311 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
6312 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
6313 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
6314 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
6315 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
6316 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
6317 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
6318 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
6320 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
6321 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
6322 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
6323 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
6326 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6328 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6330 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6332 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6334 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6338 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6340 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6342 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6344 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6346 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6348 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2);
6349 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2);
6353 if (dinfo->cfg.pcie.pcie_location != 0)
6354 pci_cfg_save_pcie(dev, dinfo);
6356 if (dinfo->cfg.pcix.pcix_location != 0)
6357 pci_cfg_save_pcix(dev, dinfo);
6360 if (dinfo->cfg.iov != NULL)
6361 pci_iov_cfg_save(dev, dinfo);
6406 struct pci_devinfo *dinfo;
6408 dinfo = device_get_ivars(dev);
6409 pci_cfg_save(dev, dinfo, 0);
6415 struct pci_devinfo *dinfo;
6417 dinfo = device_get_ivars(dev);
6418 pci_cfg_restore(dev, dinfo);
6433 struct pci_devinfo *dinfo;
6461 dinfo = device_get_ivars(pcib);
6462 if (dinfo->cfg.pcie.pcie_location != 0 &&
6463 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)
6482 struct pci_devinfo *dinfo = device_get_ivars(dev);
6486 cap = dinfo->cfg.pcie.pcie_location;
6518 struct pci_devinfo *dinfo = device_get_ivars(dev);
6521 cap = dinfo->cfg.pcie.pcie_location;
6530 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 ||
6561 struct pci_devinfo *dinfo = device_get_ivars(dev);
6606 if (dinfo->cfg.pcie.pcie_location != 0) {
6607 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
6612 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
6638 struct pci_devinfo *dinfo = device_get_ivars(dev);
6643 cap = dinfo->cfg.pcie.pcie_location;
6663 pci_printf(&dinfo->cfg,
6689 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n");
6818 pci_print_faulted_dev_name(const struct pci_devinfo *dinfo)
6823 dev = dinfo->cfg.dev;
6824 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus,
6825 dinfo->cfg.slot, dinfo->cfg.func);
6834 struct pci_devinfo *dinfo;
6840 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
6841 dev = dinfo->cfg.dev;
6847 pci_print_faulted_dev_name(dinfo);
6850 if (dinfo->cfg.pcie.pcie_location != 0) {
6852 dinfo->cfg.pcie.pcie_location +
6857 pci_print_faulted_dev_name(dinfo);
6860 dinfo->cfg.pcie.pcie_location +
6869 pci_print_faulted_dev_name(dinfo);
6898 db_clear_pcie_errors(const struct pci_devinfo *dinfo)
6904 dev = dinfo->cfg.dev;
6905 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
6907 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
6922 struct pci_devinfo *dinfo;
6926 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
6927 dev = dinfo->cfg.dev;
6936 if (dinfo->cfg.pcie.pcie_location != 0)
6937 db_clear_pcie_errors(dinfo);