Lines Matching +full:irqs +full:- +full:map +full:- +full:range
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
89 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
236 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
237 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
239 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
240 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
248 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
255 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
256 * or the CMIC-SL (AKA ServerWorks GC_LE).
274 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
318 * HPE Gen 10 VGA has a memory range that can't be allocated in the
325 /* map register information */
326 #define PCI_MAPMEM 0x01 /* memory map */
327 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
328 #define PCI_MAPPORT 0x04 /* port map */
349 "Attempt to allocate a new range for any BARs whose original "
350 "firmware-assigned ranges fail to allocate during the initial device scan.");
363 "Transition from D3 -> D0 on resume.");
368 "Transition from D0 -> D3 on suspend.");
376 "Enable support for MSI-X interrupts");
381 "Rewrite entire MSI-X table when updating MSI-X entries");
385 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
400 "Ignore firmware-assigned resources for BARs.");
404 "Ignore firmware-assigned bus numbers.");
437 for (q = &pci_quirks[0]; q->devid; q++) {
438 if (q->devid == devid && q->type == quirk)
461 if ((dinfo->cfg.domain == domain) &&
462 (dinfo->cfg.bus == bus) &&
463 (dinfo->cfg.slot == slot) &&
464 (dinfo->cfg.func == func)) {
469 return (dinfo != NULL ? dinfo->cfg.dev : NULL);
480 if ((dinfo->cfg.vendor == vendor) &&
481 (dinfo->cfg.device == device)) {
482 return (dinfo->cfg.dev);
495 if (dinfo->cfg.baseclass == class &&
496 dinfo->cfg.subclass == subclass) {
497 return (dinfo->cfg.dev);
512 if (from != dinfo->cfg.dev)
517 if (dinfo->cfg.baseclass == class &&
518 dinfo->cfg.subclass == subclass) {
519 return (dinfo->cfg.dev);
532 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
533 cfg->func);
540 /* return base address of memory or port map */
552 /* return map type of memory or port map */
565 /* return log2 of map size decoded for memory or port map */
593 /* return log2 of map size decided for device ROM */
612 /* return log2 of address range supported by map register */
641 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
645 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
646 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
655 switch (cfg->hdrtype & PCIM_HDRTYPE) {
657 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
658 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
659 cfg->mingnt = REG(PCIR_MINGNT, 1);
660 cfg->maxlat = REG(PCIR_MAXLAT, 1);
661 cfg->nummaps = PCI_MAXMAPS_0;
664 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1);
665 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1);
666 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1);
667 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1);
668 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2);
669 cfg->nummaps = PCI_MAXMAPS_1;
672 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1);
673 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1);
674 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1);
675 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1);
676 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2);
677 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
678 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
679 cfg->nummaps = PCI_MAXMAPS_2;
718 cfg = &devlist_entry->cfg;
720 cfg->domain = d;
721 cfg->bus = b;
722 cfg->slot = s;
723 cfg->func = f;
724 cfg->vendor = vid;
725 cfg->device = did;
726 cfg->cmdreg = REG(PCIR_COMMAND, 2);
727 cfg->statreg = REG(PCIR_STATUS, 2);
728 cfg->baseclass = REG(PCIR_CLASS, 1);
729 cfg->subclass = REG(PCIR_SUBCLASS, 1);
730 cfg->progif = REG(PCIR_PROGIF, 1);
731 cfg->revid = REG(PCIR_REVID, 1);
732 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
733 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
734 cfg->lattimer = REG(PCIR_LATTIMER, 1);
735 cfg->intpin = REG(PCIR_INTPIN, 1);
736 cfg->intline = REG(PCIR_INTLINE, 1);
738 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
739 cfg->hdrtype &= ~PCIM_MFDEV;
740 STAILQ_INIT(&cfg->maps);
742 cfg->iov = NULL;
752 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
753 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
754 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
755 devlist_entry->conf.pc_sel.pc_func = cfg->func;
756 devlist_entry->conf.pc_hdr = cfg->hdrtype;
758 devlist_entry->conf.pc_subvendor = cfg->subvendor;
759 devlist_entry->conf.pc_subdevice = cfg->subdevice;
760 devlist_entry->conf.pc_vendor = cfg->vendor;
761 devlist_entry->conf.pc_device = cfg->device;
763 devlist_entry->conf.pc_class = cfg->baseclass;
764 devlist_entry->conf.pc_subclass = cfg->subclass;
765 devlist_entry->conf.pc_progif = cfg->progif;
766 devlist_entry->conf.pc_revid = cfg->revid;
778 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \
779 cfg->ea.ea_location + (n), w)
789 if (cfg->ea.ea_location == 0)
792 STAILQ_INIT(&cfg->ea.ea_entries);
802 if ((cfg->hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE)
807 eae->eae_cfg_offset = cfg->ea.ea_location + ptr;
819 eae->eae_flags = val;
820 eae->eae_bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET;
835 eae->eae_base = base;
836 eae->eae_max_offset = max_offset;
838 STAILQ_INSERT_TAIL(&cfg->ea.ea_entries, eae, eae_link);
842 cfg->vendor, cfg->device, eae->eae_bei, eae->eae_flags,
843 (uintmax_t)eae->eae_base, (uintmax_t)eae->eae_max_offset);
852 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
853 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
860 switch (cfg->hdrtype & PCIM_HDRTYPE) {
890 if (cfg->pp.pp_cap == 0) {
891 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
892 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
893 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
894 if ((nextptr - ptr) > PCIR_POWER_DATA)
895 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
899 /* Determine HT-specific capability type. */
903 cfg->ht.ht_slave = ptr;
917 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
918 cfg->domain, cfg->bus,
919 cfg->slot, cfg->func,
924 cfg->ht.ht_msimap = ptr;
925 cfg->ht.ht_msictrl = val;
926 cfg->ht.ht_msiaddr = addr;
932 cfg->msi.msi_location = ptr;
933 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
934 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
937 case PCIY_MSIX: /* PCI MSI-X */
938 cfg->msix.msix_location = ptr;
939 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
940 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
943 cfg->msix.msix_table_bar = PCIR_BAR(val &
945 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
947 cfg->msix.msix_pba_bar = PCIR_BAR(val &
949 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
952 cfg->vpd.vpd_reg = ptr;
956 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
959 cfg->subvendor = val & 0xffff;
960 cfg->subdevice = val >> 16;
963 case PCIY_PCIX: /* PCI-X */
965 * Assume we have a PCI-X chipset if we have
966 * at least one PCI-PCI bridge with a PCI-X
968 * PCI-express or HT chipsets might match on
971 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
974 cfg->pcix.pcix_location = ptr;
976 case PCIY_EXPRESS: /* PCI-express */
978 * Assume we have a PCI-express chipset if we have
979 * at least one PCI-express device.
982 cfg->pcie.pcie_location = ptr;
984 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
987 cfg->ea.ea_location = ptr;
998 * slaves. PCI-PCI bridges have their windows enabled via
1001 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
1002 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
1005 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1006 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1007 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
1027 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
1029 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
1030 if (--count < 0)
1034 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
1047 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
1048 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
1049 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1050 if (--count < 0)
1070 /* return 0 and one byte in *data if no read error, -1 else */
1077 if (vrs->bytesinval == 0) {
1078 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
1079 return (-1);
1080 vrs->val = le32toh(reg);
1081 vrs->off += 4;
1082 byte = vrs->val & 0xff;
1083 vrs->bytesinval = 3;
1085 vrs->val = vrs->val >> 8;
1086 byte = vrs->val & 0xff;
1087 vrs->bytesinval--;
1090 vrs->cksum += byte;
1095 /* return 0 on match, -1 and "unget" byte on no match */
1102 return (-1);
1107 vrs->cksum -= data;
1108 vrs->val = (vrs->val << 8) + data;
1109 vrs->bytesinval++;
1110 return (-1);
1113 /* return size if tag matches, -1 on no match, -2 on read error */
1120 return (-1);
1126 return (-2);
1128 return (-2);
1149 /* read VPD keyword and return element size, return -1 on read error */
1156 return (-1);
1158 return (-1);
1160 return (-1);
1194 return (-1);
1210 vrs->cksum -= fixup;
1213 /* fetch one read-only element and return size of heading + data */
1222 cfg = vrs->cfg;
1223 vpd = &cfg->vpd;
1226 return (-1);
1227 vpd->vpd_ros = alloc_buffer(vpd->vpd_ros, sizeof(*vpd->vpd_ros), vpd->vpd_rocnt);
1228 vpd_ros = &vpd->vpd_ros[vpd->vpd_rocnt];
1229 maxsize -= 3;
1230 len = vpd_read_elem_data(vrs, vpd_ros->keyword, &vpd_ros->value, maxsize);
1231 if (vpd_ros->value == NULL)
1232 return (-1);
1233 vpd_ros->len = len;
1234 if (vpd_ros->keyword[0] == 'R' && vpd_ros->keyword[1] == 'V') {
1235 vpd_fixup_cksum(vrs, vpd_ros->value, len);
1236 if (vrs->cksum != 0) {
1238 "invalid VPD checksum %#hhx\n", vrs->cksum);
1239 return (-1);
1242 vpd->vpd_rocnt++;
1256 cfg = vrs->cfg;
1257 vpd = &cfg->vpd;
1260 return (-1);
1261 vpd->vpd_w = alloc_buffer(vpd->vpd_w, sizeof(*vpd->vpd_w), vpd->vpd_wcnt);
1262 if (vpd->vpd_w == NULL) {
1264 return (-1);
1266 vpd_w = &vpd->vpd_w[vpd->vpd_wcnt];
1267 maxsize -= 3;
1268 vpd_w->start = vrs->off + 3 - vrs->bytesinval;
1269 len = vpd_read_elem_data(vrs, vpd_w->keyword, &vpd_w->value, maxsize);
1270 if (vpd_w->value == NULL)
1271 return (-1);
1272 vpd_w->len = len;
1273 vpd->vpd_wcnt++;
1284 free(vpd->vpd_ident, M_DEVBUF);
1285 for (i = 0; i < vpd->vpd_rocnt; i++)
1286 free(vpd->vpd_ros[i].value, M_DEVBUF);
1287 free(vpd->vpd_ros, M_DEVBUF);
1288 vpd->vpd_rocnt = 0;
1289 for (i = 0; i < vpd->vpd_wcnt; i++)
1290 free(vpd->vpd_w[i].value, M_DEVBUF);
1291 free(vpd->vpd_w, M_DEVBUF);
1292 vpd->vpd_wcnt = 0;
1314 /* read VPD ident element - mandatory */
1320 cfg->vpd.vpd_ident = vpd_read_value(&vrs, size);
1321 if (cfg->vpd.vpd_ident == NULL) {
1326 /* read VPD RO elements - mandatory */
1329 pci_printf(cfg, "no read-only VPD data found\n");
1335 pci_printf(cfg, "error accessing read-only VPD data\n");
1336 return (-1);
1338 size -= elem_size;
1342 return (-1);
1344 /* read VPD RW elements - optional */
1346 if (size == -2)
1347 return (-1);
1352 return (-1);
1354 size -= elem_size;
1357 /* read empty END tag - mandatory */
1372 vpd_free(&cfg->vpd);
1373 cfg->vpd.vpd_cached = 1;
1382 pcicfgregs *cfg = &dinfo->cfg;
1384 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1387 *identptr = cfg->vpd.vpd_ident;
1400 pcicfgregs *cfg = &dinfo->cfg;
1403 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1406 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1407 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1408 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1409 *vptr = cfg->vpd.vpd_ros[i].value;
1421 pcicfgregs *cfg = &dinfo->cfg;
1423 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1425 return (&cfg->vpd);
1519 pcicfgregs *cfg = &dinfo->cfg;
1534 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1553 for (cnt = 0; ptr != 0 && cnt < (PCIE_REGMAX - 0x40) / 2; cnt++) {
1602 pcicfgregs *cfg = &dinfo->cfg;
1606 /* Only supported for PCI-express devices. */
1607 if (cfg->pcie.pcie_location == 0)
1639 pcicfgregs *cfg = &dinfo->cfg;
1643 /* Only supported for PCI-express devices. */
1644 if (cfg->pcie.pcie_location == 0)
1665 * Support for MSI-X message interrupts.
1671 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1674 KASSERT(msix->msix_table_len > index, ("bogus index"));
1675 offset = msix->msix_table_offset + index * 16;
1676 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1677 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1678 bus_write_4(msix->msix_table_res, offset + 8, data);
1688 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1699 msix->msix_location + PCIR_MSIX_CTRL,
1700 msix->msix_ctrl & ~PCIM_MSIXCTRL_MSIX_ENABLE, 2);
1705 /* Enable MSI -> HT mapping. */
1713 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1716 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1717 offset = msix->msix_table_offset + index * 16 + 12;
1718 val = bus_read_4(msix->msix_table_res, offset);
1725 bus_write_4(msix->msix_table_res, offset, val);
1732 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1735 KASSERT(msix->msix_table_len > index, ("bogus index"));
1736 offset = msix->msix_table_offset + index * 16 + 12;
1737 val = bus_read_4(msix->msix_table_res, offset);
1744 bus_write_4(msix->msix_table_res, offset, val);
1751 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1754 KASSERT(msix->msix_table_len > index, ("bogus index"));
1755 offset = msix->msix_pba_offset + (index / 32) * 4;
1757 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1761 * Restore MSI-X registers and table during resume. If MSI-X is
1762 * enabled then walk the virtual table to restore the actual MSI-X
1769 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1774 if (msix->msix_alloc > 0) {
1776 for (i = 0; i < msix->msix_msgnum; i++)
1780 for (i = 0; i < msix->msix_table_len; i++) {
1781 mte = &msix->msix_table[i];
1782 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1784 mv = &msix->msix_vectors[mte->mte_vector - 1];
1785 pci_write_msix_entry(dev, i, mv->mv_address,
1786 mv->mv_data);
1790 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1791 msix->msix_ctrl, 2);
1795 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1803 pcicfgregs *cfg = &dinfo->cfg;
1812 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1813 if (rle != NULL && rle->res != NULL)
1817 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1820 /* If MSI-X is blacklisted for this system, fail. */
1824 /* MSI-X capability present? */
1825 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1829 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1830 cfg->msix.msix_table_bar);
1831 if (rle == NULL || rle->res == NULL ||
1832 !(rman_get_flags(rle->res) & RF_ACTIVE))
1834 cfg->msix.msix_table_res = rle->res;
1835 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1836 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1837 cfg->msix.msix_pba_bar);
1838 if (rle == NULL || rle->res == NULL ||
1839 !(rman_get_flags(rle->res) & RF_ACTIVE))
1842 cfg->msix.msix_pba_res = rle->res;
1846 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1847 *count, cfg->msix.msix_msgnum);
1848 max = min(*count, cfg->msix.msix_msgnum);
1857 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1863 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1865 device_printf(child, "using IRQ %ju for MSI-X\n",
1866 rle->start);
1873 * 'run' is true if we are in a range.
1875 device_printf(child, "using IRQs %ju", rle->start);
1876 irq = rle->start;
1879 rle = resource_list_find(&dinfo->resources,
1883 if (rle->start == irq + 1) {
1889 /* Finish previous range. */
1891 printf("-%d", irq);
1895 /* Start new range. */
1896 printf(",%ju", rle->start);
1897 irq = rle->start;
1900 /* Unfinished range? */
1902 printf("-%d", irq);
1903 printf(" for MSI-X\n");
1908 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1912 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1914 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1917 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1918 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1919 cfg->msix.msix_table[i].mte_vector = i + 1;
1922 /* Update control register to enable MSI-X. */
1923 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1924 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1925 cfg->msix.msix_ctrl, 2);
1928 cfg->msix.msix_alloc = actual;
1929 cfg->msix.msix_table_len = actual;
1936 * resources consecutively to the first N messages in the MSI-X table.
1939 * populate the MSI-X table sparsely. This method allows the driver
1945 * maps directly to the MSI-X table in that index 0 in the array
1946 * specifies the vector for the first message in the MSI-X table, etc.
1953 * On successful return, each message with a non-zero vector will have
1955 * 1. Additionally, if any of the IRQs allocated via the previous
1956 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1959 * For example, suppose a driver has a MSI-X table with 6 messages and
1963 * have an MSI-X table of ABC--- (where - means no vector assigned).
1965 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1969 * In any case, the SYS_RES_IRQ rid X will always map to the message
1970 * at MSI-X table index X - 1 and will only be valid if a vector is
1978 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1984 * table can't be bigger than the actual MSI-X table in the
1987 if (count == 0 || count > msix->msix_msgnum)
1992 if (vectors[i] > msix->msix_alloc)
2000 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
2004 used[vectors[i] - 1] = 1;
2005 for (i = 0; i < msix->msix_alloc - 1; i++)
2016 for (i = 0; i < msix->msix_table_len; i++) {
2017 if (msix->msix_table[i].mte_vector == 0)
2019 if (msix->msix_table[i].mte_handlers > 0) {
2023 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2025 if (rle->res != NULL) {
2032 for (i = 0; i < msix->msix_table_len; i++) {
2033 if (msix->msix_table[i].mte_vector == 0)
2035 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2042 free(msix->msix_table, M_DEVBUF);
2043 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
2046 msix->msix_table[i].mte_vector = vectors[i];
2047 msix->msix_table_len = count;
2049 /* Free any unused IRQs and resize the vectors array if necessary. */
2050 j = msix->msix_alloc - 1;
2056 msix->msix_vectors[j].mv_irq);
2057 j--;
2061 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
2063 free(msix->msix_vectors, M_DEVBUF);
2064 msix->msix_vectors = vec;
2065 msix->msix_alloc = j + 1;
2069 /* Map the IRQs onto the rids. */
2073 irq = msix->msix_vectors[vectors[i] - 1].mv_irq;
2074 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
2079 device_printf(child, "Remapped MSI-X IRQs as: ");
2084 printf("---");
2087 msix->msix_vectors[vectors[i] - 1].mv_irq);
2099 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2104 if (msix->msix_alloc == 0)
2108 for (i = 0; i < msix->msix_table_len; i++) {
2109 if (msix->msix_table[i].mte_vector == 0)
2111 if (msix->msix_table[i].mte_handlers > 0)
2113 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2115 if (rle->res != NULL)
2119 /* Update control register to disable MSI-X. */
2120 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
2121 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
2122 msix->msix_ctrl, 2);
2125 for (i = 0; i < msix->msix_table_len; i++) {
2126 if (msix->msix_table[i].mte_vector == 0)
2128 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2130 free(msix->msix_table, M_DEVBUF);
2131 msix->msix_table_len = 0;
2133 /* Release the IRQs. */
2134 for (i = 0; i < msix->msix_alloc; i++)
2136 msix->msix_vectors[i].mv_irq);
2137 free(msix->msix_vectors, M_DEVBUF);
2138 msix->msix_alloc = 0;
2143 * Return the max supported MSI-X messages this device supports.
2152 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2154 if (pci_do_msix && msix->msix_location != 0)
2155 return (msix->msix_msgnum);
2163 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2165 if (pci_do_msix && msix->msix_location != 0)
2166 return (msix->msix_pba_bar);
2167 return (-1);
2174 struct pcicfg_msix *msix = &dinfo->cfg.msix;
2176 if (pci_do_msix && msix->msix_location != 0)
2177 return (msix->msix_table_bar);
2178 return (-1);
2188 struct pcicfg_ht *ht = &dinfo->cfg.ht;
2190 if (!ht->ht_msimap)
2193 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
2194 ht->ht_msiaddr >> 20 == addr >> 20) {
2195 /* Enable MSI -> HT mapping. */
2196 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
2197 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
2198 ht->ht_msictrl, 2);
2201 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
2202 /* Disable MSI -> HT mapping. */
2203 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
2204 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
2205 ht->ht_msictrl, 2);
2216 cap = dinfo->cfg.pcie.pcie_location;
2231 cap = dinfo->cfg.pcie.pcie_location;
2247 cap = dinfo->cfg.pcie.pcie_location;
2263 cap = dinfo->cfg.pcie.pcie_location;
2270 size = (1 << (fls(size) - 1));
2273 val |= (fls(size) - 8) << 12;
2284 cap = dinfo->cfg.pcie.pcie_location;
2300 cap = dinfo->cfg.pcie.pcie_location;
2307 * Adjusts a PCI-e capability register by clearing the bits in mask
2321 cap = dinfo->cfg.pcie.pcie_location;
2343 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2346 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR,
2348 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
2349 pci_write_config(child, msi->msi_location + PCIR_MSI_ADDR_HIGH,
2351 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA_64BIT,
2354 pci_write_config(child, msi->msi_location + PCIR_MSI_DATA, data,
2358 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
2359 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2360 msi->msi_ctrl, 2);
2362 /* Enable MSI -> HT mapping. */
2370 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2372 /* Disable MSI -> HT mapping. */
2376 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
2377 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2378 msi->msi_ctrl, 2);
2390 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2394 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
2395 address = msi->msi_addr;
2396 data = msi->msi_data;
2397 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
2399 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
2400 pci_write_config(dev, msi->msi_location +
2402 pci_write_config(dev, msi->msi_location +
2405 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
2408 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
2416 pcicfgregs *cfg = &dinfo->cfg;
2426 * of MSI IRQs. If we find it, we request updated address and
2429 if (cfg->msi.msi_alloc > 0) {
2431 if (cfg->msi.msi_handlers == 0)
2433 for (i = 0; i < cfg->msi.msi_alloc; i++) {
2434 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
2436 if (rle->start == irq) {
2442 dinfo->cfg.msi.msi_addr = addr;
2443 dinfo->cfg.msi.msi_data = data;
2452 * For MSI-X, we check to see if we have this IRQ. If we do,
2456 if (cfg->msix.msix_alloc > 0) {
2459 for (i = 0; i < cfg->msix.msix_alloc; i++) {
2460 mv = &cfg->msix.msix_vectors[i];
2461 if (mv->mv_irq == irq) {
2466 mv->mv_address = addr;
2467 mv->mv_data = data;
2468 for (j = 0; j < cfg->msix.msix_table_len; j++) {
2469 mte = &cfg->msix.msix_table[j];
2470 if (mte->mte_vector != i + 1)
2472 if (mte->mte_handlers == 0)
2504 * host-PCI bridge at device 0:0:0. In the future, it may become
2516 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2538 * Returns true if the specified device is blacklisted because MSI-X
2540 * MSI-X doesn't either.
2556 * Determine if MSI-X is blacklisted globally on this system. If MSI
2557 * is blacklisted, assume that MSI-X is as well. Check for additional
2558 * chipsets where MSI works but MSI-X does not.
2585 pcicfgregs *cfg = &dinfo->cfg;
2587 int actual, error, i, irqs[32];
2595 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2596 if (rle != NULL && rle->res != NULL)
2600 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2608 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2614 *count, cfg->msi.msi_msgnum);
2617 actual = min(*count, cfg->msi.msi_msgnum);
2629 actual, irqs);
2641 * resources in the irqs[] array, so add new resources
2645 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2646 irqs[i], irqs[i], 1);
2650 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2657 * we are in a range.
2659 device_printf(child, "using IRQs %d", irqs[0]);
2663 if (irqs[i] == irqs[i - 1] + 1) {
2668 /* Finish previous range. */
2670 printf("-%d", irqs[i - 1]);
2674 /* Start new range. */
2675 printf(",%d", irqs[i]);
2678 /* Unfinished range? */
2680 printf("-%d", irqs[actual - 1]);
2686 ctrl = cfg->msi.msi_ctrl;
2688 ctrl |= (ffs(actual) - 1) << 4;
2689 cfg->msi.msi_ctrl = ctrl;
2690 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2693 cfg->msi.msi_alloc = actual;
2694 cfg->msi.msi_handlers = 0;
2704 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2706 int error, i, irqs[32];
2708 /* Try MSI-X first. */
2714 if (msi->msi_alloc == 0)
2716 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2719 if (msi->msi_handlers > 0)
2721 for (i = 0; i < msi->msi_alloc; i++) {
2722 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2724 if (rle->res != NULL)
2726 irqs[i] = rle->start;
2730 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2732 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2733 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2734 msi->msi_ctrl, 2);
2737 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2738 for (i = 0; i < msi->msi_alloc; i++)
2739 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2742 msi->msi_alloc = 0;
2743 msi->msi_addr = 0;
2744 msi->msi_data = 0;
2758 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2760 if (pci_do_msi && msi->msi_location != 0)
2761 return (msi->msi_msgnum);
2775 if (dinfo->cfg.vpd.vpd_reg)
2776 vpd_free(&dinfo->cfg.vpd);
2778 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2788 pci_numdevs--;
2799 pcicfgregs *cfg = &dinfo->cfg;
2803 if (cfg->pp.pp_cap == 0)
2809 * behavior when going from D3 -> D3.
2834 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2841 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2846 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2861 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2871 pcicfgregs *cfg = &dinfo->cfg;
2875 if (cfg->pp.pp_cap != 0) {
2876 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2978 * New style pci driver. Parent device is either a pci-host-bridge or a
2979 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2987 pcicfgregs *cfg = &dinfo->cfg;
2989 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2990 cfg->vendor, cfg->device, cfg->revid);
2992 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2993 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2994 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2995 cfg->mfdev);
2997 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2999 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
3000 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
3001 if (cfg->intpin > 0)
3003 cfg->intpin +'a' -1, cfg->intline);
3004 if (cfg->pp.pp_cap) {
3007 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
3009 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
3010 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
3011 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
3014 if (cfg->msi.msi_location) {
3017 ctrl = cfg->msi.msi_ctrl;
3019 cfg->msi.msi_msgnum,
3020 (cfg->msi.msi_msgnum == 1) ? "" : "s",
3024 if (cfg->msix.msix_location) {
3025 printf("\tMSI-X supports %d message%s ",
3026 cfg->msix.msix_msgnum,
3027 (cfg->msix.msix_msgnum == 1) ? "" : "s");
3028 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
3029 printf("in map 0x%x\n",
3030 cfg->msix.msix_table_bar);
3033 cfg->msix.msix_table_bar,
3034 cfg->msix.msix_pba_bar);
3056 pci_addr_t map, testval;
3061 * The device ROM BAR is special. It is always a 32-bit
3066 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
3067 map = pci_read_config(dev, reg, 4);
3070 pci_write_config(dev, reg, map, 4);
3071 *mapp = map;
3078 map = pci_read_config(dev, reg, 4);
3079 ln2range = pci_maprange(map);
3081 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
3090 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
3099 * and combines the result into a 64-bit value." (section 6.2.5.1)
3114 * the BAR of the low-level console device and when booting verbose,
3117 pci_write_config(dev, reg, map, 4);
3119 pci_write_config(dev, reg + 4, map >> 32, 4);
3122 *mapp = map;
3134 /* The device ROM BAR is always a 32-bit memory BAR. */
3136 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
3139 ln2range = pci_maprange(pm->pm_value);
3140 pci_write_config(dev, pm->pm_reg, base, 4);
3142 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
3143 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
3145 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
3146 pm->pm_reg + 4, 4) << 32;
3156 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
3157 if (pm->pm_reg == reg)
3169 return (STAILQ_FIRST(&dinfo->cfg.maps));
3185 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
3186 !(pm->pm_value & PCIM_BIOS_ENABLE))
3189 if ((dinfo->cfg.flags & PCICFG_VF) != 0) {
3192 iov = dinfo->cfg.iov;
3193 cmd = pci_read_config(iov->iov_pf,
3194 iov->iov_pos + PCIR_SRIOV_CTL, 2);
3199 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
3213 pm->pm_reg = reg;
3214 pm->pm_value = value;
3215 pm->pm_size = size;
3216 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
3217 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
3220 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
3224 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
3226 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
3238 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
3239 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
3242 ln2range = pci_maprange(pm->pm_value);
3243 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
3245 pci_write_config(dev, pm->pm_reg + 4,
3246 pm->pm_value >> 32, 4);
3251 * Add a resource based on a pci map register. Return 1 if the map
3252 * register is a 32bit map register or 2 if it is a 64bit register.
3259 pci_addr_t base, map, testval;
3271 maprange = pci_maprange(pm->pm_value);
3276 pci_read_bar(dev, reg, &map, &testval, NULL);
3277 if (PCI_BAR_MEM(map)) {
3279 if (map & PCIM_BAR_MEM_PREFETCH)
3284 base = pci_mapbase(map);
3290 maprange = pci_maprange(map);
3307 pm = pci_add_bar(dev, reg, map, mapsize);
3309 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
3310 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
3330 if (!force && (basezero || map == testval))
3375 end = base + count - 1;
3381 * so that this resource range is already reserved. The
3392 * this BAR using any available range. The firmware felt
3408 * resource range.
3489 pcicfgregs *cfg = &dinfo->cfg;
3494 if (cfg->intpin == 0)
3501 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
3513 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
3516 irq = cfg->intline;
3524 if (irq != cfg->intline) {
3525 cfg->intline = irq;
3530 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
3670 eec = -1;
3721 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3735 * If the existing bus range is valid, attempt to reserve it
3786 count = end - start + 1;
3793 * rather than reserving the existing range. However,
3828 cfg = &dinfo->cfg;
3829 rl = &dinfo->resources;
3830 switch (cfg->hdrtype & PCIM_HDRTYPE) {
3877 iov = dinfo->cfg.iov;
3879 iov_pos = iov->iov_pos;
3897 return (PCIR_SRIOV_BAR(bei - PCIM_EA_BEI_VF_BAR_0) +
3901 return (-1);
3912 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
3913 if (pci_ea_bei_to_rid(dev, ea->eae_bei) == rid)
3914 return ((ea->eae_flags & PCIM_EA_ENABLE) > 0);
3935 rl = &dinfo->resources;
3939 iov = dinfo->cfg.iov;
3942 if (dinfo->cfg.ea.ea_location == 0)
3945 STAILQ_FOREACH(ea, &dinfo->cfg.ea.ea_entries, eae_link) {
3947 * TODO: Ignore EA-BAR if is not enabled.
3952 * a legacy-BAR mechanism.
3954 if ((ea->eae_flags & PCIM_EA_ENABLE) == 0)
3957 switch ((ea->eae_flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET) {
3976 if ((ea->eae_bei < PCIM_EA_BEI_VF_BAR_0) ||
3977 (ea->eae_bei > PCIM_EA_BEI_VF_BAR_5))
3984 if (((ea->eae_bei < PCIM_EA_BEI_BAR_0) ||
3985 (ea->eae_bei > PCIM_EA_BEI_BAR_5)) &&
3986 (ea->eae_bei != PCIM_EA_BEI_ROM))
3990 rid = pci_ea_bei_to_rid(dev, ea->eae_bei);
3999 start = ea->eae_base;
4000 count = ea->eae_max_offset + 1;
4003 count = count * iov->iov_num_vfs;
4005 end = start + count - 1;
4020 tmp = pci_read_config(dev, ea->eae_cfg_offset, 4);
4022 pci_write_config(dev, ea->eae_cfg_offset, tmp, 4);
4028 ea->eae_flags = pci_read_config(dev, ea->eae_cfg_offset, 4);
4049 cfg = &dinfo->cfg;
4050 rl = &dinfo->resources;
4051 devid = (cfg->device << 16) | cfg->vendor;
4056 /* ATA devices needs special map treatment */
4064 for (i = 0; i < cfg->nummaps;) {
4076 for (q = &pci_quirks[0]; q->devid != 0; q++)
4077 if (q->devid == devid &&
4078 q->type == PCI_QUIRK_UNMAP_REG &&
4079 q->arg1 == PCIR_BAR(i))
4081 if (q->devid != 0) {
4092 for (q = &pci_quirks[0]; q->devid != 0; q++)
4093 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
4094 pci_add_map(bus, dev, q->arg1, rl, force, 0);
4096 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
4098 * Try to re-route interrupts. Sometimes the BIOS or
4100 * If the re-route fails, then just stick with what we
4157 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev);
4296 vf_dinfo->cfg.flags |= PCICFG_VF;
4299 return (vf_dinfo->cfg.dev);
4321 if (dinfo->cfg.pcie.pcie_location == 0)
4357 if (dinfo->cfg.pcie.pcie_location != 0 &&
4358 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT) {
4359 r2 = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4363 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4370 pci_printf(&dinfo->cfg,
4371 "clearing AER UC 0x%08x -> 0x%08x\n",
4399 pci_printf(&dinfo->cfg,
4400 "clearing AER COR 0x%08x -> 0x%08x\n",
4416 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
4420 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
4430 dinfo->cfg.dev = dev = device_add_child(bus, NULL, DEVICE_UNIT_ANY);
4432 resource_list_init(&dinfo->resources);
4439 pci_child_added(dinfo->cfg.dev);
4444 EVENTHANDLER_INVOKE(pci_add_device, dinfo->cfg.dev);
4474 sc->sc_bus = bus_alloc_resource(dev, PCI_RES_BUS, &rid, busno, busno,
4476 if (sc->sc_bus == NULL) {
4483 sc->sc_dma_tag = bus_get_dma_tag(dev);
4519 error = bus_release_resource(dev, PCI_RES_BUS, 0, sc->sc_bus);
4602 * as MSI/MSI-X interrupts are never shared.
4604 rle = resource_list_find(&dinfo->resources,
4606 if (rle != NULL && rle->res != NULL)
4607 (void)bus_suspend_intr(child, rle->res);
4635 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
4636 if (rle != NULL && rle->res != NULL)
4637 (void)bus_resume_intr(child, rle->res);
4723 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
4760 * Check to see if the interrupt is MSI or MSI-X.
4761 * Ask our parent to map the MSI and give
4767 if (dinfo->cfg.msi.msi_alloc > 0) {
4768 if (dinfo->cfg.msi.msi_addr == 0) {
4769 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
4775 dinfo->cfg.msi.msi_addr = addr;
4776 dinfo->cfg.msi.msi_data = data;
4778 if (dinfo->cfg.msi.msi_handlers == 0)
4779 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
4780 dinfo->cfg.msi.msi_data);
4781 dinfo->cfg.msi.msi_handlers++;
4783 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
4784 ("No MSI or MSI-X interrupts allocated"));
4785 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
4786 ("MSI-X index too high"));
4787 mte = &dinfo->cfg.msix.msix_table[rid - 1];
4788 KASSERT(mte->mte_vector != 0, ("no message vector"));
4789 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
4790 KASSERT(mv->mv_irq == rman_get_start(irq),
4792 if (mv->mv_address == 0) {
4793 KASSERT(mte->mte_handlers == 0,
4794 ("MSI-X table entry has handlers, but vector not mapped"));
4799 mv->mv_address = addr;
4800 mv->mv_data = data;
4810 mte->mte_handlers++;
4811 if (mte->mte_handlers == 1) {
4812 pci_enable_msix(child, rid - 1, mv->mv_address,
4813 mv->mv_data);
4814 pci_unmask_msix(child, rid - 1);
4819 * Make sure that INTx is disabled if we are using MSI/MSI-X,
4821 * in which case we "enable" INTx so MSI/MSI-X actually works.
4861 * Check to see if the interrupt is MSI or MSI-X. If so,
4863 * MSI-X message, or disable MSI messages if the count
4867 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
4868 if (rle->res != irq)
4870 if (dinfo->cfg.msi.msi_alloc > 0) {
4871 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
4872 ("MSI-X index too high"));
4873 if (dinfo->cfg.msi.msi_handlers == 0)
4875 dinfo->cfg.msi.msi_handlers--;
4876 if (dinfo->cfg.msi.msi_handlers == 0)
4879 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
4880 ("No MSI or MSI-X interrupts allocated"));
4881 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
4882 ("MSI-X index too high"));
4883 mte = &dinfo->cfg.msix.msix_table[rid - 1];
4884 if (mte->mte_handlers == 0)
4886 mte->mte_handlers--;
4887 if (mte->mte_handlers == 0)
4888 pci_mask_msix(child, rid - 1);
4894 ("%s: generic teardown failed for MSI/MSI-X", __func__));
4906 rl = &dinfo->resources;
4932 {PCIC_OLD, -1, 1, "old"},
4933 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
4934 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
4935 {PCIC_STORAGE, -1, 1, "mass storage"},
4945 {PCIC_NETWORK, -1, 1, "network"},
4951 {PCIC_DISPLAY, -1, 1, "display"},
4955 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
4960 {PCIC_MEMORY, -1, 1, "memory"},
4963 {PCIC_BRIDGE, -1, 1, "bridge"},
4964 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
4965 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
4966 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
4967 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
4968 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
4969 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
4970 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
4971 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
4972 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
4973 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
4978 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
4983 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
4986 {PCIC_INPUTDEV, -1, 1, "input device"},
4992 {PCIC_DOCKING, -1, 1, "docking station"},
4993 {PCIC_PROCESSOR, -1, 1, "processor"},
4994 {PCIC_SERIALBUS, -1, 1, "serial bus"},
5001 {PCIC_WIRELESS, -1, 1, "wireless controller"},
5005 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
5007 {PCIC_SATCOM, -1, 1, "satellite communication"},
5012 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
5015 {PCIC_DASP, -1, 0, "dasp"},
5020 {PCIC_INSTRUMENT, -1, 0, "non-essential instrumentation"},
5047 if (pci_nomatch_tab[i].subclass == -1) {
5078 rl = &dinfo->resources;
5081 * Have to deallocate IRQs before releasing any MSI messages and
5086 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
5087 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
5088 if (dinfo->cfg.msi.msi_alloc != 0)
5089 pci_printf(&dinfo->cfg, "Device leaked %d MSI "
5090 "vectors\n", dinfo->cfg.msi.msi_alloc);
5092 pci_printf(&dinfo->cfg, "Device leaked %d MSI-X "
5093 "vectors\n", dinfo->cfg.msix.msix_alloc);
5097 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
5099 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
5101 pci_printf(&dinfo->cfg, "Device leaked PCI bus numbers\n");
5119 * - devices cannot be listed without a corresponding VENDOR line.
5128 * is set to -1. Returns nonzero at the end of the database.
5140 *device = -1;
5141 *vendor = -1;
5144 left = pci_vendordata_size - (cp - pci_vendordata);
5162 left--;
5166 left--;
5172 left--;
5213 if (vendor != -1) {
5240 cfg = &dinfo->cfg;
5251 *result = cfg->subvendor;
5254 *result = cfg->subdevice;
5257 *result = cfg->vendor;
5260 *result = cfg->device;
5263 *result = (cfg->device << 16) | cfg->vendor;
5266 *result = cfg->baseclass;
5269 *result = cfg->subclass;
5272 *result = cfg->progif;
5275 *result = cfg->revid;
5278 *result = cfg->intpin;
5281 *result = cfg->intline;
5284 *result = cfg->domain;
5287 *result = cfg->bus;
5290 *result = cfg->slot;
5293 *result = cfg->func;
5296 *result = cfg->cmdreg;
5299 *result = cfg->cachelnsz;
5302 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
5303 *result = -1;
5306 *result = cfg->mingnt;
5309 if (cfg->hdrtype != PCIM_HDRTYPE_NORMAL) {
5310 *result = -1;
5313 *result = cfg->maxlat;
5316 *result = cfg->lattimer;
5333 dinfo->cfg.intpin = value;
5363 * List resources based on pci map registers, used for within ddb
5387 if (dinfo->cfg.dev)
5388 name = device_get_name(dinfo->cfg.dev);
5390 p = &dinfo->conf;
5394 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
5396 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
5397 p->pc_sel.pc_func, (p->pc_class << 16) |
5398 (p->pc_subclass << 8) | p->pc_progif,
5399 (p->pc_subdevice << 16) | p->pc_subvendor,
5400 (p->pc_device << 16) | p->pc_vendor,
5401 p->pc_revid, p->pc_hdr);
5412 struct resource_list *rl = &dinfo->resources;
5416 pci_addr_t map, testval;
5428 mapsize = pm->pm_size;
5429 map = pm->pm_value;
5433 * BAR/map is. BARs that read back 0 here are bogus
5439 pci_read_bar(child, *rid, &map, &testval, NULL);
5445 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
5451 pm = pci_add_bar(child, *rid, map, mapsize);
5454 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
5484 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
5509 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
5511 map = rman_get_start(res);
5512 pci_write_bar(child, pm, map);
5535 rl = &dinfo->resources;
5536 cfg = &dinfo->cfg;
5546 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
5547 cfg->msix.msix_alloc > 0))
5555 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
5556 (cfg->intpin != 0))
5562 * PCI-PCI bridge I/O window resources are not BARs.
5566 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
5606 if (dinfo->cfg.flags & PCICFG_VF) {
5635 cfg = &dinfo->cfg;
5638 if (cfg->flags & PCICFG_VF) {
5652 * PCI-PCI bridge I/O window resources are not BARs. For
5655 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE &&
5666 rl = &dinfo->resources;
5681 if (dinfo->cfg.flags & PCICFG_VF) {
5704 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
5729 if (dinfo->cfg.flags & PCICFG_VF) {
5751 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
5769 if (dinfo->cfg.flags & PCICFG_VF) {
5788 struct resource_map_request *argsp, struct resource_map *map)
5795 map));
5798 if (dinfo->cfg.flags & PCICFG_VF) {
5805 map));
5812 return (bus_generic_map_resource(dev, child, r, argsp, map));
5817 struct resource_map *map)
5823 return (bus_generic_unmap_resource(dev, child, r, map));
5826 if (dinfo->cfg.flags & PCICFG_VF) {
5832 return (pci_vf_unmap_mem_resource(dev, child, r, map));
5839 return (bus_generic_unmap_resource(dev, child, r, map));
5850 rl = &dinfo->resources;
5864 if (rle->res) {
5865 if (rman_get_flags(rle->res) & RF_ACTIVE ||
5866 resource_list_busy(rl, rle->type, rle->rid)) {
5867 pci_printf(&dinfo->cfg,
5870 rle->type, rle->rid,
5871 rman_get_start(rle->res));
5872 bus_release_resource(child, rle->type, rle->rid,
5873 rle->res);
5875 resource_list_unreserve(rl, dev, child, rle->type,
5876 rle->rid);
5895 rl = &dinfo->resources;
5900 if (rle->res) {
5901 if (rman_get_flags(rle->res) & RF_ACTIVE ||
5906 type, rid, rman_get_start(rle->res));
5919 return (&dinfo->resources);
5936 tag = sc->sc_dma_tag;
5946 return (sc->sc_dma_tag);
5954 pcicfgregs *cfg = &dinfo->cfg;
5958 * SR-IOV VFs don't implement the VID or DID registers, so we have to
5961 if (cfg->flags & PCICFG_VF) {
5965 return (cfg->device << 16 | cfg->vendor);
5967 return (cfg->vendor);
5969 return (cfg->vendor & 0xff);
5975 /* Note that an unaligned 4-byte read is an error. */
5977 return (cfg->device);
5979 return (cfg->device & 0xff);
5988 cfg->bus, cfg->slot, cfg->func, reg, width));
5996 pcicfgregs *cfg = &dinfo->cfg;
5999 cfg->bus, cfg->slot, cfg->func, reg, val, width);
6019 cfg = &dinfo->cfg;
6021 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
6022 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
6023 cfg->progif);
6049 pcicfgregs *cfg = &dinfo->cfg;
6052 cfg->intpin));
6066 * Accept pciconf-style selectors of either pciD:B:S:F or
6138 cfg = &dinfo->cfg.pcie;
6139 pos = cfg->pcie_location;
6141 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
6143 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
6145 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6146 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
6147 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
6148 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
6150 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6151 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
6152 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
6153 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
6155 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6156 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
6157 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
6160 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
6161 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
6162 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
6170 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
6171 dinfo->cfg.pcix.pcix_command, 2);
6188 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
6189 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
6190 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
6191 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
6192 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
6193 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
6194 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
6196 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
6197 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
6201 dinfo->cfg.bridge.br_seclat, 1);
6203 dinfo->cfg.bridge.br_subbus, 1);
6205 dinfo->cfg.bridge.br_secbus, 1);
6207 dinfo->cfg.bridge.br_pribus, 1);
6209 dinfo->cfg.bridge.br_control, 2);
6213 dinfo->cfg.bridge.br_seclat, 1);
6215 dinfo->cfg.bridge.br_subbus, 1);
6217 dinfo->cfg.bridge.br_secbus, 1);
6219 dinfo->cfg.bridge.br_pribus, 1);
6221 dinfo->cfg.bridge.br_control, 2);
6226 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE)
6227 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
6230 * Restore extended capabilities for PCI-Express and PCI-X
6232 if (dinfo->cfg.pcie.pcie_location != 0)
6234 if (dinfo->cfg.pcix.pcix_location != 0)
6237 /* Restore MSI and MSI-X configurations if they are present. */
6238 if (dinfo->cfg.msi.msi_location != 0)
6240 if (dinfo->cfg.msix.msix_location != 0)
6244 if (dinfo->cfg.iov != NULL)
6256 cfg = &dinfo->cfg.pcie;
6257 pos = cfg->pcie_location;
6259 cfg->pcie_flags = RREG(PCIER_FLAGS);
6261 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
6263 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
6265 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6266 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
6267 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
6268 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
6270 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6271 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
6272 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
6273 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
6275 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
6276 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
6277 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
6280 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
6281 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
6282 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
6290 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
6291 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
6307 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
6308 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
6309 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
6310 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
6311 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
6312 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
6313 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
6314 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
6315 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
6316 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
6317 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
6318 switch (dinfo->cfg.hdrtype & PCIM_HDRTYPE) {
6320 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
6321 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
6322 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
6323 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
6326 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6328 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6330 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6332 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6334 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6338 dinfo->cfg.bridge.br_seclat = pci_read_config(dev,
6340 dinfo->cfg.bridge.br_subbus = pci_read_config(dev,
6342 dinfo->cfg.bridge.br_secbus = pci_read_config(dev,
6344 dinfo->cfg.bridge.br_pribus = pci_read_config(dev,
6346 dinfo->cfg.bridge.br_control = pci_read_config(dev,
6348 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_2, 2);
6349 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_2, 2);
6353 if (dinfo->cfg.pcie.pcie_location != 0)
6356 if (dinfo->cfg.pcix.pcix_location != 0)
6360 if (dinfo->cfg.iov != NULL)
6439 ("%s: non-pci device %s", __func__, device_get_nameunit(dev)));
6442 * Walk the bridge hierarchy until we find a PCI-e root
6443 * port or a non-PCI device.
6456 * PCI-PCI bridge.
6462 if (dinfo->cfg.pcie.pcie_location != 0 &&
6463 dinfo->cfg.pcie.pcie_type == PCIEM_TYPE_ROOT_PORT)
6471 * Wait for pending transactions to complete on a PCI-express function.
6477 * exceeded. If dev is not a PCI-express function, this returns true.
6486 cap = dinfo->cfg.pcie.pcie_location;
6498 max_delay -= 100;
6513 * For non-PCI-express functions this returns 0.
6521 cap = dinfo->cfg.pcie.pcie_location;
6526 * Functions using the 1.x spec use the default timeout range of
6528 * support programmable timeouts also use this range.
6530 if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 ||
6570 s = "Uncorrectable (Non-Fatal)";
6606 if (dinfo->cfg.pcie.pcie_location != 0) {
6607 rs = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
6612 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
6627 * If dev is not a PCI-express function or does not support FLR, this
6632 * PCI-standard registers via pci_save_state() and
6643 cap = dinfo->cfg.pcie.pcie_location;
6654 * which will re-enable busmastering.
6663 pci_printf(&dinfo->cfg,
6668 * Extend the post-FLR delay to cover the maximum
6689 pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n");
6694 * Attempt a power-management reset by cycling the device in/out of D3
6794 while (nelt-- > 0) {
6796 if (id->match_flag_vendor)
6797 match &= vendor == id->vendor;
6798 if (id->match_flag_device)
6799 match &= device == id->device;
6800 if (id->match_flag_subvendor)
6801 match &= subvendor == id->subvendor;
6802 if (id->match_flag_subdevice)
6803 match &= subdevice == id->subdevice;
6804 if (id->match_flag_class)
6805 match &= class == id->class_id;
6806 if (id->match_flag_subclass)
6807 match &= subclass == id->subclass;
6808 if (id->match_flag_revid)
6809 match &= revid == id->revid;
6823 dev = dinfo->cfg.dev;
6824 printf("pci%d:%d:%d:%d", dinfo->cfg.domain, dinfo->cfg.bus,
6825 dinfo->cfg.slot, dinfo->cfg.func);
6841 dev = dinfo->cfg.dev;
6850 if (dinfo->cfg.pcie.pcie_location != 0) {
6852 dinfo->cfg.pcie.pcie_location +
6860 dinfo->cfg.pcie.pcie_location +
6904 dev = dinfo->cfg.dev;
6905 r = pci_read_config(dev, dinfo->cfg.pcie.pcie_location +
6907 pci_write_config(dev, dinfo->cfg.pcie.pcie_location +
6927 dev = dinfo->cfg.dev;
6936 if (dinfo->cfg.pcie.pcie_location != 0)