Lines Matching defs:REG
654 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
657 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
658 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
659 cfg->mingnt = REG(PCIR_MINGNT, 1);
660 cfg->maxlat = REG(PCIR_MAXLAT, 1);
664 cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1);
665 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1);
666 cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1);
667 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1);
668 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2);
672 cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1);
673 cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1);
674 cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1);
675 cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1);
676 cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2);
677 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
678 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
682 #undef REG
689 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
692 vid = REG(PCIR_VENDOR, 2);
696 did = REG(PCIR_DEVICE, 2);
726 cfg->cmdreg = REG(PCIR_COMMAND, 2);
727 cfg->statreg = REG(PCIR_STATUS, 2);
728 cfg->baseclass = REG(PCIR_CLASS, 1);
729 cfg->subclass = REG(PCIR_SUBCLASS, 1);
730 cfg->progif = REG(PCIR_PROGIF, 1);
731 cfg->revid = REG(PCIR_REVID, 1);
732 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
733 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
734 cfg->lattimer = REG(PCIR_LATTIMER, 1);
735 cfg->intpin = REG(PCIR_INTPIN, 1);
736 cfg->intline = REG(PCIR_INTLINE, 1);
747 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
773 #undef REG
778 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, \
795 num_ent = REG(PCIR_EA_NUM_ENT, 2);
810 val = REG(ptr, 4);
815 dw[b] = REG(ptr, 4);
847 #undef REG
852 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
871 nextptr = REG(ptrptr, 1); /* sanity check? */
885 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
888 switch (REG(ptr + PCICAP_ID, 1)) {
891 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
900 val = REG(ptr + PCIR_HT_COMMAND, 2);
910 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
913 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
933 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
939 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
942 val = REG(ptr + PCIR_MSIX_TABLE, 4);
946 val = REG(ptr + PCIR_MSIX_PBA, 4);
958 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
983 val = REG(ptr + PCIER_FLAGS, 2);
1011 /* REG and WREG use carry through to next functions */
1029 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
1034 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
1049 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
1374 #undef REG
4141 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4172 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID)
4174 hdrtype = REG(PCIR_HDRTYPE, 1);
4182 #undef REG
4188 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4215 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID)
4218 hdrtype = REG(PCIR_HDRTYPE, 1);
4224 if (REG(PCIR_VENDOR, 2) == PCIV_INVALID)
4277 #undef REG