Lines Matching +full:low +full:- +full:to +full:- +full:high
1 /*-
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 {"w1-gpio", true},
56 #define OWC_GPIOBUS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
57 #define OWC_GPIOBUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
59 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
61 #define OWC_GPIOBUS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
80 * By default we only bid to attach if specifically added by our parent
88 ofw_bus_search_compatible(dev, compat_data)->ocd_data)
92 device_set_desc(dev, "GPIO one-wire bus");
104 sc->sc_dev = dev;
107 /* Try to configure our pin from fdt data on fdt-based systems. */
109 &sc->sc_pin);
116 * on fdt-based systems).
120 err = gpio_pin_get_by_child_index(dev, OW_PIN, &sc->sc_pin);
124 device_printf(sc->sc_dev,
136 device_add_child(sc->sc_dev, "ow", DEVICE_UNIT_ANY);
152 gpio_pin_release(sc->sc_pin);
165 * below, and let the how be confined to here.
167 #define OUTPIN(sc) gpio_pin_setflags((sc)->sc_pin, GPIO_PIN_OUTPUT)
168 #define INPIN(sc) gpio_pin_setflags((sc)->sc_pin, GPIO_PIN_INPUT)
169 #define GETPIN(sc, bp) gpio_pin_is_active((sc)->sc_pin, (bp))
170 #define LOW(sc) gpio_pin_set_active((sc)->sc_pin, false)
173 * WRITE-ONE (see owll_if.m for timings) From Figure 4-1 AN-937
175 * |<---------tSLOT---->|<-tREC->|
176 * High RRRRM | RRRRRRRRRRRR|RRRRRRRRM
179 * Low MMMMMMM | | | MMMMMM...
180 * |<-tLOW1->| | |
181 * |<------15us--->| |
182 * |<--------60us---->|
193 /* Force low */
195 LOW(sc);
196 DELAY(t->t_low1);
198 /* Allow resistor to float line high */
200 DELAY(t->t_slot - t->t_low1 + t->t_rec);
208 * WRITE-ZERO (see owll_if.m for timings) From Figure 4-2 AN-937
210 * |<---------tSLOT------>|<-tREC->|
211 * High RRRRM | | |RRRRRRRM
214 * Low MMMMMMMMMMMMMMMMMMMMMR MMMMMM...
215 * |<--15us->| | |
216 * |<------60us--->| |
217 * |<-------tLOW0------>|
228 /* Force low */
230 LOW(sc);
231 DELAY(t->t_low0);
233 /* Allow resistor to float line high */
235 DELAY(t->t_slot - t->t_low0 + t->t_rec);
243 * READ-DATA (see owll_if.m for timings) From Figure 4-3 AN-937
245 * |<---------tSLOT------>|<-tREC->|
246 * High RRRRM | rrrrrrrrrrrrrrrRRRRRRRM
249 * Low MMMMMMMSSSSSSSSSSSSSSR MMMMMM...
251 * |<------tRDV---->| |
252 * ->| |<-tRELEASE
254 * r -- allowed to pull high via the resitor when slave writes a 1-bit
268 /* Force low for t_lowr microseconds */
271 LOW(sc);
272 DELAY(t->t_lowr);
275 * Slave is supposed to hold the line low for t_rdv microseconds for 0
276 * and immediately float it high for a 1. This is measured from the
277 * master's pushing the line low.
283 } while (now - then < (t->t_rdv + 2) * SBT_1US && sample == false);
286 if (now - then < t->t_rdv * SBT_1US)
294 } while (now - then < (t->t_slot + t->t_rec) * SBT_1US);
300 * RESET AND PRESENCE PULSE (see owll_if.m for timings) From Figure 4-4 AN-937
302 * |<---------tRSTH------------>|
303 * High RRRM | | RRRRRRRS | RRRR RRM
306 * Low MMMMMMMM MMMMMM| | | SSSSSSSSSS MMMMMM
307 * |<----tRSTL--->| | |<-tPDL---->|
308 * | ->| |<-tR | |
311 * Note: for Regular Speed operations, tRSTL + tR should be less than 960us to
315 * -1 = Bus wiring error (stuck low).
329 * high. Badly wired buses that are missing the required pull up, or
330 * that have a short circuit to ground cause all kinds of mischief when
331 * we try to read them later. Return EIO if the bus is currently low.
336 *bit = -1;
342 /* Force low */
344 LOW(sc);
345 DELAY(t->t_rstl);
347 /* Allow resistor to float line high and then wait for reset pulse */
349 DELAY(t->t_pdh + t->t_pdl / 2);
357 DELAY(t->t_rsth - (t->t_pdh + t->t_pdl / 2)); /* Timing not critical for this one */
361 * window. It should return to high. If it is low, then we have some
366 *bit = -1;