Lines Matching +full:x +full:- +full:rc
1 /*-
46 * The Non-Transparent Bridge (NTB) is a device that allows you to connect
47 * two or more systems using a PCI-e links, providing remote memory access.
89 .desc = "AMD Non-Transparent Bridge"},
99 .desc = "AMD Non-Transparent Bridge"},
109 .desc = "Hygon Non-Transparent Bridge"},
115 PCI_DESCR("AMD Non-Transparent Bridge") },
118 PCI_DESCR("AMD Non-Transparent Bridge") },
121 PCI_DESCR("Hygon Non-Transparent Bridge") }
126 &g_amd_ntb_hw_debug_level, 0, "amd_ntb_hw log level -- higher is verbose");
130 device_printf(ntb->device, __VA_ARGS__); \
161 amd_ntb_printf(1, "%s: conn_type %d\n", __func__, ntb->conn_type); in amd_ntb_port_number()
163 switch (ntb->conn_type) { in amd_ntb_port_number()
172 return (-EINVAL); in amd_ntb_port_number()
190 __func__, pidx, ntb->conn_type); in amd_ntb_peer_port_number()
193 return (-EINVAL); in amd_ntb_peer_port_number()
195 switch (ntb->conn_type) { in amd_ntb_peer_port_number()
204 return (-EINVAL); in amd_ntb_peer_port_number()
218 if (peer_port == -EINVAL || port != peer_port) in amd_ntb_peer_port_idx()
219 return (-EINVAL); in amd_ntb_peer_port_idx()
225 * AMD NTB INTERFACE - LINK ROUTINES
231 amd_ntb_printf(2, "%s: peer_sta 0x%x cntl_sta 0x%x\n", in amd_link_is_up()
232 __func__, ntb->peer_sta, ntb->cntl_sta); in amd_link_is_up()
234 if (!ntb->peer_sta) in amd_link_is_up()
235 return (NTB_LNK_STA_ACTIVE(ntb->cntl_sta)); in amd_link_is_up()
247 return (NTB_LNK_STA_SPEED(ntb->lnk_sta)); in amd_ntb_link_sta_speed()
257 return (NTB_LNK_STA_WIDTH(ntb->lnk_sta)); in amd_ntb_link_sta_width()
280 amd_ntb_printf(1, "%s: int_mask 0x%x conn_type %d\n", in amd_ntb_link_enable()
281 __func__, ntb->int_mask, ntb->conn_type); in amd_ntb_link_enable()
286 ntb->int_mask &= ~AMD_EVENT_INTMASK; in amd_ntb_link_enable()
287 amd_ntb_reg_write(4, AMD_INTMASK_OFFSET, ntb->int_mask); in amd_ntb_link_enable()
289 if (ntb->conn_type == NTB_CONN_SEC) in amd_ntb_link_enable()
296 amd_ntb_printf(1, "%s: ntb_ctl 0x%x\n", __func__, ntb_ctl); in amd_ntb_link_enable()
308 amd_ntb_printf(1, "%s: int_mask 0x%x conn_type %d\n", in amd_ntb_link_disable()
309 __func__, ntb->int_mask, ntb->conn_type); in amd_ntb_link_disable()
314 ntb->int_mask |= AMD_EVENT_INTMASK; in amd_ntb_link_disable()
315 amd_ntb_reg_write(4, AMD_INTMASK_OFFSET, ntb->int_mask); in amd_ntb_link_disable()
317 if (ntb->conn_type == NTB_CONN_SEC) in amd_ntb_link_disable()
324 amd_ntb_printf(1, "%s: ntb_ctl 0x%x\n", __func__, ntb_ctl); in amd_ntb_link_disable()
338 return (ntb->hw_info->mw_count); in amd_ntb_mw_count()
349 if (mw_idx < 0 || mw_idx >= ntb->hw_info->mw_count) in amd_ntb_mw_get_range()
352 bar_info = &ntb->bar_info[ntb->hw_info->bar_start_idx + mw_idx]; in amd_ntb_mw_get_range()
355 *base = bar_info->pbase; in amd_ntb_mw_get_range()
358 *vbase = bar_info->vbase; in amd_ntb_mw_get_range()
361 *align = bar_info->size; in amd_ntb_mw_get_range()
364 *size = bar_info->size; in amd_ntb_mw_get_range()
372 * memory window 0 use a 32-bit bar. The remaining in amd_ntb_mw_get_range()
373 * cases all use 64-bit bar. in amd_ntb_mw_get_range()
375 if ((mw_idx == 0) && (ntb->hw_info->quirks & QUIRK_MW0_32BIT)) in amd_ntb_mw_get_range()
390 if (mw_idx < 0 || mw_idx >= ntb->hw_info->mw_count) in amd_ntb_mw_set_trans()
393 bar_info = &ntb->bar_info[ntb->hw_info->bar_start_idx + mw_idx]; in amd_ntb_mw_set_trans()
396 if (size > bar_info->size) { in amd_ntb_mw_set_trans()
397 amd_ntb_printf(0, "%s: size 0x%jx greater than mw_size 0x%jx\n", in amd_ntb_mw_set_trans()
398 __func__, (uintmax_t)size, (uintmax_t)bar_info->size); in amd_ntb_mw_set_trans()
402 amd_ntb_printf(1, "%s: mw %d mw_size 0x%jx size 0x%jx base %p\n", in amd_ntb_mw_set_trans()
403 __func__, mw_idx, (uintmax_t)bar_info->size, in amd_ntb_mw_set_trans()
404 (uintmax_t)size, (void *)bar_info->pci_bus_handle); in amd_ntb_mw_set_trans()
412 amd_ntb_peer_reg_write(8, bar_info->xlat_off, (uint64_t)addr); in amd_ntb_mw_set_trans()
413 amd_ntb_printf(0, "%s: mw %d xlat_off 0x%x cur_val 0x%jx addr %p\n", in amd_ntb_mw_set_trans()
414 __func__, mw_idx, bar_info->xlat_off, in amd_ntb_mw_set_trans()
415 amd_ntb_peer_reg_read(8, bar_info->xlat_off), (void *)addr); in amd_ntb_mw_set_trans()
421 * memory window 0 use a 32-bit bar. The remaining in amd_ntb_mw_set_trans()
422 * cases all use 64-bit bar. in amd_ntb_mw_set_trans()
424 if ((mw_idx == 0) && (ntb->hw_info->quirks & QUIRK_MW0_32BIT)) { in amd_ntb_mw_set_trans()
425 amd_ntb_reg_write(4, bar_info->limit_off, (uint32_t)size); in amd_ntb_mw_set_trans()
426 amd_ntb_printf(1, "%s: limit_off 0x%x cur_val 0x%x limit 0x%x\n", in amd_ntb_mw_set_trans()
427 __func__, bar_info->limit_off, in amd_ntb_mw_set_trans()
428 amd_ntb_peer_reg_read(4, bar_info->limit_off), in amd_ntb_mw_set_trans()
431 amd_ntb_reg_write(8, bar_info->limit_off, (uint64_t)size); in amd_ntb_mw_set_trans()
432 amd_ntb_printf(1, "%s: limit_off 0x%x cur_val 0x%jx limit 0x%jx\n", in amd_ntb_mw_set_trans()
433 __func__, bar_info->limit_off, in amd_ntb_mw_set_trans()
434 amd_ntb_peer_reg_read(8, bar_info->limit_off), in amd_ntb_mw_set_trans()
448 if (mw_idx < 0 || mw_idx >= ntb->hw_info->mw_count) in amd_ntb_mw_clear_trans()
459 int rc; in amd_ntb_mw_set_wc() local
461 if (mw_idx < 0 || mw_idx >= ntb->hw_info->mw_count) in amd_ntb_mw_set_wc()
464 bar_info = &ntb->bar_info[ntb->hw_info->bar_start_idx + mw_idx]; in amd_ntb_mw_set_wc()
465 if (mode == bar_info->map_mode) in amd_ntb_mw_set_wc()
468 rc = pmap_change_attr((vm_offset_t)bar_info->vbase, bar_info->size, mode); in amd_ntb_mw_set_wc()
469 if (rc == 0) in amd_ntb_mw_set_wc()
470 bar_info->map_mode = mode; in amd_ntb_mw_set_wc()
472 return (rc); in amd_ntb_mw_set_wc()
483 if (mw_idx < 0 || mw_idx >= ntb->hw_info->mw_count) in amd_ntb_mw_get_wc()
486 bar_info = &ntb->bar_info[ntb->hw_info->bar_start_idx + mw_idx]; in amd_ntb_mw_get_wc()
487 *mode = bar_info->map_mode; in amd_ntb_mw_get_wc()
500 amd_ntb_printf(1, "%s: db_count 0x%x\n", __func__, in amd_ntb_db_vector_count()
501 ntb->hw_info->db_count); in amd_ntb_db_vector_count()
503 return (ntb->hw_info->db_count); in amd_ntb_db_vector_count()
511 amd_ntb_printf(1, "%s: db_valid_mask 0x%x\n", in amd_ntb_db_valid_mask()
512 __func__, ntb->db_valid_mask); in amd_ntb_db_valid_mask()
514 return (ntb->db_valid_mask); in amd_ntb_db_valid_mask()
522 amd_ntb_printf(1, "%s: vector %d db_count 0x%x db_valid_mask 0x%x\n", in amd_ntb_db_vector_mask()
523 __func__, vector, ntb->hw_info->db_count, ntb->db_valid_mask); in amd_ntb_db_vector_mask()
525 if (vector < 0 || vector >= ntb->hw_info->db_count) in amd_ntb_db_vector_mask()
528 return (ntb->db_valid_mask & (1 << vector)); in amd_ntb_db_vector_mask()
539 amd_ntb_printf(1, "%s: dbstat_off 0x%jx\n", __func__, dbstat_off); in amd_ntb_db_read()
549 amd_ntb_printf(1, "%s: db_bits 0x%jx\n", __func__, db_bits); in amd_ntb_db_clear()
559 amd_ntb_printf(1, "%s: db_mask 0x%x db_bits 0x%jx\n", in amd_ntb_db_set_mask()
560 __func__, ntb->db_mask, db_bits); in amd_ntb_db_set_mask()
562 ntb->db_mask |= db_bits; in amd_ntb_db_set_mask()
563 amd_ntb_reg_write(2, AMD_DBMASK_OFFSET, ntb->db_mask); in amd_ntb_db_set_mask()
573 amd_ntb_printf(1, "%s: db_mask 0x%x db_bits 0x%jx\n", in amd_ntb_db_clear_mask()
574 __func__, ntb->db_mask, db_bits); in amd_ntb_db_clear_mask()
576 ntb->db_mask &= ~db_bits; in amd_ntb_db_clear_mask()
577 amd_ntb_reg_write(2, AMD_DBMASK_OFFSET, ntb->db_mask); in amd_ntb_db_clear_mask()
586 amd_ntb_printf(1, "%s: db_bits 0x%jx\n", __func__, db_bits); in amd_ntb_peer_db_set()
598 amd_ntb_printf(1, "%s: spad_count 0x%x\n", __func__, in amd_ntb_spad_count()
599 ntb->spad_count); in amd_ntb_spad_count()
601 return (ntb->spad_count); in amd_ntb_spad_count()
612 if (idx < 0 || idx >= ntb->spad_count) in amd_ntb_spad_read()
615 offset = ntb->self_spad + (idx << 2); in amd_ntb_spad_read()
617 amd_ntb_printf(2, "%s: offset 0x%x val 0x%x\n", __func__, offset, *val); in amd_ntb_spad_read()
630 if (idx < 0 || idx >= ntb->spad_count) in amd_ntb_spad_write()
633 offset = ntb->self_spad + (idx << 2); in amd_ntb_spad_write()
635 amd_ntb_printf(2, "%s: offset 0x%x val 0x%x\n", __func__, offset, val); in amd_ntb_spad_write()
645 for (i = 0; i < ntb->spad_count; i++) in amd_ntb_spad_clear()
646 amd_ntb_spad_write(ntb->device, i, 0); in amd_ntb_spad_clear()
657 if (idx < 0 || idx >= ntb->spad_count) in amd_ntb_peer_spad_read()
660 offset = ntb->peer_spad + (idx << 2); in amd_ntb_peer_spad_read()
662 amd_ntb_printf(2, "%s: offset 0x%x val 0x%x\n", __func__, offset, *val); in amd_ntb_peer_spad_read()
675 if (idx < 0 || idx >= ntb->spad_count) in amd_ntb_peer_spad_write()
678 offset = ntb->peer_spad + (idx << 2); in amd_ntb_peer_spad_write()
680 amd_ntb_printf(2, "%s: offset 0x%x val 0x%x\n", __func__, offset, val); in amd_ntb_peer_spad_write()
693 int rc = 0; in amd_ntb_hw_info_handler() local
697 return (sb->s_error); in amd_ntb_hw_info_handler()
701 (ntb->conn_type == NTB_CONN_PRI)? "PRIMARY" : "SECONDARY"); in amd_ntb_hw_info_handler()
702 sbuf_printf(sb, "AMD LNK STA: 0x%#06x\n", ntb->lnk_sta); in amd_ntb_hw_info_handler()
708 sbuf_printf(sb, "AMD Link Speed: PCI-E Gen %u\n", in amd_ntb_hw_info_handler()
709 NTB_LNK_STA_SPEED(ntb->lnk_sta)); in amd_ntb_hw_info_handler()
710 sbuf_printf(sb, "AMD Link Width: PCI-E Width %u\n", in amd_ntb_hw_info_handler()
711 NTB_LNK_STA_WIDTH(ntb->lnk_sta)); in amd_ntb_hw_info_handler()
715 ntb->hw_info->mw_count); in amd_ntb_hw_info_handler()
717 ntb->spad_count); in amd_ntb_hw_info_handler()
719 ntb->hw_info->db_count); in amd_ntb_hw_info_handler()
720 sbuf_printf(sb, "AMD MSI-X vec count: %d\n\n", in amd_ntb_hw_info_handler()
721 ntb->msix_vec_count); in amd_ntb_hw_info_handler()
722 sbuf_printf(sb, "AMD Doorbell valid mask: 0x%x\n", in amd_ntb_hw_info_handler()
723 ntb->db_valid_mask); in amd_ntb_hw_info_handler()
724 sbuf_printf(sb, "AMD Doorbell Mask: 0x%x\n", in amd_ntb_hw_info_handler()
726 sbuf_printf(sb, "AMD Doorbell: 0x%x\n", in amd_ntb_hw_info_handler()
729 sbuf_printf(sb, "AMD XLAT1: 0x%jx\n", in amd_ntb_hw_info_handler()
731 sbuf_printf(sb, "AMD XLAT23: 0x%jx\n", in amd_ntb_hw_info_handler()
733 sbuf_printf(sb, "AMD XLAT45: 0x%jx\n", in amd_ntb_hw_info_handler()
735 sbuf_printf(sb, "AMD LMT1: 0x%x\n", in amd_ntb_hw_info_handler()
737 sbuf_printf(sb, "AMD LMT23: 0x%jx\n", in amd_ntb_hw_info_handler()
739 sbuf_printf(sb, "AMD LMT45: 0x%jx\n", in amd_ntb_hw_info_handler()
742 rc = sbuf_finish(sb); in amd_ntb_hw_info_handler()
744 return (rc); in amd_ntb_hw_info_handler()
753 ctx = device_get_sysctl_ctx(ntb->device); in amd_ntb_sysctl_init()
754 globals = SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)); in amd_ntb_sysctl_init()
772 if (reg == ntb->cntl_sta) in amd_ntb_poll_link()
775 amd_ntb_printf(0, "%s: SIDEINFO reg_val = 0x%x cntl_sta 0x%x\n", in amd_ntb_poll_link()
776 __func__, fullreg, ntb->cntl_sta); in amd_ntb_poll_link()
778 ntb->cntl_sta = reg; in amd_ntb_poll_link()
780 stat = pci_read_config(ntb->device, AMD_LINK_STATUS_OFFSET, 4); in amd_ntb_poll_link()
782 amd_ntb_printf(0, "%s: LINK_STATUS stat = 0x%x lnk_sta 0x%x.\n", in amd_ntb_poll_link()
783 __func__, stat, ntb->lnk_sta); in amd_ntb_poll_link()
785 ntb->lnk_sta = stat; in amd_ntb_poll_link()
796 ntb_link_event(ntb->device); in amd_link_hb()
799 callout_reset(&ntb->hb_timer, AMD_LINK_HB_TIMEOUT, in amd_link_hb()
802 callout_reset(&ntb->hb_timer, (AMD_LINK_HB_TIMEOUT * 10), in amd_link_hb()
810 if (vec < ntb->hw_info->db_count) in amd_ntb_interrupt()
811 ntb_db_event(ntb->device, vec); in amd_ntb_interrupt()
821 amd_ntb_interrupt(nvec->ntb, nvec->num); in amd_ntb_vec_isr()
827 /* If we couldn't set up MSI-X, we only have the one vector. */ in amd_ntb_irq_isr()
862 int flags = 0, rc = 0; in amd_ntb_setup_isr() local
871 ntb->int_info[i].rid = i; in amd_ntb_setup_isr()
873 ntb->int_info[i].rid = i + 1; in amd_ntb_setup_isr()
875 ntb->int_info[i].res = bus_alloc_resource_any(ntb->device, in amd_ntb_setup_isr()
876 SYS_RES_IRQ, &ntb->int_info[i].rid, flags); in amd_ntb_setup_isr()
877 if (ntb->int_info[i].res == NULL) { in amd_ntb_setup_isr()
882 ntb->int_info[i].tag = NULL; in amd_ntb_setup_isr()
883 ntb->allocated_interrupts++; in amd_ntb_setup_isr()
886 rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, in amd_ntb_setup_isr()
888 ntb, &ntb->int_info[i].tag); in amd_ntb_setup_isr()
890 rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, in amd_ntb_setup_isr()
892 &ntb->msix_vec[i], &ntb->int_info[i].tag); in amd_ntb_setup_isr()
895 if (rc != 0) { in amd_ntb_setup_isr()
909 ntb->msix_vec = malloc(max_vectors * sizeof(*ntb->msix_vec), M_AMD_NTB, in amd_ntb_create_msix_vec()
913 ntb->msix_vec[i].num = i; in amd_ntb_create_msix_vec()
914 ntb->msix_vec[i].ntb = ntb; in amd_ntb_create_msix_vec()
923 if (ntb->msix_vec_count) { in amd_ntb_free_msix_vec()
924 pci_release_msi(ntb->device); in amd_ntb_free_msix_vec()
925 ntb->msix_vec_count = 0; in amd_ntb_free_msix_vec()
928 if (ntb->msix_vec != NULL) { in amd_ntb_free_msix_vec()
929 free(ntb->msix_vec, M_AMD_NTB); in amd_ntb_free_msix_vec()
930 ntb->msix_vec = NULL; in amd_ntb_free_msix_vec()
939 int rc = 0; in amd_ntb_init_isr() local
941 ntb->db_mask = ntb->db_valid_mask; in amd_ntb_init_isr()
943 rc = amd_ntb_create_msix_vec(ntb, ntb->hw_info->msix_vector_count); in amd_ntb_init_isr()
944 if (rc != 0) { in amd_ntb_init_isr()
945 amd_ntb_printf(0, "Error creating msix vectors: %d\n", rc); in amd_ntb_init_isr()
950 * Check the number of MSI-X message supported by the device. in amd_ntb_init_isr()
951 * Minimum necessary MSI-X message count should be equal to db_count. in amd_ntb_init_isr()
953 supported_vectors = pci_msix_count(ntb->device); in amd_ntb_init_isr()
954 num_vectors = MIN(supported_vectors, ntb->hw_info->db_count); in amd_ntb_init_isr()
955 if (num_vectors < ntb->hw_info->db_count) { in amd_ntb_init_isr()
957 supported_vectors, ntb->hw_info->db_count); in amd_ntb_init_isr()
962 /* Allocate the necessary number of MSI-x messages */ in amd_ntb_init_isr()
963 rc = pci_alloc_msix(ntb->device, &num_vectors); in amd_ntb_init_isr()
964 if (rc != 0) { in amd_ntb_init_isr()
965 amd_ntb_printf(0, "Error allocating msix vectors: %d\n", rc); in amd_ntb_init_isr()
970 if (num_vectors < ntb->hw_info->db_count) { in amd_ntb_init_isr()
971 amd_ntb_printf(0, "Allocated only %d MSI-X\n", num_vectors); in amd_ntb_init_isr()
974 * Else set ntb->hw_info->db_count = ntb->msix_vec_count = in amd_ntb_init_isr()
982 free(ntb->msix_vec, M_AMD_NTB); in amd_ntb_init_isr()
983 ntb->msix_vec = NULL; in amd_ntb_init_isr()
984 pci_release_msi(ntb->device); in amd_ntb_init_isr()
986 rc = pci_alloc_msi(ntb->device, &num_vectors); in amd_ntb_init_isr()
987 if (rc != 0) { in amd_ntb_init_isr()
988 amd_ntb_printf(0, "Error allocating msix vectors: %d\n", rc); in amd_ntb_init_isr()
994 ntb->hw_info->db_count = ntb->msix_vec_count = num_vectors; in amd_ntb_init_isr()
998 ntb->hw_info->db_count = 1; in amd_ntb_init_isr()
999 ntb->msix_vec_count = 0; in amd_ntb_init_isr()
1003 __func__, ntb->hw_info->db_count, ntb->msix_vec_count, (int)msi, (int)intx); in amd_ntb_init_isr()
1005 rc = amd_ntb_setup_isr(ntb, num_vectors, msi, intx); in amd_ntb_init_isr()
1006 if (rc != 0) { in amd_ntb_init_isr()
1007 amd_ntb_printf(0, "Error setting up isr: %d\n", rc); in amd_ntb_init_isr()
1011 return (rc); in amd_ntb_init_isr()
1021 ntb->db_mask = ntb->db_valid_mask; in amd_ntb_deinit_isr()
1022 amd_ntb_reg_write(4, AMD_DBMASK_OFFSET, ntb->db_mask); in amd_ntb_deinit_isr()
1024 for (i = 0; i < ntb->allocated_interrupts; i++) { in amd_ntb_deinit_isr()
1025 current_int = &ntb->int_info[i]; in amd_ntb_deinit_isr()
1026 if (current_int->tag != NULL) in amd_ntb_deinit_isr()
1027 bus_teardown_intr(ntb->device, current_int->res, in amd_ntb_deinit_isr()
1028 current_int->tag); in amd_ntb_deinit_isr()
1030 if (current_int->res != NULL) in amd_ntb_deinit_isr()
1031 bus_release_resource(ntb->device, SYS_RES_IRQ, in amd_ntb_deinit_isr()
1032 rman_get_rid(current_int->res), current_int->res); in amd_ntb_deinit_isr()
1054 ntb->db_valid_mask = (1ull << ntb->hw_info->db_count) - 1; in amd_ntb_init_dev()
1055 mtx_init(&ntb->db_mask_lock, "amd ntb db bits", NULL, MTX_SPIN); in amd_ntb_init_dev()
1057 switch (ntb->conn_type) { in amd_ntb_init_dev()
1060 ntb->spad_count >>= 1; in amd_ntb_init_dev()
1062 if (ntb->conn_type == NTB_CONN_PRI) { in amd_ntb_init_dev()
1063 ntb->self_spad = 0; in amd_ntb_init_dev()
1064 ntb->peer_spad = 0x20; in amd_ntb_init_dev()
1066 ntb->self_spad = 0x20; in amd_ntb_init_dev()
1067 ntb->peer_spad = 0; in amd_ntb_init_dev()
1070 callout_init(&ntb->hb_timer, 1); in amd_ntb_init_dev()
1071 callout_reset(&ntb->hb_timer, AMD_LINK_HB_TIMEOUT, in amd_ntb_init_dev()
1078 ntb->conn_type); in amd_ntb_init_dev()
1082 ntb->int_mask = AMD_EVENT_INTMASK; in amd_ntb_init_dev()
1083 amd_ntb_reg_write(4, AMD_INTMASK_OFFSET, ntb->int_mask); in amd_ntb_init_dev()
1091 int rc = 0; in amd_ntb_init() local
1093 ntb->conn_type = amd_ntb_get_topo(ntb); in amd_ntb_init()
1095 (ntb->conn_type == NTB_CONN_PRI)? "PRIMARY" : "SECONDARY"); in amd_ntb_init()
1097 rc = amd_ntb_init_dev(ntb); in amd_ntb_init()
1098 if (rc != 0) in amd_ntb_init()
1099 return (rc); in amd_ntb_init()
1101 rc = amd_ntb_init_isr(ntb); in amd_ntb_init()
1102 if (rc != 0) in amd_ntb_init()
1103 return (rc); in amd_ntb_init()
1112 amd_ntb_printf(0, "Mapped BAR%d v:[%p-%p] p:[0x%jx-0x%jx] (0x%jx bytes) (%s)\n", in print_map_success()
1113 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, in print_map_success()
1114 (char *)bar->vbase + bar->size - 1, (uintmax_t)bar->pbase, in print_map_success()
1115 (uintmax_t)(bar->pbase + bar->size - 1), (uintmax_t)bar->size, kind); in print_map_success()
1121 bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); in save_bar_parameters()
1122 bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); in save_bar_parameters()
1123 bar->pbase = rman_get_start(bar->pci_resource); in save_bar_parameters()
1124 bar->size = rman_get_size(bar->pci_resource); in save_bar_parameters()
1125 bar->vbase = rman_get_virtual(bar->pci_resource); in save_bar_parameters()
1126 bar->map_mode = VM_MEMATTR_UNCACHEABLE; in save_bar_parameters()
1132 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, in map_bar()
1133 &bar->pci_resource_id, RF_ACTIVE); in map_bar()
1134 if (bar->pci_resource == NULL) in map_bar()
1146 int rc = 0; in amd_ntb_map_pci_bars() local
1148 /* NTB Config/Control registers - BAR 0 */ in amd_ntb_map_pci_bars()
1149 ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0); in amd_ntb_map_pci_bars()
1150 rc = map_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]); in amd_ntb_map_pci_bars()
1151 if (rc != 0) in amd_ntb_map_pci_bars()
1154 /* Memory Window 0 BAR - BAR 1 */ in amd_ntb_map_pci_bars()
1155 ntb->bar_info[NTB_BAR_1].pci_resource_id = PCIR_BAR(1); in amd_ntb_map_pci_bars()
1156 rc = map_bar(ntb, &ntb->bar_info[NTB_BAR_1]); in amd_ntb_map_pci_bars()
1157 if (rc != 0) in amd_ntb_map_pci_bars()
1159 ntb->bar_info[NTB_BAR_1].xlat_off = AMD_BAR1XLAT_OFFSET; in amd_ntb_map_pci_bars()
1160 ntb->bar_info[NTB_BAR_1].limit_off = AMD_BAR1LMT_OFFSET; in amd_ntb_map_pci_bars()
1162 /* Memory Window 1 BAR - BAR 2&3 */ in amd_ntb_map_pci_bars()
1163 ntb->bar_info[NTB_BAR_2].pci_resource_id = PCIR_BAR(2); in amd_ntb_map_pci_bars()
1164 rc = map_bar(ntb, &ntb->bar_info[NTB_BAR_2]); in amd_ntb_map_pci_bars()
1165 if (rc != 0) in amd_ntb_map_pci_bars()
1167 ntb->bar_info[NTB_BAR_2].xlat_off = AMD_BAR23XLAT_OFFSET; in amd_ntb_map_pci_bars()
1168 ntb->bar_info[NTB_BAR_2].limit_off = AMD_BAR23LMT_OFFSET; in amd_ntb_map_pci_bars()
1170 /* Memory Window 2 BAR - BAR 4&5 */ in amd_ntb_map_pci_bars()
1171 ntb->bar_info[NTB_BAR_3].pci_resource_id = PCIR_BAR(4); in amd_ntb_map_pci_bars()
1172 rc = map_bar(ntb, &ntb->bar_info[NTB_BAR_3]); in amd_ntb_map_pci_bars()
1173 if (rc != 0) in amd_ntb_map_pci_bars()
1175 ntb->bar_info[NTB_BAR_3].xlat_off = AMD_BAR45XLAT_OFFSET; in amd_ntb_map_pci_bars()
1176 ntb->bar_info[NTB_BAR_3].limit_off = AMD_BAR45LMT_OFFSET; in amd_ntb_map_pci_bars()
1179 if (rc != 0) in amd_ntb_map_pci_bars()
1182 return (rc); in amd_ntb_map_pci_bars()
1192 bar_info = &ntb->bar_info[i]; in amd_ntb_unmap_pci_bars()
1193 if (bar_info->pci_resource != NULL) in amd_ntb_unmap_pci_bars()
1194 bus_release_resource(ntb->device, SYS_RES_MEMORY, in amd_ntb_unmap_pci_bars()
1195 bar_info->pci_resource_id, bar_info->pci_resource); in amd_ntb_unmap_pci_bars()
1209 ntb->hw_info = (struct amd_ntb_hw_info *)tbl->driver_data; in amd_ntb_probe()
1210 ntb->spad_count = ntb->hw_info->spad_count; in amd_ntb_probe()
1211 device_set_desc(device, tbl->descr); in amd_ntb_probe()
1222 ntb->device = device; in amd_ntb_attach()
1225 pci_enable_busmaster(ntb->device); in amd_ntb_attach()
1258 callout_drain(&ntb->hb_timer); in amd_ntb_detach()
1260 mtx_destroy(&ntb->db_mask_lock); in amd_ntb_detach()
1261 pci_disable_busmaster(ntb->device); in amd_ntb_detach()