Lines Matching +full:tx +full:- +full:threshold
46 /* XXX: Currently multi-queue can be used on the Tx side only */
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1)
134 /* Rx DMA Wake on LAN Registers 0x3690 - 0x36b8 */
136 /* Tx DMA Miscellaneous Registers */
139 #define MVNETA_PXTFTT 0x2478 /* Port Tx FIFO Threshold */
140 #define MVNETA_TXBADFCS 0x3cc0 /*Tx Bad FCS Transmitted Pckts Counter*/
141 #define MVNETA_TXDROPPED 0x3cc4 /* Tx Dropped Packets Counter */
143 /* Tx DMA Networking Controller Miscellaneous Registers */
146 #define MVNETA_PTXS(q) (0x3c40 + ((q) << 2)) /* Port TX queues Status*/
149 #define MVNETA_TXTBC(q) (0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/
150 #define MVNETA_PTXINIT 0x3cf0 /* Port TX Initialization */
152 /* Tx DMA Packet Modification Registers */
157 /* Tx DMA Queue Arbiter Registers (Version 1) */
159 #define MVNETA_TQTBC_V1 0x24e0 /* Transmit Queue Token-Bucket Cfg */
161 #define MVNETA_PMTBS_V1 0x24ec /* Port Max Token-Bucket Size */
163 /* Transmit Queue Token-Bucket Counter */
165 /* Transmit Queue Token-Bucket Configuration */
168 /* Tx DMA Queue Arbiter Registers (Version 3) */
174 #define MVNETA_PMTBS_V3 0x3e14 /* Port Max Token-Bucket Size */
178 /* Transmit Queue Max Token-Bucket Size */
180 /* Transmit Queue Token-Bucket Counter */
207 /* Gigabit Ethernet Auto-Negotiation Configuration Registers */
208 #define MVNETA_PANC 0x2c0c /* Port Auto-Negotiation Configuration*/
239 /* Port Rx Interrupt Threshold */
240 #define MVNETA_PRXTXTIC 0x25a0 /*Port RX_TX Threshold Interrupt Cause*/
241 #define MVNETA_PRXTXTIM 0x25a4 /*Port RX_TX Threshold Interrupt Mask */
269 /* MAC MIB Counters 0x3000 - 0x307c */
288 /* Tx */
330 #define MVNETA_S_SIZE(size) (((size) - 1) & 0xffff0000)
333 #define MVNETA_BARE_EN_MASK ((1 << MVNETA_NWINDOW) - 1)
433 #define MVNETA_DF_QUEUE_ALL ((MVNETA_RX_QNUM_MAX-1) << 1)
434 #define MVNETA_DF_QUEUE_MASK ((MVNETA_RX_QNUM_MAX-1) << 1)
440 #define MVNETA_PMFS_RXMFS(rxmfs) (((rxmfs) - 40) & 0x7c)
464 /* Port RX queues Descriptors Queue Threshold (MVNETA_PRXDQTH) */
465 /* Occupied Descriptors Threshold */
467 /* Non Occupied Descriptors Threshold */
486 * Tx DMA Miscellaneous Registers
497 * Tx DMA Networking Controller Miscellaneous Registers
499 /* Port TX queues Descriptors Queue Size (MVNETA_PTXDQS) */
503 /* Transmitted Buffer Threshold */
507 /* Port TX queues Status (MVNETA_PTXS) */
516 /* Port TX queues Status Update (MVNETA_PTXSU) */
522 /* TX Transmitted Buffers Counter (MVNETA_TXTBC) */
526 /* Port TX Initialization (MVNETA_PTXINIT) */
530 * Tx DMA Queue Arbiter Registers (Version 1 )
608 * Gigabit Ethernet Auto-Negotiation Configuration Registers
610 /* Port Auto-Negotiation Configuration (MVNETA_PANC) */
671 #define MVNETA_PI_PCSTXPRLPI (1 << 12) /* PCS Tx path received LPI*/
693 #define MVNETA_LPIS_PCSTXPLPIS (1 << 1) /* PCS Tx path LPI status */
695 #define MVNETA_LPIS_MACTXPLPWS (1 << 3)/* MAC Tx path LP wait status */
696 #define MVNETA_LPIS_MACTXPLPIS (1 << 4)/* MAC Tx path LP idle status */
716 #define MVNETA_PSR_PTP (1 << 7) /* Port Tx Pause */
717 #define MVNETA_PSR_PDP (1 << 8) /*Port is Doing Back-Pressure*/
733 /* Port RX_TX Interrupt Threshold */
736 /* Port RX_TX Threshold Interrupt Cause/Mask (MVNETA_PRXTXTIC/MVNETA_PRXTXTIM) */
740 /* Tx Buffer Threshold Cross Queue*/
748 /* Rx Descriptor Threshold Alert Queue*/