Lines Matching +full:sgmii +full:- +full:enable +full:- +full:pll

46 /* XXX: Currently multi-queue can be used on the Tx side only */
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
62 #define	MVNETA_TX_QUEUE_ALL	((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define	MVNETA_RX_QUEUE_ALL	((1<<MVNETA_RX_QNUM_MAX)-1)
76 #define	MVNETA_BARE		0x2290	/* Base Address Enable */
85 #define	MVNETA_MBUS_RETRY_EN	0x20	/* MBUS transactions retry enable */
134 /* Rx DMA Wake on LAN Registers	0x3690 - 0x36b8 */
149 #define	MVNETA_TXTBC(q)		(0x3ca0 + ((q) << 2)) /* TX Trans-ed Buf Count*/
159 #define	MVNETA_TQTBC_V1		0x24e0	/* Transmit Queue Token-Bucket Cfg */
161 #define	MVNETA_PMTBS_V1		0x24ec	/* Port Max Token-Bucket Size */
163 				/* Transmit Queue Token-Bucket Counter */
165 				/* Transmit Queue Token-Bucket Configuration */
174 #define	MVNETA_PMTBS_V3		0x3e14	/* Port Max Token-Bucket Size */
178 				/* Transmit Queue Max Token-Bucket Size */
180 				/* Transmit Queue Token-Bucket Counter */
207 /* Gigabit Ethernet Auto-Negotiation Configuration Registers */
208 #define	MVNETA_PANC		0x2c0c	/* Port Auto-Negotiation Configuration*/
246 #define	MVNETA_PIE		0x25b8	/* Port Interrupt Enable */
254 /* SGMII PHY Registers */
255 #define	MVNETA_PPLLC		0x2e04	/* Power and PLL Control */
260 #define	MVNETA_DLE		0x2e8c	/* Digital Loopback Enable */
269 /* MAC MIB Counters			0x3000 - 0x307c */
330 #define	MVNETA_S_SIZE(size)		(((size) - 1) & 0xffff0000)
332 /* Base Address Enable (MVNETA_BARE) */
333 #define	MVNETA_BARE_EN_MASK		((1 << MVNETA_NWINDOW) - 1)
433 #define	MVNETA_DF_QUEUE_ALL		((MVNETA_RX_QNUM_MAX-1) << 1)
434 #define	MVNETA_DF_QUEUE_MASK		((MVNETA_RX_QNUM_MAX-1) << 1)
440 #define	MVNETA_PMFS_RXMFS(rxmfs)	(((rxmfs) - 40) & 0x7c)
443 #define	MVNETA_RQC_EN_MASK		(0xff << 0)	/* Enable Q */
490 #define	MVNETA_TQC_ENQ(q)		(1 << ((q) + 0))/* Enable Q */
608  * Gigabit Ethernet Auto-Negotiation Configuration Registers
610 /* Port Auto-Negotiation Configuration (MVNETA_PANC) */
683 #define	MVNETA_LPIC1_LPIRE		(1 << 0)	/* LPI request enable */
717 #define	MVNETA_PSR_PDP			(1 << 8) /*Port is Doing Back-Pressure*/
781 /* Port Interrupt Enable (MVNETA_PIE) */
795  * SGMII PHY Registers
797 /* Power and PLL Control (MVNETA_PPLLC) */
809 /* Digital Loopback Enable (MVNETA_DLE) */