Lines Matching +full:0 +full:xe000000
99 static int mxge_force_firmware = 0;
103 static int mxge_verbose = 0;
107 static int mxge_always_promisc = 0;
109 static int mxge_throttle = 0;
140 DRIVER_MODULE(mxge, pci, mxge_driver, 0, 0);
172 return 0;
188 if (err != 0) {
191 sc->wc = 0;
201 if (error == 0) {
215 boundary = 0;
235 if (err != 0) {
244 if (err != 0) {
252 (void *)&dma->bus_addr, 0);
253 if (err != 0) {
257 return 0;
276 * SN=x\0
277 * MAC=x:x:x:x:x:x\0
278 * PC=text\0
289 found_mac = 0;
290 found_sn2 = 0;
291 while (*ptr != '\0') {
292 if (strncmp(ptr, "MAC=", 4) == 0) {
294 for (i = 0;;) {
305 } else if (strncmp(ptr, "PC=", 3) == 0) {
309 } else if (!found_sn2 && (strncmp(ptr, "SN=", 3) == 0)) {
313 } else if (strncmp(ptr, "SN2=", 4) == 0) {
320 while (*ptr++ != '\0') {}
324 return 0;
355 if (vendor_id != 0x10de)
358 base = 0;
360 if (device_id == 0x005d) {
362 base = 0xe0000000UL;
363 } else if (device_id >= 0x0374 && device_id <= 0x378) {
365 mcp55 = pci_find_bsf(0, 0, 0);
367 0x10de == pci_read_config(mcp55, PCIR_VENDOR, 2) &&
368 0x0369 == pci_read_config(mcp55, PCIR_DEVICE, 2)) {
369 word = pci_read_config(mcp55, 0x90, 2);
370 base = ((unsigned long)word & 0x7ffeU) << 25;
378 config read/write beyond 0xff will access the config space
383 #if 0
386 val = pci_read_config(pdev, 0x178, 4);
387 if (val != 0xffffffff) {
388 val |= 0x40;
389 pci_write_config(pdev, 0x178, val, 4);
395 * opteron/nvidia class machine the 0xe000000 mapping is
413 + 0x00100000UL * (unsigned long)bus
414 + 0x00001000UL * (unsigned long)(func
431 device_printf(sc->dev, "mapping failed: 0x%x:0x%x\n",
437 ptr32 = (uint32_t*)(cfgptr + 0x178);
440 if (val == 0xffffffff) {
445 *ptr32 = val | 0x40;
486 cmd.data2 = len * 0x10000;
488 if (status != 0) {
493 (cmd.data0 & 0xffff);
496 cmd.data2 = len * 0x1;
498 if (status != 0) {
503 (cmd.data0 & 0xffff);
507 cmd.data2 = len * 0x10001;
509 if (status != 0) {
514 (cmd.data0 & 0xffff);
517 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
555 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
556 pectl = pci_read_config(dev, reg + 0x8, 2);
558 device_printf(dev, "Max Read Req. size != 4k (0x%x\n",
570 if (status != 0) {
584 return 0;
586 if (status == 0)
587 return 0; /* keep the aligned firmware */
600 int aligned = 0;
606 if (force_firmware != 0) {
610 aligned = 0;
620 if (sc->link_width != 0 && sc->link_width <= 4) {
628 if (0 == mxge_firmware_probe(sc))
629 return 0;
639 return (mxge_load_firmware(sc, 0));
647 device_printf(sc->dev, "Bad firmware type: 0x%x\n",
668 return 0;
729 if (status != 0)
733 for (i = 0; i < fw_len; i += 256) {
743 status = 0;
771 *confirm = 0;
781 buf[0] = htobe32(dma_high); /* confirm addr MSW */
783 buf[2] = htobe32(0xffffffff); /* confirm data */
796 i = 0;
797 while (*confirm != 0xffffffff && i < 20) {
801 if (*confirm != 0xffffffff) {
802 device_printf(sc->dev, "dummy rdma %s failed (%p = 0x%x)",
817 int err, sleep_total = 0;
832 response->result = 0xffffffff;
838 for (sleep_total = 0; sleep_total < 20; sleep_total++) {
843 case 0:
845 err = 0;
847 case 0xffffffff:
966 return 0;
970 *confirm = 0;
980 buf[0] = htobe32(dma_high); /* confirm addr MSW */
982 buf[2] = htobe32(0xffffffff); /* confirm data */
992 buf[6] = htobe32(0); /* where to jump to */
999 i = 0;
1000 while (*confirm != 0xffffffff && i < 20) {
1006 if (*confirm != 0xffffffff) {
1007 device_printf(sc->dev,"handoff failed (%p = 0x%x)",
1012 return 0;
1022 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
1049 return 0;
1084 if (ctx->error != 0)
1085 return (0);
1110 if (err != 0) {
1126 if (err != 0) {
1135 ctx.error = 0;
1137 if (ctx.error != 0) {
1146 if (err != 0) {
1163 cmd.data0 = 0;
1166 if (status == 0)
1184 memset(&cmd, 0, sizeof (cmd));
1186 if (status != 0) {
1203 * slice 0. It must also be called *after*
1212 if (status != 0) {
1226 if (status != 0) {
1235 for (slice = 0; slice < sc->num_slices; slice++) {
1237 memset(rx_done->entry, 0, sc->rx_ring_size);
1258 if (status != 0) {
1268 for (slice = 0; slice < sc->num_slices; slice++) {
1272 /* reset mcp/driver shared state back to 0 */
1273 ss->rx_done.idx = 0;
1274 ss->rx_done.cnt = 0;
1275 ss->tx.req = 0;
1276 ss->tx.done = 0;
1277 ss->tx.pkt_done = 0;
1278 ss->tx.queue_active = 0;
1279 ss->tx.activate = 0;
1280 ss->tx.deactivate = 0;
1281 ss->tx.wake = 0;
1282 ss->tx.defrag = 0;
1283 ss->tx.stall = 0;
1284 ss->rx_big.cnt = 0;
1285 ss->rx_small.cnt = 0;
1286 ss->lc.lro_bad_csum = 0;
1287 ss->lc.lro_queued = 0;
1288 ss->lc.lro_flushed = 0;
1320 if (err != 0) {
1325 return 0;
1333 if (err == 0)
1349 if (err != 0) {
1353 return 0;
1355 if (intr_coal_delay == 0 || intr_coal_delay > 1000*1000)
1376 if (err != 0) {
1380 return 0;
1411 for (slice = 0; slice < sc->num_slices; slice++) {
1434 fw = sc->ss[0].fw_stats;
1440 0, "firmware version");
1444 0, "serial number");
1448 0, "product_code");
1452 0, "tx_boundary");
1456 0, "tx_boundary");
1460 0, "write combining PIO?");
1464 0, "DMA Read speed in MB/s");
1468 0, "DMA Write speed in MB/s");
1472 0, "DMA concurrent Read/Write speed in MB/s");
1476 0, "Number of times NIC was reset");
1481 sc, 0, mxge_change_intr_coal, "I",
1485 "throttle", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
1490 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0,
1497 0, "Wait for IRQ line to go low in ihandler");
1503 &fw->link_up, 0, mxge_handle_be32, "I", "link up");
1506 &fw->rdma_tags_available, 0, mxge_handle_be32, "I",
1510 &fw->dropped_bad_crc32, 0, mxge_handle_be32, "I",
1514 &fw->dropped_bad_phy, 0, mxge_handle_be32, "I", "dropped_bad_phy");
1518 &fw->dropped_link_error_or_filtered, 0, mxge_handle_be32, "I",
1523 &fw->dropped_link_overflow, 0, mxge_handle_be32, "I",
1528 &fw->dropped_multicast_filtered, 0, mxge_handle_be32, "I",
1533 &fw->dropped_no_big_buffer, 0, mxge_handle_be32, "I",
1538 &fw->dropped_no_small_buffer, 0, mxge_handle_be32, "I",
1543 &fw->dropped_overrun, 0, mxge_handle_be32, "I",
1547 &fw->dropped_pause, 0, mxge_handle_be32, "I", "dropped_pause");
1550 &fw->dropped_runt, 0, mxge_handle_be32, "I", "dropped_runt");
1555 &fw->dropped_unicast_filtered, 0, mxge_handle_be32, "I",
1562 0, "verbose printing");
1568 "slice", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "");
1570 for (slice = 0; slice < sc->num_slices; slice++) {
1578 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "");
1583 0, "rx_small_cnt");
1587 0, "rx_small_cnt");
1590 0, "number of lro merge queues flushed");
1594 0, "number of bad csums preventing LRO");
1598 0, "number of frames appended to lro merge"
1604 0, "tx_req");
1609 0, "tx_done");
1613 0, "tx_done");
1617 0, "tx_stall");
1621 0, "tx_wake");
1625 0, "tx_defrag");
1629 0, "tx_queue_active");
1633 0, "tx_activate");
1637 0, "tx_deactivate");
1680 src->flags = 0;
1686 for (i = 0; i < (cnt - 1); i += 2) {
1696 i = 0;
1744 m_copydata(m, 0, pi->ip_off + sizeof(*pi->ip),
1750 return 0;
1754 m_copydata(m, 0, pi->ip_off + pi->ip_hlen +
1764 m_copydata(m, 0, pi->ip_off + sizeof(*pi->ip6),
1768 nxt = 0;
1775 return 0;
1782 m_copydata(m, 0, pi->ip_off + pi->ip_hlen +
1792 return 0;
1822 if (__predict_false((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_TCP_IPV6)) == 0)) {
1830 #if (CSUM_TCP_IPV6 != 0) && defined(INET6)
1834 IPPROTO_TCP, 0);
1866 cnt = 0;
1867 rdma_count = 0;
1872 * to 0 after a segment cut.
1897 if (__predict_true(cum_len >= 0)) {
1901 next_is_first = (cum_len_next == 0);
1907 } else if (cum_len_next >= 0) {
1910 cum_len_next = 0;
1921 req->pad = 0;
1934 if (cksum_offset != 0 && !pi->ip6) {
1938 cksum_offset = 0;
1956 if ((ss->sc->num_slices > 1) && tx->queue_active == 0) {
2019 struct mxge_pkt_info pi = {0,0,0,0};
2064 if (__predict_false(err != 0)) {
2082 cksum_offset = 0;
2083 pseudo_hdr_offset = 0;
2098 odd_flag = 0;
2104 cum_len = 0;
2107 for (i = 0; i < cnt; i++) {
2117 cksum_offset = 0;
2119 req->pad = 0; /* complete solid 16-byte block */
2125 req->flags = 0;
2136 req->cksum_offset = 0;
2138 req->pad = 0; /* complete solid 16-byte block */
2144 tx->req_list[0].rdma_count = cnt;
2145 #if 0
2147 for (i = 0; i < cnt; i++) {
2148 printf("%d: addr: 0x%x 0x%x len:%d pso%d,"
2149 "cso:%d, flags:0x%x, rdma:%d\n",
2162 if ((ss->sc->num_slices > 1) && tx->queue_active == 0) {
2187 for (slice = 0; slice < sc->num_slices; slice++) {
2221 if (((ss->if_drv_flags & IFF_DRV_OACTIVE) == 0)
2252 } else if ((err = drbr_enqueue(ifp, tx->br, m)) != 0) {
2257 return (0);
2266 int err = 0;
2292 ss = &sc->ss[0];
2312 src->addr_low = 0xffffffff;
2339 if (err != 0) {
2372 if (err != 0) {
2383 for (i = 0; i < rx->nbufs; i++) {
2400 csum = 0;
2401 while (len > 0) {
2406 csum = (csum >> 16) + (csum & 0xffff);
2407 csum = (csum >> 16) + (csum & 0xffff);
2440 csum = (csum >> 16) + (csum & 0xFFFF);
2441 csum = (csum >> 16) + (csum & 0xFFFF);
2444 c ^= 0xffff;
2474 if ((cap & IFCAP_RXCSUM) == 0)
2482 c ^= 0xffff;
2487 if ((cap & IFCAP_RXCSUM_IPV6) == 0)
2517 (*csum) = ((*csum) >> 16) + ((*csum) & 0xFFFF);
2518 (*csum) = ((*csum) >> 16) + ((*csum) & 0xFFFF);
2605 (0 == mxge_rx_csum(m, csum))) {
2607 m->m_pkthdr.csum_data = 0xffff;
2612 if (lro && (0 == tcp_lro_rx(&ss->lc, m, 0)))
2673 (0 == mxge_rx_csum(m, csum))) {
2675 m->m_pkthdr.csum_data = 0xffff;
2680 if (lro && (0 == tcp_lro_rx(&ss->lc, m, csum)))
2692 int limit = 0;
2698 while (rx_done->entry[rx_done->idx].length != 0) {
2700 rx_done->entry[rx_done->idx].length = 0;
2747 tx->info[idx].flag = 0;
2767 tx->queue_active = 0;
2777 {IFM_10G_CX4, 0x7f, "10GBASE-CX4 (module)"},
2780 {0, (1 << 5), "10GBASE-ER"},
2782 {0, (1 << 3), "10GBASE-SW"},
2783 {0, (1 << 2), "10GBASE-LW"},
2784 {0, (1 << 1), "10GBASE-EW"},
2785 {0, (1 << 0), "Reserved"}
2789 {IFM_10G_TWINAX, 0, "10GBASE-Twinax"},
2790 {0, (1 << 7), "Reserved"},
2794 {IFM_10G_TWINAX,(1 << 0), "10GBASE-Twinax"}
2802 0, NULL);
2829 for (i = 0; i < 3; i++, ptr++) {
2874 sc->need_media_probe = 0;
2903 cmd.data0 = 0; /* just fetch 1 byte, not all 256 */
2919 for (ms = 0; (err == EBUSY) && (ms < 50); ms++) {
2930 if (cmd.data0 == mxge_media_types[0].bitmask) {
2933 mxge_media_types[0].name);
2934 if (sc->current_media != mxge_media_types[0].flag) {
2936 mxge_media_set(sc, mxge_media_types[0].flag);
2955 device_printf(sc->dev, "%s media 0x%x unknown\n",
2980 *sc->irq_deassert = 0;
2983 stats->valid = 0;
2985 stats->valid = 0;
2993 (rx_done->entry[rx_done->idx].length != 0)) {
3028 sc->link_state = 0;
3034 if (valid & 0x1)
3046 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
3059 for (i = 0; i <= ss->rx_big.mask; i++) {
3068 for (i = 0; i <= ss->rx_small.mask; i++) {
3081 for (i = 0; i <= ss->tx.mask; i++) {
3082 ss->tx.info[i].flag = 0;
3097 for (slice = 0; slice < sc->num_slices; slice++)
3128 for (i = 0; i <= ss->tx.mask; i++) {
3140 for (i = 0; i <= ss->rx_small.mask; i++) {
3154 for (i = 0; i <= ss->rx_big.mask; i++) {
3172 for (slice = 0; slice < sc->num_slices; slice++)
3216 if (err != 0) {
3224 0, /* boundary */
3234 if (err != 0) {
3239 for (i = 0; i <= ss->rx_small.mask; i++) {
3240 err = bus_dmamap_create(ss->rx_small.dmat, 0,
3242 if (err != 0) {
3248 err = bus_dmamap_create(ss->rx_small.dmat, 0,
3250 if (err != 0) {
3256 for (i = 0; i <= ss->rx_big.mask; i++) {
3257 err = bus_dmamap_create(ss->rx_big.dmat, 0,
3259 if (err != 0) {
3265 err = bus_dmamap_create(ss->rx_big.dmat, 0,
3267 if (err != 0) {
3309 if (err != 0) {
3317 for (i = 0; i <= ss->tx.mask; i++) {
3318 err = bus_dmamap_create(ss->tx.dmat, 0,
3320 if (err != 0) {
3326 return 0;
3341 if (err != 0) {
3351 for (slice = 0; slice < sc->num_slices; slice++) {
3355 if (err != 0)
3358 return 0;
3409 err = 0;
3430 if (err != 0) {
3437 for (i = 0; i <= ss->rx_small.mask; i++) {
3446 for (i = 0; i <= ss->rx_big.mask; i++) {
3447 ss->rx_big.shadow[i].addr_low = 0xffffffff;
3448 ss->rx_big.shadow[i].addr_high = 0xffffffff;
3454 for (i = 0; i <= ss->rx_big.mask; i += ss->rx_big.nbufs) {
3463 return 0;
3479 if (err != 0) {
3492 if (err != 0) {
3500 for (i = 0; i < sc->num_slices; i++)
3506 if (err != 0) {
3536 if (err != 0) {
3542 for (slice = 0; slice < sc->num_slices; slice++) {
3553 if (err != 0) {
3562 sc->fw_multicast_support = 0;
3567 if (err != 0) {
3572 for (slice = 0; slice < sc->num_slices; slice++) {
3574 if (err != 0) {
3587 for (slice = 0; slice < sc->num_slices; slice++) {
3592 if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING, 0);
3593 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_OACTIVE);
3595 return 0;
3611 for (slice = 0; slice < sc->num_slices; slice++) {
3615 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING);
3635 return 0;
3646 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3647 lnk = pci_read_config(dev, reg + 0x12, 2);
3648 sc->link_width = (lnk >> 4) & 0x3f;
3650 if (sc->pectl == 0) {
3651 pectl = pci_read_config(dev, reg + 0x8, 2);
3652 pectl = (pectl & ~0x7000) | (5 << 12);
3653 pci_write_config(dev, reg + 0x8, pectl, 2);
3657 pci_write_config(dev, reg + 0x8, sc->pectl, 2);
3672 if (pci_find_cap(dev, PCIY_VENDOR, &vs) != 0) {
3678 pci_write_config(dev, vs + 0x10, 0x3, 1);
3680 pci_write_config(dev, vs + 0x18, 0xfffffff0, 4);
3681 return (pci_read_config(dev, vs + 0x14, 4));
3705 if (cmd == 0xffff) {
3713 if (cmd == 0xffff) {
3717 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
3720 device_printf(sc->dev, "NIC rebooted, status = 0x%x\n",
3731 sc->link_state = 0;
3739 for (s = 0; s < num_tx_slices; s++) {
3753 err = mxge_load_firmware(sc, 0);
3762 for (s = 0; s < num_tx_slices; s++) {
3772 err = 0;
3778 sc->dying = 0;
3813 int i, err = 0;
3817 for (i = 0; (i < sc->num_slices) && (err == 0); i++) {
3850 rv = 0;
3854 for (int s = 0; s < sc->num_slices; s++)
3858 for (int s = 0; s < sc->num_slices; s++)
3862 for (int s = 0; s < sc->num_slices; s++)
3866 for (int s = 0; s < sc->num_slices; s++)
3870 for (int s = 0; s < sc->num_slices; s++)
3874 for (int s = 0; s < sc->num_slices; s++)
3886 u_long pkts = 0;
3887 int err = 0;
3900 if (pkts == 0) {
3903 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
3912 if (err == 0)
3928 int err = 0;
3937 mxge_close(sc, 0);
3939 if (err != 0) {
3941 mxge_close(sc, 0);
3958 ifmr->ifm_status |= sc->link_state ? IFM_ACTIVE : 0;
3969 if (i2c->dev_addr != 0xA0 &&
3970 i2c->dev_addr != 0xA2)
3975 for (i = 0; i < i2c->len; i++) {
3976 i2c_args = i2c->dev_addr << 0x8;
3978 cmd.data0 = 0; /* just fetch 1 byte, not all 256 */
3985 cmd.data0 = i2c_args & 0xff;
3987 for (ms = 0; (err == EBUSY) && (ms < 50); ms++) {
3988 cmd.data0 = i2c_args & 0xff;
3997 return (0);
4008 err = 0;
4032 mxge_close(sc, 0);
4055 if_setcapenablebit(ifp, 0, (IFCAP_TXCSUM|IFCAP_TSO4));
4056 if_sethwassistbits(ifp, 0, (CSUM_TCP | CSUM_UDP));
4058 if_setcapenablebit(ifp, IFCAP_TXCSUM, 0);
4059 if_sethwassistbits(ifp, (CSUM_TCP | CSUM_UDP), 0);
4064 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM);
4066 if_setcapenablebit(ifp, IFCAP_RXCSUM, 0);
4071 if_setcapenablebit(ifp, 0, IFCAP_TSO4);
4073 if_setcapenablebit(ifp, IFCAP_TSO4, 0);
4074 if_sethwassistbits(ifp, CSUM_TSO, 0);
4085 if_setcapenablebit(ifp, 0,
4087 if_sethwassistbits(ifp, 0,
4090 if_setcapenablebit(ifp, IFCAP_TXCSUM_IPV6, 0);
4092 CSUM_TCP_IPV6 | CSUM_UDP_IPV6, 0);
4097 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM_IPV6);
4099 if_setcapenablebit(ifp, IFCAP_RXCSUM_IPV6, 0);
4104 if_setcapenablebit(ifp, 0, IFCAP_TSO6);
4106 if_setcapenablebit(ifp, IFCAP_TSO6, 0);
4107 if_sethwassistbits(ifp, CSUM_TSO, 0);
4125 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
4151 if (err != 0)
4160 if (err == 0)
4197 if (mxge_intr_coal_delay < 0 || mxge_intr_coal_delay > 10*1000)
4199 if (mxge_ticks == 0)
4226 for (i = 0; i < sc->num_slices; i++) {
4255 if (err != 0) {
4266 for (i = 0; i < sc->num_slices; i++) {
4275 if (err != 0)
4289 if (err != 0)
4299 return (0);
4319 if (mxge_max_slices == 0 || mxge_max_slices == 1 || mp_ncpus < 2)
4333 status = mxge_load_firmware(sc, 0);
4334 if (status != 0) {
4341 memset(&cmd, 0, sizeof (cmd));
4343 if (status != 0) {
4350 if (status != 0) {
4359 if (status != 0) {
4366 if (status != 0) {
4395 (void) mxge_load_firmware(sc, 0);
4415 if (err != 0) {
4436 for (i = 0; i < sc->num_slices; i++) {
4452 for (i = 0; i < sc->num_slices; i++) {
4456 if (err != 0) {
4468 for (i = 0; i < sc->num_slices; i++)
4472 return (0);
4475 for (i = 0; i < sc->num_slices; i++) {
4485 for (i = 0; i < sc->num_slices; i++) {
4510 if (count == 1 && pci_alloc_msi(sc->dev, &count) == 0) {
4513 rid = 0;
4528 mxge_intr, &sc->ss[0], &sc->ih);
4529 if (err != 0) {
4531 sc->legacy_irq ? 0 : 1, sc->irq_res);
4543 for (i = 0; i < sc->num_slices; i++) {
4552 for (i = 0; i < sc->num_slices; i++) {
4573 sc->legacy_irq ? 0 : 1, sc->irq_res);
4597 if (0 && err == 0 && sc->num_slices > 1) {
4621 0, /* boundary */
4628 0, /* flags */
4632 if (err != 0) {
4649 callout_init_mtx(&sc->co_hdl, &sc->driver_mtx, 0);
4663 sc->sram_size = 2*1024*1024 - (2*(48*1024)+(32*1024)) - 0x100;
4680 if (err != 0)
4689 if (err != 0)
4693 if (err != 0)
4697 if (err != 0)
4702 if (err != 0)
4708 if (err != 0)
4711 err = mxge_reset(sc, 0);
4712 if (err != 0)
4716 if (err != 0) {
4722 if (err != 0) {
4732 if_setcapabilitiesbit(ifp, IFCAP_LRO, 0);
4736 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM, 0);
4741 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTSO, 0);
4745 if_setcapabilitiesbit(ifp, IFCAP_JUMBO_MTU, 0);
4751 if_sethwassistbits(ifp, CSUM_TCP_IPV6 | CSUM_UDP_IPV6, 0);
4755 if_setcapabilitiesbit(ifp, IFCAP_TSO6, 0);
4757 sizeof (sc->ss[0].scratch));
4760 if (sc->lro_cnt == 0)
4761 if_setcapenablebit(ifp, 0, IFCAP_LRO);
4769 if_sethwtsomaxsegcount(ifp, sc->ss[0].tx.max_desc);
4772 ifmedia_init(&sc->media, 0, mxge_media_change,
4776 sc->dying = 0;
4788 return 0;
4830 mxge_close(sc, 0);
4840 mxge_dummy_rdma(sc, 0);
4854 return 0;
4860 return 0;