Lines Matching defs:ctlr
98 struct mvs_controller *ctlr = device_get_softc(dev);
104 ctlr->dev = dev;
110 ctlr->channels = mvs_ids[i].ports;
111 ctlr->quirks = mvs_ids[i].quirks;
112 ctlr->ccc = 0;
114 device_get_unit(dev), "ccc", &ctlr->ccc);
115 ctlr->cccc = 8;
117 device_get_unit(dev), "cccc", &ctlr->cccc);
118 if (ctlr->ccc == 0 || ctlr->cccc == 0) {
119 ctlr->ccc = 0;
120 ctlr->cccc = 0;
122 if (ctlr->ccc > 100000)
123 ctlr->ccc = 100000;
126 ((ctlr->quirks & MVS_Q_GENI) ? "I" :
127 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")),
128 ctlr->channels,
129 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"),
130 ((ctlr->quirks & MVS_Q_GENI) ?
132 ((ctlr->quirks & MVS_Q_GENIIE) ?
134 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF);
136 ctlr->r_rid = PCIR_BAR(0);
137 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
138 &ctlr->r_rid, RF_ACTIVE)))
141 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
142 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
143 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
144 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
145 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
146 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
149 if ((error = rman_manage_region(&ctlr->sc_iomem,
150 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
151 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
152 rman_fini(&ctlr->sc_iomem);
159 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
160 rman_fini(&ctlr->sc_iomem);
164 for (unit = 0; unit < ctlr->channels; unit++) {
178 struct mvs_controller *ctlr = device_get_softc(dev);
187 if (ctlr->irq.r_irq) {
188 bus_teardown_intr(dev, ctlr->irq.r_irq,
189 ctlr->irq.handle);
191 ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
195 rman_fini(&ctlr->sc_iomem);
196 if (ctlr->r_mem)
197 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
198 mtx_destroy(&ctlr->mtx);
205 struct mvs_controller *ctlr = device_get_softc(dev);
206 int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0;
209 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
211 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
213 ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000);
217 ctlr->ccc, ctlr->cccc);
221 if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) {
222 ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc);
223 ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc);
224 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
230 for (i = 0; i < ctlr->channels / 4; i++) {
232 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc);
233 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc);
237 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000);
240 ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) |
242 ctlr->mim = ctlr->gmim | ctlr->pmim;
243 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
245 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff);
252 struct mvs_controller *ctlr = device_get_softc(dev);
256 if (ctlr->ccc == 0)
259 mtx_lock(&ctlr->mtx);
261 ctlr->pmim |= bit;
263 ctlr->pmim &= ~bit;
264 ctlr->mim = ctlr->gmim | ctlr->pmim;
265 if (!ctlr->msia)
266 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
267 mtx_unlock(&ctlr->mtx);
273 struct mvs_controller *ctlr = device_get_softc(dev);
277 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
279 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
294 struct mvs_controller *ctlr = device_get_softc(dev);
307 ctlr->msi = msi;
309 ctlr->irq.r_irq_rid = msi ? 1 : 0;
310 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
311 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
315 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL,
316 mvs_intr, ctlr, &ctlr->irq.handle))) {
319 ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
320 ctlr->irq.r_irq = NULL;
332 struct mvs_controller *ctlr = data;
338 ic = ATA_INL(ctlr->r_mem, CHIP_MIC);
339 if (ctlr->msi) {
341 mtx_lock(&ctlr->mtx);
342 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0);
343 ctlr->msia = 1; /* Deny MIM update during processing. */
344 mtx_unlock(&ctlr->mtx);
349 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
350 for (p = 0; p < ctlr->channels; p++) {
371 ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic);
376 (function = ctlr->interrupt[p].function)) {
377 arg.arg = ctlr->interrupt[p].argument;
382 if (ctlr->msi) {
384 mtx_lock(&ctlr->mtx);
385 ctlr->msia = 0; /* Allow MIM update. */
386 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
387 mtx_unlock(&ctlr->mtx);
396 struct mvs_controller *ctlr = device_get_softc(dev);
404 st = rman_get_start(ctlr->r_mem);
405 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
410 bsh = rman_get_bushandle(ctlr->r_mem);
411 bst = rman_get_bustag(ctlr->r_mem);
419 res = ctlr->irq.r_irq;
446 struct mvs_controller *ctlr = device_get_softc(dev);
453 ctlr->interrupt[unit].function = function;
454 ctlr->interrupt[unit].argument = argument;
462 struct mvs_controller *ctlr = device_get_softc(dev);
465 ctlr->interrupt[unit].function = NULL;
466 ctlr->interrupt[unit].argument = NULL;