1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
42 #define IC_HC0			 0x000001ff	/* bits 0-8 = HC0 */
44 #define IC_HC1			 (IC_HC0 << IC_HC_SHIFT) /* 9-17 = HC1 */
58 #define IC_MAIN_RSVD		 (0xfe000000)	/* bits 31-25 */
59 #define IC_MAIN_RSVD_5		 (0xfff10000)	/* bits 31-19 */
60 #define IC_MAIN_RSVD_SOC	 (0xfffffec0)	/* bits 31-9, 7-6 */
65 #define CHIP_SOC_HC0_MASK(num)	(0xff >> ((4 - (num)) * 2))
87 #define HC_RQOP			0x4	/* Request Queue Out-Pointer */
88 #define HC_RQIP			0x8	/* Response Queue In-Pointer */
128 #define EDMA_IE_ETRANSINT	 (1 << 8)	/* Transport Layer */
133 	/* Link Layer is reset by the reception of SYNC primitive from device */
147 							/* Non-fatal Errors */
148 #define EDMA_REQQBAH		0x10	/* Request Queue Base Address High */
149 #define EDMA_REQQIP		0x14	/* Request Queue In-Pointer */
150 #define EDMA_REQQOP		0x18	/* Request Queue Out-Pointer */
155 #define EDMA_RESQBAH		0x1c	/* Response Queue Base Address High */
156 #define EDMA_RESQIP		0x20	/* Response Queue In-Pointer */
157 #define EDMA_RESQOP		0x24	/* Response Queue Out-Pointer */
248 #define DMA_DTLBA			0x22c	/* Descriptor Table Low Base Address */
250 #define DMA_DTHBA			0x230	/* Descriptor Table High Base Address */
254 /* Serial-ATA Registers */
321 #define SATA_SATAICFG			0x050	/* Serial-ATA Interface Configuration */
346 #define SATA_SATAICTL			0x344	/* Serial-ATA Interface Control */
354 #define SATA_SATAITC			0x348	/* Serial-ATA Interface Test Control */
355 #define SATA_SATAIS			0x34c	/* Serial-ATA Interface Status */
397 	uint32_t cprdbl;	/* cPRD Desriptor Table Base Low Address */
398 	uint32_t cprdbh;	/* cPRD Desriptor Table Base High Address */
409 	uint32_t cprdbl;	/* cPRD Desriptor Table Base Low Address */
410 	uint32_t cprdbh;	/* cPRD Desriptor Table Base High Address */
506     u_int			eprd_offset;	/* EPRD offset */
555 	int			fbs_enabled;	/* FIS-based switching enabled */
573 	int			resetting;	/* Hard-reset in progress. */
574 	int			resetpolldiv;	/* Hard-reset poll divider. */
583 	struct callout		reset_timer;	/* Hard-reset timeout */
585 	struct mvs_device	user[16];	/* User-specified settings */
633 #define ATA_INB(res, offset) \  argument
634 	bus_read_1((res), (offset))
635 #define ATA_INW(res, offset) \  argument
636 	bus_read_2((res), (offset))
637 #define ATA_INL(res, offset) \  argument
638 	bus_read_4((res), (offset))
639 #define ATA_INSW(res, offset, addr, count) \  argument
640 	bus_read_multi_2((res), (offset), (addr), (count))
641 #define ATA_INSW_STRM(res, offset, addr, count) \  argument
642 	bus_read_multi_stream_2((res), (offset), (addr), (count))
643 #define ATA_INSL(res, offset, addr, count) \  argument
644 	bus_read_multi_4((res), (offset), (addr), (count))
645 #define ATA_INSL_STRM(res, offset, addr, count) \  argument
646 	bus_read_multi_stream_4((res), (offset), (addr), (count))
647 #define ATA_OUTB(res, offset, value) \  argument
648 	bus_write_1((res), (offset), (value))
649 #define ATA_OUTW(res, offset, value) \  argument
650 	bus_write_2((res), (offset), (value))
651 #define ATA_OUTL(res, offset, value) \  argument
652 	bus_write_4((res), (offset), (value));
653 #define ATA_OUTSW(res, offset, addr, count) \  argument
654 	bus_write_multi_2((res), (offset), (addr), (count))
655 #define ATA_OUTSW_STRM(res, offset, addr, count) \  argument
656 	bus_write_multi_stream_2((res), (offset), (addr), (count))
657 #define ATA_OUTSL(res, offset, addr, count) \  argument
658 	bus_write_multi_4((res), (offset), (addr), (count))
659 #define ATA_OUTSL_STRM(res, offset, addr, count) \  argument
660 	bus_write_multi_stream_4((res), (offset), (addr), (count))