Lines Matching defs:rq
49 struct mlx5e_rq_param rq;
848 struct mlx5e_rq *rq = &pch->rq;
849 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
852 rq_stats->sw_lro_queued = rq->lro.lro_queued;
853 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
1205 struct mlx5e_rq *rq)
1234 &rq->dma_tag)))
1237 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1238 &rq->wq_ctrl);
1242 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1244 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1248 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1250 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1254 rq->mbuf = malloc_domainset(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN,
1257 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1260 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1263 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1268 for (j = 0; j < rq->nsegs; j++)
1272 INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1274 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1277 struct mlx5e_channel_param, rq)->rx_cq.cqc;
1281 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1284 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1287 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1292 rq->ifp = priv->ifp;
1293 rq->channel = c;
1294 rq->ix = c->ix;
1297 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1299 rq->stats.arg);
1303 free(rq->mbuf, M_MLX5EN);
1304 tcp_lro_free(&rq->lro);
1306 mlx5_wq_destroy(&rq->wq_ctrl);
1308 bus_dma_tag_destroy(rq->dma_tag);
1314 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1320 sysctl_ctx_free(&rq->stats.ctx);
1323 tcp_lro_free(&rq->lro);
1325 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1327 if (rq->mbuf[i].mbuf != NULL) {
1328 if (rq->mbuf[i].ipsec_mtag != NULL)
1329 m_tag_free(&rq->mbuf[i].ipsec_mtag->tag);
1330 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1331 m_freem(rq->mbuf[i].mbuf);
1333 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1335 free(rq->mbuf, M_MLX5EN);
1336 mlx5_wq_destroy(&rq->wq_ctrl);
1337 bus_dma_tag_destroy(rq->dma_tag);
1341 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1343 struct mlx5e_channel *c = rq->channel;
1354 sizeof(u64) * rq->wq_ctrl.buf.npages;
1370 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1372 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1374 mlx5_fill_page_array(&rq->wq_ctrl.buf,
1377 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1385 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1387 struct mlx5e_channel *c = rq->channel;
1403 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1415 mlx5e_disable_rq(struct mlx5e_rq *rq)
1417 struct mlx5e_channel *c = rq->channel;
1421 mlx5_core_destroy_rq(mdev, rq->rqn);
1427 struct mlx5e_rq *rq)
1431 err = mlx5e_create_rq(c, param, rq);
1436 MLX5_SET(rqc, param->rqc, cqn, c->rq.cq.mcq.cqn);
1438 err = mlx5e_enable_rq(rq, param);
1442 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1446 c->rq.enabled = 1;
1451 mlx5e_disable_rq(rq);
1453 mlx5e_destroy_rq(rq);
1459 mlx5e_close_rq(struct mlx5e_rq *rq)
1461 mtx_lock(&rq->mtx);
1462 rq->enabled = 0;
1463 callout_stop(&rq->watchdog);
1464 mtx_unlock(&rq->mtx);
1466 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1470 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1473 mlx5e_disable_rq(rq);
1474 mlx5e_close_cq(&rq->cq);
1475 cancel_work_sync(&rq->dim.work);
1476 mlx5e_destroy_rq(rq);
2189 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2191 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2229 callout_drain(&c->rq.watchdog);
2231 mtx_destroy(&c->rq.mtx);
2251 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2262 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2275 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2281 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL);
2293 mlx5e_close_cq(&c->rq.cq);
2305 mlx5e_close_rq(&c->rq);
2311 mlx5e_close_rq_wait(&c->rq);
2495 mlx5e_build_rq_param(priv, &cparam->rq);
2592 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2613 mtx_lock(&rq->mtx);
2614 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2615 mtx_unlock(&rq->mtx);
2618 cancel_work_sync(&rq->dim.work);
2625 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2629 mtx_lock(&rq->mtx);
2630 rq->dim.mode = dim_mode;
2631 rq->dim.state = 0;
2632 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2633 mtx_unlock(&rq->mtx);
2635 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2643 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2654 err = mlx5e_refresh_rq_params(priv, &c->rq);
2840 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2864 MLX5_SET(rqtc, rqtc, rq_num[0], priv->channel[ix].rq.rqn);
4143 struct mlx5e_rq *rq = &ch->rq;
4147 mtx_lock(&rq->mtx);
4148 rq->enabled = 0;
4149 callout_stop(&rq->watchdog);
4150 mtx_unlock(&rq->mtx);
4152 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
4154 mlx5_en_err(rq->ifp,
4158 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
4161 rq->cq.mcq.comp(&rq->cq.mcq, NULL);
4169 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
4171 mlx5_en_err(rq->ifp,
4179 struct mlx5e_rq *rq = &ch->rq;
4183 rq->wq.wqe_ctr = 0;
4184 mlx5_wq_ll_update_db_record(&rq->wq);
4185 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
4187 mlx5_en_err(rq->ifp,
4191 rq->enabled = 1;
4194 rq->cq.mcq.comp(&rq->cq.mcq, NULL);