Lines Matching defs:priv
44 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
368 mlx5e_update_carrier(struct mlx5e_priv *priv)
370 struct mlx5_core_dev *mdev = priv->mdev;
385 priv->media_status_last |= IFM_ACTIVE;
387 priv->media_status_last &= ~IFM_ACTIVE;
388 priv->media_active_last = IFM_ETHER;
389 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
396 priv->media_active_last = IFM_ETHER;
397 if_setbaudrate(priv->ifp, 1);
398 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
415 mlx5_en_err(priv->ifp,
429 mlx5_en_err(priv->ifp,
438 mlx5_en_err(priv->ifp,
447 mlx5_en_err(priv->ifp,
454 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
455 if_setbaudrate(priv->ifp, media_entry.baudrate);
457 if_link_state_change(priv->ifp, LINK_STATE_UP);
463 struct mlx5e_priv *priv = if_getsoftc(dev);
465 ifmr->ifm_status = priv->media_status_last;
466 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last |
467 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
468 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
508 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
510 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
511 priv->params.rx_pauseframe_control,
512 priv->params.tx_pauseframe_control,
513 priv->params.rx_priority_flow_control,
514 priv->params.tx_priority_flow_control));
518 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
522 if (priv->gone != 0) {
524 } else if (priv->params.rx_pauseframe_control ||
525 priv->params.tx_pauseframe_control) {
526 mlx5_en_err(priv->ifp,
530 error = mlx5e_set_port_pause_and_pfc(priv);
538 struct mlx5e_priv *priv = if_getsoftc(dev);
539 struct mlx5_core_dev *mdev = priv->mdev;
548 locked = PRIV_LOCKED(priv);
550 PRIV_LOCK(priv);
552 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
565 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
572 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
587 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
589 if (priv->params.rx_priority_flow_control ||
590 priv->params.tx_priority_flow_control) {
597 priv->params.rx_pauseframe_control =
598 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
599 priv->params.tx_pauseframe_control =
600 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
603 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
608 error = -mlx5e_set_port_pause_and_pfc(priv);
614 PRIV_UNLOCK(priv);
621 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
624 PRIV_LOCK(priv);
625 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
626 mlx5e_update_carrier(priv);
627 PRIV_UNLOCK(priv);
637 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
639 struct mlx5_core_dev *mdev = priv->mdev;
640 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
684 * host endian ones and stored in the "priv->stats.pport" structure.
687 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
689 struct mlx5_core_dev *mdev = priv->mdev;
690 struct mlx5e_pport_stats *s = &priv->stats.pport;
691 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
762 mlx5e_update_pcie_counters(priv);
785 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
790 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
798 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
801 priv->stats.vport.rx_steer_missed_packets =
809 * sysctl interface. Execution is serialized using the priv's global
813 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
815 struct mlx5_core_dev *mdev = priv->mdev;
816 struct mlx5e_vport_stats *s = &priv->stats.vport;
846 for (i = 0; i < priv->params.num_channels; i++) {
847 struct mlx5e_channel *pch = priv->channel + i;
865 for (j = 0; j < priv->num_tc; j++) {
879 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) {
880 struct mlx5e_rl_worker *rlw = priv->rl.workers + j;
882 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) {
917 mlx5e_grp_vnic_env_update_stats(priv);
930 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
931 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
988 mlx5e_update_pport_counters(priv);
991 priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
992 priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
993 priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
994 priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
1000 if (priv->params_ethtool.diag_pci_enable ||
1001 priv->params_ethtool.diag_general_enable) {
1003 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1004 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1006 mlx5_en_err(priv->ifp,
1011 error = mlx5e_fec_update(priv);
1013 mlx5_en_err(priv->ifp,
1018 if (priv->params_ethtool.hw_num_temp != 0) {
1019 error = mlx5e_hw_temperature_update(priv);
1021 mlx5_en_err(priv->ifp,
1030 struct mlx5e_priv *priv;
1032 priv = container_of(work, struct mlx5e_priv, update_stats_work);
1033 PRIV_LOCK(priv);
1034 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1035 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1036 mlx5e_update_stats_locked(priv);
1037 PRIV_UNLOCK(priv);
1043 struct mlx5e_priv *priv = arg;
1045 queue_work(priv->wq, &priv->update_stats_work);
1047 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv);
1051 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1057 queue_work(priv->wq, &priv->update_carrier_work);
1069 struct mlx5e_priv *priv = vpriv;
1071 mtx_lock(&priv->async_events_mtx);
1072 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1073 mlx5e_async_event_sub(priv, event);
1074 mtx_unlock(&priv->async_events_mtx);
1078 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1080 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1084 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1086 mtx_lock(&priv->async_events_mtx);
1087 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1088 mtx_unlock(&priv->async_events_mtx);
1113 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1116 if (priv->clbr_done == 0)
1117 mlx5e_calibration_callout(priv);
1119 callout_reset_sbt_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1122 mlx5e_calibration_callout, priv, C_DIRECT_EXEC);
1133 mlx5e_hw_clock(struct mlx5e_priv *priv)
1138 iseg = priv->mdev->iseg;
1157 struct mlx5e_priv *priv;
1162 priv = arg;
1163 curr = &priv->clbr_points[priv->clbr_curr];
1164 clbr_curr_next = priv->clbr_curr + 1;
1165 if (clbr_curr_next >= nitems(priv->clbr_points))
1167 next = &priv->clbr_points[clbr_curr_next];
1172 next->clbr_hw_curr = mlx5e_hw_clock(priv);
1175 if (priv->clbr_done != 0) {
1176 mlx5_en_err(priv->ifp,
1179 priv->clbr_done = 0;
1190 priv->clbr_curr = clbr_curr_next;
1191 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1193 if (priv->clbr_done < mlx5e_calibration_duration)
1194 priv->clbr_done++;
1195 mlx5e_reset_calibration_callout(priv);
1207 struct mlx5e_priv *priv = c->priv;
1208 struct mlx5_core_dev *mdev = priv->mdev;
1217 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1244 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1250 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1269 wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1273 if (priv->params.rx_cq_moderation_mode < 2) {
1292 rq->ifp = priv->ifp;
1297 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1344 struct mlx5e_priv *priv = c->priv;
1345 struct mlx5_core_dev *mdev = priv->mdev;
1368 if (priv->counter_set_id >= 0)
1369 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1388 struct mlx5e_priv *priv = c->priv;
1389 struct mlx5_core_dev *mdev = priv->mdev;
1418 struct mlx5e_priv *priv = c->priv;
1419 struct mlx5_core_dev *mdev = priv->mdev;
1500 mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1509 drop_rq->channel = priv->channel;
1513 MLX5_SET(cqc, param_cq.cqc, uar_page, priv->mdev->priv.uar->index);
1516 err = mlx5e_open_cq(priv, ¶m_cq, &drop_rq->cq,
1526 MLX5_SET(wq, rqc_wq, pd, priv->pdn);
1530 err = mlx5_wq_ll_create(priv->mdev, ¶m_rq.wq, rqc_wq, &drop_rq->wq,
1595 mlx5_dev_domainset(sq->priv->mdev), M_WAITOK | M_ZERO);
1617 sq->max_inline = sq->priv->params.tx_max_inline;
1618 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1624 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1626 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1636 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1640 for (i = 0; i != priv->num_tc; i++) {
1648 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1653 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1656 for (i = 0; i < priv->params.num_channels; i++)
1657 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1666 struct mlx5e_priv *priv = c->priv;
1667 struct mlx5_core_dev *mdev = priv->mdev;
1689 sq->mkey_be = cpu_to_be32(priv->mr.key);
1690 sq->ifp = priv->ifp;
1691 sq->priv = priv;
1708 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1753 ts_format = mlx5_get_sq_default_ts(sq->priv->mdev);
1776 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1802 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1813 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1824 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1834 err = mlx5e_enable_sq(sq, param, &c->bfreg, c->priv->tisn[tc]);
1909 struct mlx5_core_dev *mdev= sq->priv->mdev;
1915 * caller ensuring the priv's state lock is locked or in case
1940 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1980 mlx5e_create_cq(struct mlx5e_priv *priv,
1986 struct mlx5_core_dev *mdev = priv->mdev;
2018 cq->priv = priv;
2054 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
2061 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out));
2068 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2077 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2081 mlx5e_open_cq(struct mlx5e_priv *priv,
2089 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2119 for (tc = 0; tc < c->priv->num_tc; tc++) {
2121 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2140 for (tc = 0; tc < c->priv->num_tc; tc++)
2151 for (tc = 0; tc < c->priv->num_tc; tc++) {
2171 for (tc = 0; tc < c->priv->num_tc; tc++)
2176 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2180 /* setup priv and channel number */
2181 c->priv = priv;
2185 m_snd_tag_init(&c->tag, c->priv->ifp, &mlx5e_ul_snd_tag_sw);
2216 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2221 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2243 mlx5e_open_channel(struct mlx5e_priv *priv,
2252 for (i = 0; i != priv->num_tc; i++)
2262 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2318 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2322 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2323 MLX5E_SW2MB_MTU(if_getmtu(priv->ifp));
2351 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2358 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2363 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2364 MLX5_SET(wq, wq, pd, priv->pdn);
2370 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2376 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2378 MLX5_SET(wq, wq, pd, priv->pdn);
2384 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2389 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2393 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2399 if (priv->params.hw_lro_en &&
2406 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2419 if (priv->params.cqe_zipping_en) {
2424 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2426 switch (priv->params.rx_cq_moderation_mode) {
2428 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2429 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2433 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2434 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2435 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2441 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2447 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2450 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2459 mlx5e_dim_build_cq_param(priv, param);
2461 mlx5e_build_common_cq_param(priv, param);
2465 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2470 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2471 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2472 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2474 switch (priv->params.tx_cq_moderation_mode) {
2479 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2486 mlx5e_build_common_cq_param(priv, param);
2490 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2495 mlx5e_build_rq_param(priv, &cparam->rq);
2496 mlx5e_build_sq_param(priv, &cparam->sq);
2497 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2498 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2502 mlx5e_open_channels(struct mlx5e_priv *priv)
2510 mlx5e_build_channel_param(priv, cparam);
2511 for (i = 0; i < priv->params.num_channels; i++) {
2512 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2517 if (priv->params_ethtool.irq_cpu_base > -1) {
2524 err = mlx5_vector2eqn(priv->mdev, i,
2531 irq = priv->mdev->priv.msix_arr[nirq].vector;
2532 cpu = (unsigned)(priv->params_ethtool.irq_cpu_base +
2533 i * priv->params_ethtool.irq_cpu_stride) % (unsigned)mp_ncpus;
2545 mlx5e_close_channel(&priv->channel[i]);
2546 mlx5e_close_channel_wait(&priv->channel[i]);
2553 mlx5e_close_channels(struct mlx5e_priv *priv)
2557 for (i = 0; i < priv->params.num_channels; i++)
2558 mlx5e_close_channel(&priv->channel[i]);
2559 for (i = 0; i < priv->params.num_channels; i++)
2560 mlx5e_close_channel_wait(&priv->channel[i]);
2564 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2567 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2570 switch (priv->params.tx_cq_moderation_mode) {
2580 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2581 priv->params.tx_cq_moderation_usec,
2582 priv->params.tx_cq_moderation_pkts,
2586 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2587 priv->params.tx_cq_moderation_usec,
2588 priv->params.tx_cq_moderation_pkts));
2592 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2595 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2600 switch (priv->params.rx_cq_moderation_mode) {
2620 if (priv->params.rx_cq_moderation_mode >= 2) {
2623 mlx5e_get_default_profile(priv, dim_mode, &curr);
2625 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2635 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2636 priv->params.rx_cq_moderation_usec,
2637 priv->params.rx_cq_moderation_pkts,
2643 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2644 priv->params.rx_cq_moderation_usec,
2645 priv->params.rx_cq_moderation_pkts));
2649 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2654 err = mlx5e_refresh_rq_params(priv, &c->rq);
2658 for (i = 0; i != priv->num_tc; i++) {
2659 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2668 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2673 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2676 for (i = 0; i < priv->params.num_channels; i++) {
2679 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2687 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2689 struct mlx5_core_dev *mdev = priv->mdev;
2696 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2698 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2702 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2704 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc], 0);
2708 mlx5e_open_tises(struct mlx5e_priv *priv)
2710 int num_tc = priv->num_tc;
2715 err = mlx5e_open_tis(priv, tc);
2724 mlx5e_close_tis(priv, tc);
2730 mlx5e_close_tises(struct mlx5e_priv *priv)
2732 int num_tc = priv->num_tc;
2736 mlx5e_close_tis(priv, tc);
2740 mlx5e_open_default_rqt(struct mlx5e_priv *priv, u32 *prqtn, int sz)
2758 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2760 err = mlx5_core_create_rqt(priv->mdev, in, inlen, prqtn);
2767 mlx5e_open_rqts(struct mlx5e_priv *priv)
2772 err = mlx5e_open_default_rqt(priv, &priv->rqtn,
2773 1 << priv->params.rx_hash_log_tbl_sz);
2777 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2778 err = mlx5e_open_default_rqt(priv, &priv->channel[i].rqtn, 1);
2786 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0);
2788 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0);
2795 mlx5e_close_rqts(struct mlx5e_priv *priv)
2799 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++)
2800 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0);
2802 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0);
2806 mlx5e_activate_rqt(struct mlx5e_priv *priv)
2815 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2835 ix %= priv->params.num_channels;
2838 ix -= ix % (int)priv->params.channels_rsss;
2840 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2843 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen);
2851 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2859 ix %= priv->params.num_channels;
2862 ix -= ix % (int)priv->params.channels_rsss;
2864 MLX5_SET(rqtc, rqtc, rq_num[0], priv->channel[ix].rq.rqn);
2866 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen);
2877 mlx5e_deactivate_rqt(struct mlx5e_priv *priv)
2886 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2899 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2901 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen);
2909 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2910 MLX5_SET(rqtc, rqtc, rq_num[0], priv->drop_rq.rqn);
2912 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen);
2948 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt, bool inner_vxlan)
2955 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2971 if (priv->params.hw_lro_en) {
2976 (priv->params.lro_wqe_sz -
2980 MLX5_CAP_ETH(priv->mdev,
2996 priv->rqtn);
3123 mlx5e_open_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan)
3125 struct mlx5_core_dev *mdev = priv->mdev;
3137 mlx5e_build_tir_ctx(priv, tirc, tt, inner_vxlan);
3140 &priv->tirn_inner_vxlan[tt] : &priv->tirn[tt]);
3148 mlx5e_close_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan)
3150 mlx5_core_destroy_tir(priv->mdev, inner_vxlan ?
3151 priv->tirn_inner_vxlan[tt] : priv->tirn[tt], 0);
3155 mlx5e_open_tirs(struct mlx5e_priv *priv)
3161 err = mlx5e_open_tir(priv, i / 2, (i % 2) ? true : false);
3170 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false);
3176 mlx5e_close_tirs(struct mlx5e_priv *priv)
3181 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false);
3191 struct mlx5e_priv *priv = if_getsoftc(ifp);
3192 struct mlx5_core_dev *mdev = priv->mdev;
3235 priv->params_ethtool.hw_mtu = hw_mtu;
3240 priv->params_ethtool.hw_mtu_msb = hw_mtu;
3248 struct mlx5e_priv *priv = if_getsoftc(ifp);
3253 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3257 if (rss_getnumbuckets() > priv->params.num_channels) {
3260 rss_getnumbuckets(), priv->params.num_channels);
3263 err = mlx5e_open_tises(priv);
3268 err = mlx5_vport_alloc_q_counter(priv->mdev,
3271 mlx5_en_err(priv->ifp,
3276 priv->counter_set_id = set_id;
3278 err = mlx5e_open_channels(priv);
3284 err = mlx5e_activate_rqt(priv);
3290 set_bit(MLX5E_STATE_OPENED, &priv->state);
3292 mlx5e_update_carrier(priv);
3297 mlx5e_close_channels(priv);
3300 mlx5_vport_dealloc_q_counter(priv->mdev,
3301 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3304 mlx5e_close_tises(priv);
3312 struct mlx5e_priv *priv = arg;
3314 PRIV_LOCK(priv);
3315 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3316 mlx5_en_err(priv->ifp,
3319 mlx5e_open_locked(priv->ifp);
3320 if_setdrvflagbits(priv->ifp, IFF_DRV_RUNNING, 0);
3321 PRIV_UNLOCK(priv);
3327 struct mlx5e_priv *priv = if_getsoftc(ifp);
3330 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3333 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3335 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3337 mlx5e_deactivate_rqt(priv);
3338 mlx5e_close_channels(priv);
3339 mlx5_vport_dealloc_q_counter(priv->mdev,
3340 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3341 mlx5e_close_tises(priv);
3349 struct mlx5e_priv *priv = if_getsoftc(ifp);
3352 /* PRIV_LOCK(priv); XXX not allowed */
3355 retval = priv->stats.vport.rx_packets;
3358 retval = priv->stats.pport.in_range_len_errors +
3359 priv->stats.pport.out_of_range_len +
3360 priv->stats.pport.too_long_errors +
3361 priv->stats.pport.check_seq_err +
3362 priv->stats.pport.alignment_err;
3365 retval = priv->stats.vport.rx_out_of_buffer;
3368 retval = priv->stats.vport.tx_packets;
3371 retval = priv->stats.port_stats_debug.out_discards;
3374 retval = priv->stats.vport.rx_bytes;
3377 retval = priv->stats.vport.tx_bytes;
3380 retval = priv->stats.vport.rx_multicast_packets;
3383 retval = priv->stats.vport.tx_multicast_packets;
3386 retval = priv->stats.vport.tx_queue_dropped;
3389 retval = priv->stats.pport.collisions;
3395 /* PRIV_UNLOCK(priv); XXX not allowed */
3402 struct mlx5e_priv *priv = if_getsoftc(ifp);
3404 queue_work(priv->wq, &priv->set_rx_mode_work);
3455 struct mlx5e_priv *priv;
3470 priv = if_getsoftc(ifp);
3473 if (priv == NULL || priv->gone != 0)
3480 PRIV_LOCK(priv);
3481 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3487 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3502 PRIV_UNLOCK(priv);
3510 PRIV_LOCK(priv);
3513 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3516 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3520 mlx5_set_port_status(priv->mdev,
3522 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3524 mlx5e_update_carrier(priv);
3528 PRIV_UNLOCK(priv);
3538 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3547 PRIV_LOCK(priv);
3553 PRIV_LOCK(priv);
3555 if (!mlx5e_is_tlstx_capable(priv->mdev)) {
3559 if (!mlx5e_is_tlsrx_capable(priv->mdev)) {
3564 if (!mlx5e_is_ipsec_capable(priv->mdev)) {
3568 if (!mlx5e_is_ratelimit_capable(priv->mdev)) {
3639 mlx5e_disable_vlan_filter(priv);
3641 mlx5e_enable_vlan_filter(priv);
3653 mlx5e_del_all_vxlan_rules(priv);
3659 int err = mlx5e_add_all_vxlan_rules(priv);
3675 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3682 if (priv->params.hw_lro_en) {
3683 priv->params.hw_lro_en = false;
3687 if (priv->params.hw_lro_en == false &&
3688 priv->params_ethtool.hw_lro != 0) {
3689 priv->params.hw_lro_en = true;
3701 if (priv->clbr_done == 0)
3702 mlx5e_reset_calibration_callout(priv);
3704 callout_drain(&priv->tstmp_clbr);
3705 priv->clbr_done = 0;
3719 ipsec_accel_on_ifdown(priv->ifp);
3726 PRIV_UNLOCK(priv);
3745 PRIV_LOCK(priv);
3747 error = mlx5_query_module_num(priv->mdev, &module_num);
3755 module_status = mlx5_query_module_status(priv->mdev, module_num);
3780 error = mlx5_query_eeprom(priv->mdev,
3792 error = mlx5_query_eeprom(priv->mdev,
3807 PRIV_UNLOCK(priv);
3812 PRIV_LOCK(priv);
3813 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL,
3815 PRIV_UNLOCK(priv);
3886 struct mlx5e_priv *priv,
3895 priv->params.log_sq_size =
3897 priv->params.log_rq_size =
3899 priv->params.rx_cq_moderation_usec =
3903 priv->params.rx_cq_moderation_mode =
3905 priv->params.rx_cq_moderation_pkts =
3907 priv->params.tx_cq_moderation_usec =
3909 priv->params.tx_cq_moderation_pkts =
3911 priv->params.rx_hash_log_tbl_sz =
3916 priv->params.num_tc = 1;
3917 priv->params.default_vlan_prio = 0;
3918 priv->counter_set_id = -1;
3919 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3921 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3929 priv->params.hw_lro_en = false;
3930 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3938 priv->params.cqe_zipping_en = false;
3940 priv->mdev = mdev;
3941 priv->params.num_channels = num_comp_vectors;
3942 priv->params.channels_rsss = 1;
3943 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3944 priv->queue_mapping_channel_mask =
3946 priv->num_tc = priv->params.num_tc;
3947 priv->default_vlan_prio = priv->params.default_vlan_prio;
3949 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3950 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3951 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3969 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3972 if_t ifp = priv->ifp;
3973 struct mlx5_core_dev *mdev = priv->mdev;
4013 mlx5e_priv_static_init(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev,
4019 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
4020 sx_init(&priv->state_lock, "mlx5state");
4021 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
4022 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
4024 mlx5e_chan_static_init(priv, &priv->channel[x], x);
4027 err = mlx5_alloc_bfreg(mdev, &priv->channel[x].bfreg, false, false);
4035 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg);
4038 mlx5e_chan_static_destroy(&priv->channel[x]);
4039 callout_drain(&priv->watchdog);
4040 mtx_destroy(&priv->async_events_mtx);
4041 sx_destroy(&priv->state_lock);
4046 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev,
4052 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg);
4054 mlx5e_chan_static_destroy(&priv->channel[x]);
4055 callout_drain(&priv->watchdog);
4056 mtx_destroy(&priv->async_events_mtx);
4057 sx_destroy(&priv->state_lock);
4071 struct mlx5e_priv *priv = arg1;
4074 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
4075 fw_rev_sub(priv->mdev));
4085 for (i = 0; i < ch->priv->num_tc; i++)
4136 for (i = 0; i < ch->priv->num_tc; i++)
4199 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
4203 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
4206 for (i = 0; i < priv->params.num_channels; i++) {
4208 mlx5e_disable_tx_dma(&priv->channel[i]);
4210 mlx5e_enable_tx_dma(&priv->channel[i]);
4215 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
4219 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
4222 for (i = 0; i < priv->params.num_channels; i++) {
4224 mlx5e_disable_rx_dma(&priv->channel[i]);
4226 mlx5e_enable_rx_dma(&priv->channel[i]);
4231 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
4233 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
4235 priv, 0, sysctl_firmware, "A", "HCA firmware version");
4237 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
4238 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
4245 struct mlx5e_priv *priv = arg1;
4251 PRIV_LOCK(priv);
4253 tx_pfc = priv->params.tx_priority_flow_control;
4265 priv->params.tx_priority_flow_control = 0;
4273 priv->params.tx_priority_flow_control |= (temp[i] << i);
4277 if (tx_pfc != priv->params.tx_priority_flow_control)
4278 err = -mlx5e_set_port_pfc(priv);
4281 priv->params.tx_priority_flow_control= tx_pfc;
4282 PRIV_UNLOCK(priv);
4290 struct mlx5e_priv *priv = arg1;
4296 PRIV_LOCK(priv);
4298 rx_pfc = priv->params.rx_priority_flow_control;
4310 priv->params.rx_priority_flow_control = 0;
4318 priv->params.rx_priority_flow_control |= (temp[i] << i);
4322 if (rx_pfc != priv->params.rx_priority_flow_control) {
4323 err = -mlx5e_set_port_pfc(priv);
4324 if (err == 0 && priv->sw_is_port_buf_owner)
4325 err = mlx5e_update_buf_lossy(priv);
4329 priv->params.rx_priority_flow_control= rx_pfc;
4330 PRIV_UNLOCK(priv);
4336 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
4341 priv->params.tx_pauseframe_control = 1;
4342 priv->params.rx_pauseframe_control = 1;
4345 priv->params.tx_priority_flow_control = 0;
4346 priv->params.rx_priority_flow_control = 0;
4349 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4351 &priv->params.tx_pauseframe_control, 0,
4354 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4356 &priv->params.rx_pauseframe_control, 0,
4360 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4362 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
4365 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4367 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
4370 PRIV_LOCK(priv);
4373 priv->params.tx_pauseframe_control =
4374 priv->params.tx_pauseframe_control ? 1 : 0;
4375 priv->params.rx_pauseframe_control =
4376 priv->params.rx_pauseframe_control ? 1 : 0;
4379 error = mlx5e_set_port_pause_and_pfc(priv);
4381 mlx5_en_err(priv->ifp,
4383 priv->params.rx_priority_flow_control = 0;
4384 priv->params.tx_priority_flow_control = 0;
4387 (void) mlx5e_set_port_pause_and_pfc(priv);
4389 PRIV_UNLOCK(priv);
4397 struct mlx5e_priv *priv;
4400 priv = if_getsoftc(ifp);
4402 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4406 u32 ch = priv->params.num_channels;
4421 * reference the priv.
4423 pch = priv->channel + ch;
4527 mlx5e_ifm_add(struct mlx5e_priv *priv, int type)
4529 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL);
4530 ifmedia_add(&priv->media, type | IFM_ETHER |
4532 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL);
4533 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL);
4534 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL);
4535 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4537 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4539 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4547 struct mlx5e_priv *priv;
4550 int ncv = mdev->priv.eq_table.num_comp_vectors;
4565 * Try to allocate the priv and make room for worst-case
4568 priv = malloc_domainset(sizeof(*priv) +
4569 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4572 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4574 if (mlx5e_priv_static_init(priv, mdev, mdev->priv.eq_table.num_comp_vectors)) {
4579 if_setsoftc(ifp, priv);
4642 sysctl_ctx_init(&priv->sysctl_ctx);
4643 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4646 if (priv->sysctl_ifnet == NULL) {
4651 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4654 if (priv->sysctl_ifnet == NULL) {
4661 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4664 if (priv->sysctl_hw == NULL) {
4669 err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4676 priv->wq = mdev->priv.health.wq_watchdog;
4678 err = mlx5_core_alloc_pd(mdev, &priv->pdn, 0);
4683 err = mlx5_alloc_transport_domain(mdev, &priv->tdn, 0);
4689 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4694 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4697 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4703 err = mlx5e_rl_init(priv);
4709 err = mlx5e_tls_init(priv);
4716 err = mlx5e_ipsec_init(priv);
4723 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4729 err = mlx5e_open_rqts(priv);
4735 err = mlx5e_open_tirs(priv);
4741 err = mlx5e_open_flow_tables(priv);
4747 err = mlx5e_tls_rx_init(priv);
4757 priv->media_status_last = IFM_AVALID;
4758 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX;
4761 mlx5e_setup_pauseframes(priv);
4775 ifmedia_init(&priv->media, IFM_IMASK,
4797 mlx5e_ifm_add(priv, media_entry.subtype);
4813 mlx5e_ifm_add(priv, media_entry.subtype);
4817 mlx5e_ifm_add(priv, IFM_10G_LR);
4822 mlx5e_ifm_add(priv, IFM_AUTO);
4825 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4833 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4834 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4835 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4836 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4839 priv->vxlan_start = EVENTHANDLER_REGISTER(vxlan_start,
4840 mlx5e_vxlan_start, priv, EVENTHANDLER_PRI_ANY);
4841 priv->vxlan_stop = EVENTHANDLER_REGISTER(vxlan_stop,
4842 mlx5e_vxlan_stop, priv, EVENTHANDLER_PRI_ANY);
4847 mlx5e_enable_async_events(priv);
4849 mlx5e_add_hw_stats(priv);
4851 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4853 priv->stats.vport.arg);
4855 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4857 priv->stats.pport.arg);
4859 mlx5e_create_ethtool(priv);
4861 mtx_lock(&priv->async_events_mtx);
4862 mlx5e_update_stats(priv);
4863 mtx_unlock(&priv->async_events_mtx);
4865 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4867 &priv->clbr_done, 0,
4869 callout_init(&priv->tstmp_clbr, 1);
4871 priv->cclk = (uint64_t)MLX5_CAP_GEN(mdev, device_frequency_khz) * 1000ULL;
4872 mlx5e_reset_calibration_callout(priv);
4878 priv->pfil = pfil_head_register(&pa);
4880 PRIV_LOCK(priv);
4881 err = mlx5e_open_flow_rules(priv);
4886 PRIV_UNLOCK(priv);
4888 return (priv);
4891 mlx5e_close_flow_tables(priv);
4894 mlx5e_close_tirs(priv);
4897 mlx5e_close_rqts(priv);
4900 mlx5e_close_drop_rq(&priv->drop_rq);
4903 mlx5e_ipsec_cleanup(priv);
4906 mlx5e_tls_cleanup(priv);
4909 mlx5e_rl_cleanup(priv);
4912 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4915 mlx5_dealloc_transport_domain(mdev, priv->tdn, 0);
4918 mlx5_core_dealloc_pd(mdev, priv->pdn, 0);
4921 flush_workqueue(priv->wq);
4924 sysctl_ctx_free(&priv->sysctl_ctx);
4925 if (priv->sysctl_debug)
4926 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4927 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors);
4931 free(priv, M_MLX5EN);
4938 struct mlx5e_priv *priv = vpriv;
4939 if_t ifp = priv->ifp;
4942 priv->gone = 1;
4958 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4959 mlx5_en_err(priv->ifp,
4967 while (priv->tls.init != 0 &&
4968 uma_zone_get_cur(priv->tls.zone) != 0) {
4969 mlx5_en_err(priv->ifp,
4975 while (priv->tls_rx.init != 0 &&
4976 uma_zone_get_cur(priv->tls_rx.zone) != 0) {
4977 mlx5_en_err(priv->ifp,
4983 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
4986 callout_drain(&priv->watchdog);
4988 callout_drain(&priv->tstmp_clbr);
4990 if (priv->vlan_attach != NULL)
4991 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4992 if (priv->vlan_detach != NULL)
4993 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4994 if (priv->vxlan_start != NULL)
4995 EVENTHANDLER_DEREGISTER(vxlan_start, priv->vxlan_start);
4996 if (priv->vxlan_stop != NULL)
4997 EVENTHANDLER_DEREGISTER(vxlan_stop, priv->vxlan_stop);
5000 PRIV_LOCK(priv);
5002 mlx5e_close_flow_rules(priv);
5003 PRIV_UNLOCK(priv);
5006 if (priv->pfil != NULL) {
5007 pfil_head_unregister(priv->pfil);
5008 priv->pfil = NULL;
5012 ifmedia_removeall(&priv->media);
5015 mlx5e_tls_rx_cleanup(priv);
5017 ipsec_accel_on_ifdown(priv->ifp);
5019 mlx5e_close_flow_tables(priv);
5020 mlx5e_close_tirs(priv);
5021 mlx5e_close_rqts(priv);
5022 mlx5e_close_drop_rq(&priv->drop_rq);
5023 mlx5e_ipsec_cleanup(priv);
5024 mlx5e_tls_cleanup(priv);
5025 mlx5e_rl_cleanup(priv);
5028 sysctl_ctx_free(&priv->stats.vport.ctx);
5029 sysctl_ctx_free(&priv->stats.pport.ctx);
5030 if (priv->sysctl_debug)
5031 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
5032 sysctl_ctx_free(&priv->sysctl_ctx);
5034 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
5035 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn, 0);
5036 mlx5_core_dealloc_pd(priv->mdev, priv->pdn, 0);
5037 mlx5e_disable_async_events(priv);
5038 flush_workqueue(priv->wq);
5039 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors);
5041 free(priv, M_MLX5EN);
5048 struct mlx5e_priv *priv = if_getsoftc(dev);
5050 PRIV_LOCK(priv);
5051 *nrxr = priv->params.num_channels;
5054 PRIV_UNLOCK(priv);
5065 struct mlx5e_priv *priv = if_getsoftc(dev);
5070 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0)
5073 sq = &priv->channel[0].sq[0];
5095 struct mlx5e_priv *priv = if_getsoftc(dev);
5098 (priv->media_status_last & IFM_ACTIVE) == 0)
5101 mlx5_poll_interrupts(priv->mdev);
5110 struct mlx5e_priv *priv = vpriv;
5112 return (priv->ifp);