Lines Matching defs:_channel

91 #define MGB_FCT_ENBL(_channel)		(1 << (28 + (_channel)))
92 #define MGB_FCT_DSBL(_channel)		(1 << (24 + (_channel)))
93 #define MGB_FCT_RESET(_channel)		(1 << (20 + (_channel)))
134 #define MGB_DMA_REG(reg, _channel)	((reg) | ((_channel) << 6))
140 #define MGB_DMA_TX_CONFIG0(_channel)	MGB_DMA_REG(0x0D40, _channel)
141 #define MGB_DMA_TX_CONFIG1(_channel)	MGB_DMA_REG(0x0D44, _channel)
142 #define MGB_DMA_TX_BASE_H(_channel)	MGB_DMA_REG(0x0D48, _channel)
143 #define MGB_DMA_TX_BASE_L(_channel)	MGB_DMA_REG(0x0D4C, _channel)
144 #define MGB_DMA_TX_HEAD_WB_H(_channel)	MGB_DMA_REG(0x0D50, _channel) /* head Writeback */
145 #define MGB_DMA_TX_HEAD_WB_L(_channel)	MGB_DMA_REG(0x0D54, _channel)
146 #define MGB_DMA_TX_HEAD(_channel)	MGB_DMA_REG(0x0D58, _channel)
147 #define MGB_DMA_TX_TAIL(_channel)	MGB_DMA_REG(0x0D5C, _channel)
149 #define MGB_DMA_RX_CONFIG0(_channel)	MGB_DMA_REG(0x0C40, _channel)
150 #define MGB_DMA_RX_CONFIG1(_channel)	MGB_DMA_REG(0x0C44, _channel)
151 #define MGB_DMA_RX_BASE_H(_channel)	MGB_DMA_REG(0x0C48, _channel)
152 #define MGB_DMA_RX_BASE_L(_channel)	MGB_DMA_REG(0x0C4C, _channel)
153 #define MGB_DMA_RX_HEAD_WB_H(_channel)	MGB_DMA_REG(0x0C50, _channel) /* head Writeback */
154 #define MGB_DMA_RX_HEAD_WB_L(_channel)	MGB_DMA_REG(0x0C54, _channel)
155 #define MGB_DMA_RX_HEAD(_channel)	MGB_DMA_REG(0x0C58, _channel)
156 #define MGB_DMA_RX_TAIL(_channel)	MGB_DMA_REG(0x0C5C, _channel)
201 #define MGB_INTR_STS_RX(_channel)	(1 << (24 + (_channel)))
203 #define MGB_INTR_STS_TX(_channel)	(1 << (16 + (_channel)))