Lines Matching +full:rgmii +full:- +full:compliant
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 * LAN7430 https://www.microchip.com/en-us/product/LAN7430
36 * - Integrated IEEE 802.3 compliant PHY
37 * LAN7431 https://www.microchip.com/en-us/product/LAN7431
38 * - RGMII Interface
43 * ----------------------
47 * - Multiple (up to 4) RX queues support
48 * - Just needs to remove asserts and malloc multiple `rx_ring_data`
50 * - RX/TX Checksum Offloading support
51 * - VLAN support
52 * - Receive Packet Filtering (Multicast Perfect/Hash Address) support
53 * - Wake on LAN (WoL) support
54 * - TX LSO support
55 * - Receive Side Scaling (RSS) support
56 * - Debugging Capabilities:
57 * - Could include MAC statistics and
341 sc->ctx = ctx;
342 sc->dev = iflib_get_dev(ctx);
346 scctx->isc_txrx = &mgb_txrx;
347 scctx->isc_tx_nsegments = MGB_DMA_MAXSEGS;
349 scctx->isc_txqsizes[0] = sizeof(struct mgb_ring_desc) *
350 scctx->isc_ntxd[0];
351 scctx->isc_rxqsizes[0] = sizeof(struct mgb_ring_desc) *
352 scctx->isc_nrxd[0];
355 scctx->isc_txqsizes[1] = sizeof(uint32_t) * scctx->isc_ntxd[1];
356 scctx->isc_rxqsizes[1] = sizeof(uint32_t) * scctx->isc_nrxd[1];
359 scctx->isc_nrxqsets = 1;
360 scctx->isc_ntxqsets = 1;
362 /* scctx->isc_tx_csum_flags = (CSUM_TCP | CSUM_UDP) |
364 scctx->isc_tx_csum_flags = 0;
365 scctx->isc_capabilities = scctx->isc_capenable = 0;
376 scctx->isc_capabilities |= IFCAP_LRO | IFCAP_VLAN_HWFILTER;
382 device_printf(sc->dev,
393 device_printf(sc->dev,
398 switch (pci_get_device(sc->dev)) {
409 error = mii_attach(sc->dev, &sc->miibus, iflib_get_ifp(ctx),
413 device_printf(sc->dev, "Failed to attach MII interface\n");
417 miid = device_get_softc(sc->miibus);
418 scctx->isc_media = &miid->mii_media;
420 scctx->isc_msix_bar = pci_msix_table_bar(sc->dev);
422 rid = pci_msix_pba_bar(sc->dev);
423 if (rid != scctx->isc_msix_bar) {
424 sc->pba = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
426 if (sc->pba == NULL) {
428 device_printf(sc->dev, "Failed to setup PBA BAR\n");
464 device_printf(sc->dev, "Interrupt test: %s\n",
482 iflib_irq_free(ctx, &sc->rx_irq);
483 iflib_irq_free(ctx, &sc->admin_irq);
485 bus_generic_detach(sc->dev);
487 if (sc->pba != NULL)
488 error = bus_release_resource(sc->dev, SYS_RES_MEMORY,
489 rman_get_rid(sc->pba), sc->pba);
490 sc->pba = NULL;
508 miid = device_get_softc(sc->miibus);
509 LIST_FOREACH(miisc, &miid->mii_phys, mii_list)
525 miid = device_get_softc(sc->miibus);
530 ifmr->ifm_active = miid->mii_media_active;
531 ifmr->ifm_status = miid->mii_media_status;
544 rdata = &sc->tx_ring_data;
548 rdata->ring = (struct mgb_ring_desc *) vaddrs[q * ntxqs + 0];
549 rdata->ring_bus_addr = paddrs[q * ntxqs + 0];
552 rdata->head_wb = (uint32_t *) vaddrs[q * ntxqs + 1];
553 rdata->head_wb_bus_addr = paddrs[q * ntxqs + 1];
568 rdata = &sc->rx_ring_data;
572 rdata->ring = (struct mgb_ring_desc *) vaddrs[q * nrxqs + 0];
573 rdata->ring_bus_addr = paddrs[q * nrxqs + 0];
576 rdata->head_wb = (uint32_t *) vaddrs[q * nrxqs + 1];
577 rdata->head_wb_bus_addr = paddrs[q * nrxqs + 1];
589 memset(&sc->rx_ring_data, 0, sizeof(struct mgb_ring_data));
590 memset(&sc->tx_ring_data, 0, sizeof(struct mgb_ring_data));
601 miid = device_get_softc(sc->miibus);
602 device_printf(sc->dev, "running init ...\n");
616 device_printf(sc->dev, "%s: mii_mediachg returned %d", __func__,
630 device_printf(sc->dev, "0x%04x: 0x%08x\n", i,
679 device_printf(sc->dev, "%s at offset 0x%04x = 0x%08x\n",
680 stat_names[i - 1], stats[i - 1],
681 CSR_READ_REG(sc, stats[i - 1]));
684 device_printf(sc->dev, "ring[%d].data0=0x%08x\n"
688 i, sc->tx_ring_data.ring[i].ctl,
689 i, sc->tx_ring_data.ring[i].addr.low,
690 i, sc->tx_ring_data.ring[i].addr.high,
691 i, sc->tx_ring_data.ring[i].sts);
692 device_printf(sc->dev, "==== DUMP_TX_DMA_RAM ====\n");
702 device_printf(sc->dev, "DMAC_TX_RAM_0[%u]=%08x\n", i,
719 for (i = 0; i < scctx->isc_nrxqsets; i++) {
723 for (i = 0; i < scctx->isc_ntxqsets; i++) {
735 iflib_admin_intr_deferred(sc->ctx);
748 scctx = iflib_get_softc_ctx(sc->ctx);
754 for (qidx = 0; qidx < scctx->isc_nrxqsets; qidx++) {
773 scctx = iflib_get_softc_ctx(sc->ctx);
783 sc->isr_test_flag = true;
788 for (qidx = 0; qidx < scctx->isc_nrxqsets; qidx++) {
790 iflib_rx_intr_deferred(sc->ctx, qidx);
797 for (qidx = 0; qidx < scctx->isc_ntxqsets; qidx++) {
804 iflib_tx_intr_deferred(sc->ctx, qidx);
824 KASSERT(scctx->isc_nrxqsets == 1 && scctx->isc_ntxqsets == 1,
833 error = iflib_irq_alloc_generic(ctx, &sc->admin_irq, vectorid + 1,
836 device_printf(sc->dev,
841 for (i = 0; i < scctx->isc_nrxqsets; i++) {
844 error = iflib_irq_alloc_generic(ctx, &sc->rx_irq, vectorid + 1,
847 device_printf(sc->dev,
856 for (i = 0; i < scctx->isc_ntxqsets; i++) {
877 for (i = 0; i < scctx->isc_nrxqsets; i++) {
940 sc->isr_test_flag = false;
946 if (sc->isr_test_flag)
950 if (sc->isr_test_flag)
955 return (sc->isr_test_flag);
968 KASSERT(ipi->ipi_qsidx == 0,
969 ("tried to refill TX Channel %d.\n", ipi->ipi_qsidx));
971 rdata = &sc->tx_ring_data;
973 pidx = ipi->ipi_pidx;
974 segs = ipi->ipi_segs;
975 nsegs = ipi->ipi_nsegs;
980 txd = &rdata->ring[pidx];
981 txd->ctl = htole32(
990 txd->addr.low = htole32(CSR_TRANSLATE_ADDR_LOW32(
992 txd->addr.high = htole32(CSR_TRANSLATE_ADDR_HIGH32(
994 txd->sts = htole32(
998 ipi->ipi_new_pidx = pidx;
1010 rdata = &sc->tx_ring_data;
1012 if (rdata->last_tail != pidx) {
1013 rdata->last_tail = pidx;
1014 CSR_WRITE_REG(sc, MGB_DMA_TX_TAIL(txqid), rdata->last_tail);
1031 * - vmx driver
1036 rdata = &sc->tx_ring_data;
1038 while (*(rdata->head_wb) != rdata->last_head) {
1042 txd = &rdata->ring[rdata->last_head];
1044 rdata->last_head = MGB_NEXT_RING_IDX(rdata->last_head);
1062 rdata = &sc->rx_ring_data;
1063 for (; idx != *(rdata->head_wb); idx = MGB_NEXT_RING_IDX(idx)) {
1080 KASSERT(ri->iri_qsidx == 0,
1081 ("tried to check availability in RX Channel %d\n", ri->iri_qsidx));
1084 rdata = &sc->rx_ring_data;
1086 while (*(rdata->head_wb) != rdata->last_head) {
1088 rxd = rdata->ring[rdata->last_head];
1095 device_printf(sc->dev,
1101 device_printf(sc->dev,
1104 device_printf(sc->dev, "Tried to read descriptor ... that it FS is not set.\n");
1107 /* XXX: Multi-packet support */
1109 device_printf(sc->dev,
1111 "found that LS is not set. (Multi-buffer packets not yet supported)\n");
1114 ri->iri_frags[0].irf_flid = 0;
1115 ri->iri_frags[0].irf_idx = rdata->last_head;
1116 ri->iri_frags[0].irf_len = MGB_DESC_GET_FRAME_LEN(&rxd);
1117 total_len += ri->iri_frags[0].irf_len;
1119 rdata->last_head = MGB_NEXT_RING_IDX(rdata->last_head);
1122 ri->iri_nfrags = 1;
1123 ri->iri_len = total_len;
1139 count = iru->iru_count;
1140 len = iru->iru_buf_size;
1141 idxs = iru->iru_idxs;
1142 paddrs = iru->iru_paddrs;
1143 KASSERT(iru->iru_qsidx == 0,
1144 ("tried to refill RX Channel %d.\n", iru->iru_qsidx));
1147 rdata = &sc->rx_ring_data;
1150 idx = idxs[--count];
1151 rxd = &rdata->ring[idx];
1153 rxd->sts = 0;
1154 rxd->addr.low =
1156 rxd->addr.high =
1158 rxd->ctl = htole32(MGB_DESC_CTL_OWN |
1177 sc->rx_ring_data.last_tail = MGB_PREV_RING_IDX(pidx);
1178 CSR_WRITE_REG(sc, MGB_DMA_RX_TAIL(rxqid), sc->rx_ring_data.last_tail);
1193 device_printf(sc->dev, "ID check failed.\n");
1204 pci_enable_busmaster(sc->dev);
1205 sc->regs = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1207 if (sc->regs == NULL)
1218 if (sc->regs != NULL)
1219 error = bus_release_resource(sc->dev, SYS_RES_MEMORY,
1220 rman_get_rid(sc->regs), sc->regs);
1221 sc->regs = NULL;
1222 pci_disable_busmaster(sc->dev);
1232 scctx = iflib_get_softc_ctx(sc->ctx);
1234 for (ch = 0; ch < scctx->isc_nrxqsets; ch++)
1238 for (ch = 0; ch < scctx->isc_nrxqsets; ch++)
1252 rdata = &sc->rx_ring_data;
1258 if (rdata->ring_bus_addr == 0) {
1259 device_printf(sc->dev, "Invalid ring bus addr.\n");
1264 CSR_TRANSLATE_ADDR_HIGH32(rdata->ring_bus_addr));
1266 CSR_TRANSLATE_ADDR_LOW32(rdata->ring_bus_addr));
1269 if (rdata->head_wb_bus_addr == 0) {
1270 device_printf(sc->dev, "Invalid head wb bus addr.\n");
1274 CSR_TRANSLATE_ADDR_HIGH32(rdata->head_wb_bus_addr));
1276 CSR_TRANSLATE_ADDR_LOW32(rdata->head_wb_bus_addr));
1291 rdata->last_head = CSR_READ_REG(sc, MGB_DMA_RX_HEAD(channel));
1295 device_printf(sc->dev, "Failed to reset RX FCT.\n");
1300 device_printf(sc->dev, "Failed to enable RX FCT.\n");
1305 device_printf(sc->dev, "Failed to start RX DMAC.\n");
1316 rdata = &sc->tx_ring_data;
1318 device_printf(sc->dev, "Failed to reset TX FCT.\n");
1323 device_printf(sc->dev, "Failed to enable TX FCT.\n");
1328 device_printf(sc->dev, "Failed to reset TX DMAC.\n");
1335 if (rdata->ring_bus_addr == 0) {
1336 device_printf(sc->dev, "Invalid ring bus addr.\n");
1340 CSR_TRANSLATE_ADDR_HIGH32(rdata->ring_bus_addr));
1342 CSR_TRANSLATE_ADDR_LOW32(rdata->ring_bus_addr));
1355 if (rdata->head_wb_bus_addr == 0) {
1356 device_printf(sc->dev, "Invalid head wb bus addr.\n");
1360 CSR_TRANSLATE_ADDR_HIGH32(rdata->head_wb_bus_addr));
1362 CSR_TRANSLATE_ADDR_LOW32(rdata->head_wb_bus_addr));
1364 rdata->last_head = CSR_READ_REG(sc, MGB_DMA_TX_HEAD(channel));
1365 KASSERT(rdata->last_head == 0, ("MGB_DMA_TX_HEAD was not reset.\n"));
1366 rdata->last_tail = 0;
1367 CSR_WRITE_REG(sc, MGB_DMA_TX_TAIL(channel), rdata->last_tail);
1371 device_printf(sc->dev, "Failed to start TX DMAC.\n");
1535 CSR_READ_REG_BYTES(sc, MGB_MAC_ADDR_BASE_L, &dest->octet[0], 4);
1536 CSR_READ_REG_BYTES(sc, MGB_MAC_ADDR_BASE_H, &dest->octet[4], 2);
1590 miid = device_get_softc(sc->miibus);
1592 sc->baudrate = ifmedia_baudrate(miid->mii_media_active);
1593 iflib_link_state_change(sc->ctx, sc->link_state, sc->baudrate);
1604 miid = device_get_softc(sc->miibus);
1606 if (miid->mii_media_status & IFM_AVALID) {
1607 if (miid->mii_media_status & IFM_ACTIVE)
1613 sc->link_state = link_state;
1614 iflib_link_state_change(sc->ctx, sc->link_state, sc->baudrate);