Lines Matching defs:abilities

2838 	struct i40e_aq_get_phy_abilities_resp abilities;
2844 	    FALSE, FALSE, &abilities, NULL);
2859 	config.phy_type = abilities.phy_type;
2860 	config.phy_type_ext = abilities.phy_type_ext;
2861 	config.abilities = abilities.abilities
2863 	config.eee_capability = abilities.eee_capability;
2864 	config.eeer = abilities.eeer_val;
2865 	config.low_power_ctrl = abilities.d3_lpan;
2866 	config.fec_config = abilities.fec_cfg_curr_mod_ext_info
3226 	struct i40e_aq_get_phy_abilities_resp abilities;
3233 	    FALSE, TRUE, &abilities, NULL);
3242 	phy_type = abilities.phy_type;
3243 	phy_type_ext = abilities.phy_type_ext;
3247 	    FALSE, FALSE, &abilities, NULL);
3258 	config.link_speed = abilities.link_speed;
3259 	config.abilities = abilities.abilities;
3260 	config.eee_capability = abilities.eee_capability;
3261 	config.eeer = abilities.eeer_val;
3262 	config.low_power_ctrl = abilities.d3_lpan;
3263 	config.fec_config = abilities.fec_cfg_curr_mod_ext_info
3268 	config.abilities &= ~(I40E_AQ_PHY_FLAG_PAUSE_TX |
3273 		config.abilities |= I40E_AQ_PHY_FLAG_PAUSE_TX |
3277 		config.abilities |= I40E_AQ_PHY_FLAG_PAUSE_RX;
3280 		config.abilities |= I40E_AQ_PHY_FLAG_PAUSE_TX;
3458 	struct i40e_aq_get_phy_abilities_resp abilities;
3469 	    FALSE, arg2 != 0, &abilities, NULL);
3481 	    abilities.phy_type);
3483 	if (abilities.phy_type != 0) {
3486 			if ((1 << i) & abilities.phy_type)
3492 	    abilities.phy_type_ext);
3494 	if (abilities.phy_type_ext != 0) {
3497 			if ((1 << i) & abilities.phy_type_ext)
3503 	sbuf_printf(buf, "\nSpeed    : %02x", abilities.link_speed);
3504 	if (abilities.link_speed != 0) {
3508 			link_speed = (1 << i) & abilities.link_speed;
3526 	    abilities.abilities, abilities.eee_capability,
3527 	    abilities.eeer_val, abilities.d3_lpan,
3528 	    abilities.phy_id[0], abilities.phy_id[1],
3529 	    abilities.phy_id[2], abilities.phy_id[3],
3530 	    abilities.module_type[0], abilities.module_type[1],
3531 	    abilities.module_type[2], (abilities.fec_cfg_curr_mod_ext_info & 0xe0) >> 5,
3532 	    abilities.fec_cfg_curr_mod_ext_info & 0x1F,
3533 	    abilities.ext_comp_code);
4336 ixl_get_fec_config(struct ixl_pf *pf, struct i40e_aq_get_phy_abilities_resp *abilities,
4347 	    FALSE, FALSE, abilities, NULL);
4356 	*is_set = !!(abilities->fec_cfg_curr_mod_ext_info & bit_pos);
4361 ixl_set_fec_config(struct ixl_pf *pf, struct i40e_aq_get_phy_abilities_resp *abilities,
4371 	config.fec_config = abilities->fec_cfg_curr_mod_ext_info & ~(bit_pos);
4374 	if (config.fec_config != abilities->fec_cfg_curr_mod_ext_info) {
4375 		config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
4376 		config.phy_type = abilities->phy_type;
4377 		config.phy_type_ext = abilities->phy_type_ext;
4378 		config.link_speed = abilities->link_speed;
4379 		config.eee_capability = abilities->eee_capability;
4380 		config.eeer = abilities->eeer_val;
4381 		config.low_power_ctrl = abilities->d3_lpan;
4402 	struct i40e_aq_get_phy_abilities_resp abilities;
4403 	error = ixl_get_fec_config(pf, &abilities, I40E_AQ_ENABLE_FEC_KR, &mode);
4411 	return ixl_set_fec_config(pf, &abilities, I40E_AQ_SET_FEC_ABILITY_KR, !!(mode));
4420 	struct i40e_aq_get_phy_abilities_resp abilities;
4421 	error = ixl_get_fec_config(pf, &abilities, I40E_AQ_ENABLE_FEC_RS, &mode);
4429 	return ixl_set_fec_config(pf, &abilities, I40E_AQ_SET_FEC_ABILITY_RS, !!(mode));
4438 	struct i40e_aq_get_phy_abilities_resp abilities;
4439 	error = ixl_get_fec_config(pf, &abilities, I40E_AQ_REQUEST_FEC_KR, &mode);
4447 	return ixl_set_fec_config(pf, &abilities, I40E_AQ_SET_FEC_REQUEST_KR, !!(mode));
4456 	struct i40e_aq_get_phy_abilities_resp abilities;
4457 	error = ixl_get_fec_config(pf, &abilities, I40E_AQ_REQUEST_FEC_RS, &mode);
4465 	return ixl_set_fec_config(pf, &abilities, I40E_AQ_SET_FEC_REQUEST_RS, !!(mode));
4474 	struct i40e_aq_get_phy_abilities_resp abilities;
4475 	error = ixl_get_fec_config(pf, &abilities, I40E_AQ_ENABLE_FEC_AUTO, &mode);
4483 	return ixl_set_fec_config(pf, &abilities, I40E_AQ_SET_FEC_AUTO, !!(mode));