92 	u64 time_left = 0;  in i40e_acquire_nvm()
100 					    0, &time_left, NULL);  in i40e_acquire_nvm()
121 							access, 0, &time_left,  in i40e_acquire_nvm()
130 			hw->nvm.hw_semaphore_timeout = 0;  in i40e_acquire_nvm()
151 	u32 total_delay = 0;  in i40e_release_nvm()
158 	ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);  in i40e_release_nvm()
167 						I40E_NVM_RESOURCE_ID, 0, NULL);  in i40e_release_nvm()
186 	for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {  in i40e_poll_sr_srctl_done_bit()
202  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
242 			   "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",  in i40e_read_nvm_word_srctl()
270 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_read_nvm_aq()
305  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
317 	ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, TRUE);  in i40e_read_nvm_word_aq()
326  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
348  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
384 	u16 specific_ptr = 0;  in i40e_read_nvm_module_data()
385 	u16 ptr_value = 0;  in i40e_read_nvm_module_data()
386 	u16 offset = 0;  in i40e_read_nvm_module_data()
388 	if (module_ptr != 0) {  in i40e_read_nvm_module_data()
397 #define I40E_NVM_INVALID_PTR_VAL 0x7FFF  in i40e_read_nvm_module_data()
398 #define I40E_NVM_INVALID_VAL 0xFFFF  in i40e_read_nvm_module_data()
444  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
461 	for (word = 0; word < *words; word++) {  in i40e_read_nvm_buffer_srctl()
477  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
491 	u16 words_read = 0;  in i40e_read_nvm_buffer_aq()
492 	u16 i = 0;  in i40e_read_nvm_buffer_aq()
513 		ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,  in i40e_read_nvm_buffer_aq()
525 	for (i = 0; i < *words; i++)  in i40e_read_nvm_buffer_aq()
536  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
556  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
603 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_write_nvm_aq()
624 					      data, last_command, 0,  in i40e_write_nvm_aq()
648 	/* Value 0x00 below means that we treat SR as a flat mem */  in __i40e_write_nvm_word()
649 	return i40e_write_nvm_aq(hw, 0x00, offset, 1, data, FALSE);  in __i40e_write_nvm_word()
671 	u32 i = 0;  in __i40e_write_nvm_buffer()
675 	for (i = 0; i < words; i++)  in __i40e_write_nvm_buffer()
699 	u16 pcie_alt_module = 0;  in i40e_calc_nvm_checksum()
700 	u16 checksum_local = 0;  in i40e_calc_nvm_checksum()
701 	u16 vpd_module = 0;  in i40e_calc_nvm_checksum()
703 	u16 i = 0;  in i40e_calc_nvm_checksum()
731 	for (i = 0; i < hw->nvm.sr_size; i++) {  in i40e_calc_nvm_checksum()
733 		if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {  in i40e_calc_nvm_checksum()
788 		ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,  in i40e_update_nvm_checksum()
807 	u16 checksum_sr = 0;  in i40e_validate_nvm_checksum()
808 	u16 checksum_local = 0;  in i40e_validate_nvm_checksum()
924 	*perrno = 0;  in i40e_nvmupd_command()
929 …UG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data…  in i40e_nvmupd_command()
951 		bytes[0] = hw->nvmupd_state;  in i40e_nvmupd_command()
954 			bytes[1] = 0;  in i40e_nvmupd_command()
977 		 * make sure the trailing bytes are set to 0x0.  in i40e_nvmupd_command()
980 			i40e_memset(bytes + hw->nvmupd_features.size, 0x0,  in i40e_nvmupd_command()
1024 		if (cmd->offset == 0xffff) {  in i40e_nvmupd_command()
1361 		   "NVMUPD: clearing wait on opcode 0x%04x\n",  in i40e_nvmupd_clear_wait_state()
1368 	hw->nvm_wait_opcode = 0;  in i40e_nvmupd_clear_wait_state()
1504 			if (module == 0)  in i40e_nvmupd_validate_command()
1530 	u32 buff_size = 0;  in i40e_nvmupd_exec_aq()
1536 	if (cmd->offset == 0xffff)  in i40e_nvmupd_exec_aq()
1539 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_nvmupd_exec_aq()
1543 	memset(&hw->nvm_wb_desc, 0, aq_desc_len);  in i40e_nvmupd_exec_aq()
1576 		memset(&hw->nvm_aq_event_desc, 0, aq_desc_len);  in i40e_nvmupd_exec_aq()
1657 	if (remainder > 0) {  in i40e_nvmupd_get_aq_result()
1725 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_nvmupd_nvm_read()
1732 			   "i40e_nvmupd_nvm_read mod 0x%x  off 0x%x  len 0x%x\n",  in i40e_nvmupd_nvm_read()
1764 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_nvmupd_nvm_erase()
1771 			   "i40e_nvmupd_nvm_erase mod 0x%x  off 0x%x len 0x%x\n",  in i40e_nvmupd_nvm_erase()
1806 	memset(&cmd_details, 0, sizeof(cmd_details));  in i40e_nvmupd_nvm_write()
1814 			   "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",  in i40e_nvmupd_nvm_write()