Lines Matching full:hw
48 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
49 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
50 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
54 * @hw: pointer to hardware structure
59 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
61 struct ixgbe_mac_info *mac = &hw->mac;
62 struct ixgbe_phy_info *phy = &hw->phy;
63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
69 ret_val = ixgbe_init_phy_ops_generic(hw);
70 ret_val = ixgbe_init_ops_generic(hw);
139 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
146 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
150 hw->mbx.ops[i].init_params = ixgbe_init_mbx_params_pf;
166 * @hw: pointer to hardware structure
172 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
176 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
183 * @hw: pointer to hardware structure
187 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
189 UNREFERENCED_1PARAMETER(hw);
195 * @hw: pointer to hardware structure
199 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
204 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
209 * @hw: pointer to hardware structure
214 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
218 u32 swfw_mask = hw->phy.phy_semaphore_mask;
223 status = hw->mac.ops.stop_adapter(hw);
228 ixgbe_clear_tx_pending(hw);
231 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
238 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
239 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
240 IXGBE_WRITE_FLUSH(hw);
241 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
246 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
261 * for any pending HW events to complete.
263 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
264 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
269 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
272 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
279 hw->mac.num_rar_entries = 128;
280 hw->mac.ops.init_rx_addrs(hw);
283 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
286 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
288 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
290 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
291 hw->mac.san_addr, 0, IXGBE_RAH_AV);
294 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
298 hw->mac.num_rar_entries--;
302 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
303 &hw->mac.wwpn_prefix);
311 * @hw: pointer to hardware structure
317 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
323 ret_val = ixgbe_start_hw_generic(hw);
327 ixgbe_start_hw_gen2(hw);
335 * @hw: pointer to hardware structure
339 u64 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
346 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
360 * @hw: pointer to hardware structure
365 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
367 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
377 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
392 * @hw: pointer to hardware structure
398 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
403 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
405 status = ixgbe_read_eerd_generic(hw, offset, data);
406 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
416 * @hw: pointer to hardware structure
423 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
429 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
431 status = ixgbe_read_eerd_buffer_generic(hw, offset,
433 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
443 * @hw: pointer to hardware structure
449 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
454 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
456 status = ixgbe_write_eewr_generic(hw, offset, data);
457 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
467 * @hw: pointer to hardware structure
474 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
480 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
482 status = ixgbe_write_eewr_buffer_generic(hw, offset,
484 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
498 * @hw: pointer to hardware structure
502 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
511 /* Do not use hw->eeprom.ops.read because we do not want to take
522 if (ixgbe_read_eerd_generic(hw, i, &word)) {
536 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
543 pointer >= hw->eeprom.word_size)
546 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
553 (pointer + length) >= hw->eeprom.word_size)
557 if (ixgbe_read_eerd_generic(hw, j, &word)) {
572 * @hw: pointer to hardware structure
578 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
591 status = hw->eeprom.ops.read(hw, 0, &checksum);
597 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
600 status = hw->eeprom.ops.calc_checksum(hw);
606 /* Do not use hw->eeprom.ops.read because we do not want to take
609 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
628 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
635 * @hw: pointer to hardware structure
641 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
652 status = hw->eeprom.ops.read(hw, 0, &checksum);
658 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
661 status = hw->eeprom.ops.calc_checksum(hw);
667 /* Do not use hw->eeprom.ops.write because we do not want to
670 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
674 status = ixgbe_update_flash_X540(hw);
677 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
683 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
684 * @hw: pointer to hardware structure
689 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
696 status = ixgbe_poll_flash_update_done_X540(hw);
702 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
703 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
705 status = ixgbe_poll_flash_update_done_X540(hw);
711 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
712 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
716 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
719 status = ixgbe_poll_flash_update_done_X540(hw);
731 * @hw: pointer to hardware structure
736 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
745 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
762 * @hw: pointer to hardware structure
768 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
789 if (hw->mac.type >= ixgbe_mac_X550)
796 if (ixgbe_get_swfw_sync_semaphore(hw)) {
801 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
804 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
806 ixgbe_release_swfw_sync_semaphore(hw);
813 ixgbe_release_swfw_sync_semaphore(hw);
817 /* If the resource is not released by the FW/HW the SW can assume that
818 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
819 * of the requested resource(s) while ignoring the corresponding FW/HW
822 if (ixgbe_get_swfw_sync_semaphore(hw)) {
826 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
829 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
830 ixgbe_release_swfw_sync_semaphore(hw);
846 ixgbe_release_swfw_sync_X540(hw, rmask);
847 ixgbe_release_swfw_sync_semaphore(hw);
851 ixgbe_release_swfw_sync_semaphore(hw);
859 * @hw: pointer to hardware structure
865 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
874 ixgbe_get_swfw_sync_semaphore(hw);
876 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
878 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
880 ixgbe_release_swfw_sync_semaphore(hw);
886 * @hw: pointer to hardware structure
890 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
905 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
916 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
930 ixgbe_release_swfw_sync_semaphore(hw);
944 * @hw: pointer to hardware structure
948 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
956 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
958 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
960 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
962 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
964 IXGBE_WRITE_FLUSH(hw);
969 * @hw: pointer to hardware structure
974 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
984 ixgbe_get_swfw_sync_semaphore(hw);
985 ixgbe_release_swfw_sync_semaphore(hw);
993 ixgbe_acquire_swfw_sync_X540(hw, rmask);
994 ixgbe_release_swfw_sync_X540(hw, rmask);
999 * @hw: pointer to hardware structure
1005 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
1022 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1024 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1026 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1029 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1032 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1033 IXGBE_WRITE_FLUSH(hw);
1040 * @hw: pointer to hardware structure
1046 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
1057 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1061 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1064 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1066 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1067 IXGBE_WRITE_FLUSH(hw);