Lines Matching +full:mdi +full:- +full:x
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
85 * ixgbe_ones_comp_byte_add - Perform one's complement addition
89 * Returns one's complement 8-bit sum.
100 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
112 u32 swfw_mask = hw->phy.phy_semaphore_mask;
125 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
140 /* Re-start condition */
158 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
167 DEBUGOUT("I2C byte read combined error - Retrying.\n");
177 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
189 u32 swfw_mask = hw->phy.phy_semaphore_mask;
201 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
224 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
230 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
232 DEBUGOUT("I2C byte write combined error - Retrying.\n");
242 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
249 struct ixgbe_phy_info *phy = &hw->phy;
254 phy->ops.identify = ixgbe_identify_phy_generic;
255 phy->ops.reset = ixgbe_reset_phy_generic;
256 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
257 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
258 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
259 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
260 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
261 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
262 phy->ops.check_link = NULL;
263 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
264 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
265 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
266 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
267 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
268 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
269 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
270 phy->ops.identify_sfp = ixgbe_identify_module_generic;
271 phy->sfp_type = ixgbe_sfp_type_unknown;
272 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
273 phy->ops.write_i2c_byte_unlocked =
275 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
280 * ixgbe_probe_phy - Probe a single address for a PHY
291 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
299 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
301 if (hw->phy.type == ixgbe_phy_unknown) {
302 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
307 hw->phy.type = ixgbe_phy_cu_unknown;
309 hw->phy.type = ixgbe_phy_generic;
316 * ixgbe_identify_phy_generic - Get physical layer module
328 if (!hw->phy.phy_semaphore_mask) {
329 if (hw->bus.lan_id)
330 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
332 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
335 if (hw->phy.type != ixgbe_phy_unknown)
338 if (hw->phy.nw_mng_if_sel) {
339 phy_addr = (hw->phy.nw_mng_if_sel &
360 hw->phy.addr = 0;
366 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
381 if (hw->mac.type == ixgbe_mac_82598EB)
395 * ixgbe_validate_phy_addr - Determines phy address is valid
407 hw->phy.addr = phy_addr;
408 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
414 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
420 * ixgbe_get_phy_id - Get the phy type
432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
437 hw->phy.id = (u32)(phy_id_high << 16);
438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
444 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
451 * ixgbe_get_phy_type_from_id - Get the phy type
491 * ixgbe_reset_phy_generic - Performs a PHY reset
502 if (hw->phy.type == ixgbe_phy_unknown)
505 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
509 if (!hw->phy.reset_if_overtemp &&
510 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
521 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
526 * Poll for reset bit to self-clear indicating reset is complete.
532 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
533 status = hw->phy.ops.read_reg(hw,
545 status = hw->phy.ops.read_reg(hw,
570 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
581 /* Restart PHY auto-negotiation. */
582 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
585 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
590 * ixgbe_read_phy_reg_mdi - Reads a value from a specified PHY register without
605 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
612 * The MDI Command bit will clear when the operation is
636 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
643 * completed. The MDI Command bit will clear when the
672 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
673 * using the SWFW lock - this function is needed in most cases
683 u32 gssr = hw->phy.phy_semaphore_mask;
687 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
690 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
692 hw->mac.ops.release_swfw_sync(hw, gssr);
698 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
710 /* Put the data in the MDI single read and write data register*/
716 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
723 * The MDI Command bit will clear when the operation is
745 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
752 * completed. The MDI Command bit will clear when the
772 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
773 * using SWFW lock- this function is needed in most cases
783 u32 gssr = hw->phy.phy_semaphore_mask;
787 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
788 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
790 hw->mac.ops.release_swfw_sync(hw, gssr);
799 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
802 * Restart auto-negotiation and PHY and waits for completion.
815 /* Set or unset auto-negotiation 10G advertisement */
816 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
825 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
829 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
833 if (hw->mac.type == ixgbe_mac_X550) {
834 /* Set or unset auto-negotiation 5G advertisement */
836 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
840 /* Set or unset auto-negotiation 2.5G advertisement */
842 if ((hw->phy.autoneg_advertised &
848 /* Set or unset auto-negotiation 1G advertisement */
850 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
854 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
858 /* Set or unset auto-negotiation 100M advertisement */
859 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
865 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
869 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
878 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
895 hw->phy.autoneg_advertised = 0;
898 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
901 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
904 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
907 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
910 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
913 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
922 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
933 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
940 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
946 switch (hw->mac.type) {
948 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
949 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
953 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
963 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
966 * @autoneg: boolean auto-negotiation value
977 if (!hw->phy.speeds_supported)
980 *speed = hw->phy.speeds_supported;
985 * ixgbe_check_phy_link_tnx - Determine link and speed status
1016 status = hw->phy.ops.read_reg(hw,
1036 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1039 * Restart auto-negotiation and PHY and waits for completion.
1053 /* Set or unset auto-negotiation 10G advertisement */
1054 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1059 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1062 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1068 /* Set or unset auto-negotiation 1G advertisement */
1069 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1074 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1077 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1083 /* Set or unset auto-negotiation 100M advertisement */
1084 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1089 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1092 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1102 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1113 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1121 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1132 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1140 * ixgbe_reset_phy_nl - Performs a PHY reset
1158 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1162 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1167 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1186 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1192 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1207 ret_val = hw->eeprom.ops.read(hw, data_offset,
1213 ret_val = hw->eeprom.ops.read(hw, data_offset,
1217 hw->phy.ops.write_reg(hw, phy_offset,
1219 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1256 * ixgbe_identify_module_generic - Identifies module type
1267 switch (hw->mac.ops.get_media_type(hw)) {
1277 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1286 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1295 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1307 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1308 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1314 hw->mac.ops.set_lan_id(hw);
1316 status = hw->phy.ops.read_i2c_eeprom(hw,
1324 hw->phy.type = ixgbe_phy_sfp_unsupported;
1327 status = hw->phy.ops.read_i2c_eeprom(hw,
1334 status = hw->phy.ops.read_i2c_eeprom(hw,
1340 status = hw->phy.ops.read_i2c_eeprom(hw,
1352 * 3 SFP_DA_CORE0 - 82599-specific
1353 * 4 SFP_DA_CORE1 - 82599-specific
1354 * 5 SFP_SR/LR_CORE0 - 82599-specific
1355 * 6 SFP_SR/LR_CORE1 - 82599-specific
1356 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1357 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1358 * 9 SFP_1g_cu_CORE0 - 82599-specific
1359 * 10 SFP_1g_cu_CORE1 - 82599-specific
1360 * 11 SFP_1g_sx_CORE0 - 82599-specific
1361 * 12 SFP_1g_sx_CORE1 - 82599-specific
1363 if (hw->mac.type == ixgbe_mac_82598EB) {
1365 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1367 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1369 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1371 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1374 if (hw->bus.lan_id == 0)
1375 hw->phy.sfp_type =
1378 hw->phy.sfp_type =
1381 hw->phy.ops.read_i2c_eeprom(
1386 if (hw->bus.lan_id == 0)
1387 hw->phy.sfp_type =
1390 hw->phy.sfp_type =
1393 hw->phy.sfp_type =
1399 if (hw->bus.lan_id == 0)
1400 hw->phy.sfp_type =
1403 hw->phy.sfp_type =
1406 if (hw->bus.lan_id == 0)
1407 hw->phy.sfp_type =
1410 hw->phy.sfp_type =
1413 if (hw->bus.lan_id == 0)
1414 hw->phy.sfp_type =
1417 hw->phy.sfp_type =
1420 if (hw->bus.lan_id == 0)
1421 hw->phy.sfp_type =
1424 hw->phy.sfp_type =
1427 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1431 if (hw->phy.sfp_type != stored_sfp_type)
1432 hw->phy.sfp_setup_needed = true;
1435 hw->phy.multispeed_fiber = false;
1442 hw->phy.multispeed_fiber = true;
1445 if (hw->phy.type != ixgbe_phy_nl) {
1446 hw->phy.id = identifier;
1447 status = hw->phy.ops.read_i2c_eeprom(hw,
1454 status = hw->phy.ops.read_i2c_eeprom(hw,
1461 status = hw->phy.ops.read_i2c_eeprom(hw,
1476 hw->phy.type =
1481 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1483 hw->phy.type = ixgbe_phy_sfp_ftl;
1486 hw->phy.type = ixgbe_phy_sfp_avago;
1489 hw->phy.type = ixgbe_phy_sfp_intel;
1493 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1495 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1497 hw->phy.type = ixgbe_phy_sfp_unknown;
1511 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1513 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1517 hw->phy.type = ixgbe_phy_sfp_unsupported;
1522 /* Anything else 82598-based is supported */
1523 if (hw->mac.type == ixgbe_mac_82598EB) {
1530 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1537 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1540 if (hw->allow_unsupported_sfp == true) {
1551 hw->phy.type =
1565 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1566 if (hw->phy.type != ixgbe_phy_nl) {
1567 hw->phy.id = 0;
1568 hw->phy.type = ixgbe_phy_unknown;
1574 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1587 hw->phy.ops.identify_sfp(hw);
1588 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1591 switch (hw->phy.type) {
1606 hw->phy.ops.read_i2c_eeprom(hw,
1608 hw->phy.ops.read_i2c_eeprom(hw,
1621 hw->phy.ops.read_i2c_eeprom(hw,
1636 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1645 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1659 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1660 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1666 hw->mac.ops.set_lan_id(hw);
1668 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1675 hw->phy.type = ixgbe_phy_sfp_unsupported;
1680 hw->phy.id = identifier;
1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1688 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1695 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1696 if (hw->bus.lan_id == 0)
1697 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1699 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1702 if (hw->bus.lan_id == 0)
1703 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1705 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1711 /* check for active DA cables that pre-date
1712 * SFF-8436 v3.6 */
1713 hw->phy.ops.read_i2c_eeprom(hw,
1717 hw->phy.ops.read_i2c_eeprom(hw,
1721 hw->phy.ops.read_i2c_eeprom(hw,
1734 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1735 if (hw->bus.lan_id == 0)
1736 hw->phy.sfp_type =
1739 hw->phy.sfp_type =
1743 hw->phy.type = ixgbe_phy_sfp_unsupported;
1749 if (hw->phy.sfp_type != stored_sfp_type)
1750 hw->phy.sfp_setup_needed = true;
1753 hw->phy.multispeed_fiber = false;
1758 hw->phy.multispeed_fiber = true;
1763 status = hw->phy.ops.read_i2c_eeprom(hw,
1770 status = hw->phy.ops.read_i2c_eeprom(hw,
1777 status = hw->phy.ops.read_i2c_eeprom(hw,
1790 hw->phy.type = ixgbe_phy_qsfp_intel;
1792 hw->phy.type = ixgbe_phy_qsfp_unknown;
1797 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1800 if (hw->allow_unsupported_sfp == true) {
1810 hw->phy.type =
1824 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1825 hw->phy.id = 0;
1826 hw->phy.type = ixgbe_phy_unknown;
1832 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1845 u16 sfp_type = hw->phy.sfp_type;
1849 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1852 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1855 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1856 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1875 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1892 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1898 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1908 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1927 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1939 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1945 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1950 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1955 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1961 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1973 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1979 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1988 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1994 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2010 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2016 if (hw->mac.type >= ixgbe_mac_X550)
2022 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2063 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2069 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2073 DEBUGOUT("I2C byte read error - Retrying.\n");
2083 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2100 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2117 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2133 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2137 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2170 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2176 DEBUGOUT("I2C byte write error - Retrying.\n");
2183 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2189 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2206 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2223 * ixgbe_i2c_start - Sets I2C start condition
2226 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2227 * Set bit-bang mode on X550 hardware.
2257 * ixgbe_i2c_stop - Sets I2C stop condition
2260 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2261 * Disables bit-bang mode and negates data output enable on X550
2294 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2308 for (i = 7; i >= 0; i--) {
2315 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2330 for (i = 7; i >= 0; i--) {
2349 * ixgbe_get_i2c_ack - Polls for I2C ACK
2401 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2435 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2464 "I2C data was not set to %X\n", data);
2471 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2475 * Raises the I2C clock line '0'->'1'
2507 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2511 * Lowers the I2C clock line '1'->'0'
2529 * ixgbe_set_i2c_data - Sets the I2C data bit
2553 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2569 "Error - I2C data was not set to %X.\n",
2577 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2607 * ixgbe_i2c_bus_clear - Clears the I2C bus
2644 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2656 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2660 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2673 * ixgbe_set_copper_phy_power - Control power for copper phy
2685 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2699 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,