Lines Matching full:hw
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
55 * @hw: pointer to the hardware structure
60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
64 status = ixgbe_clock_out_i2c_byte(hw, byte);
67 return ixgbe_get_i2c_ack(hw);
72 * @hw: pointer to the hardware structure
77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
79 ixgbe_clock_in_i2c_byte(hw, byte);
81 return ixgbe_clock_out_i2c_bit(hw, false);
101 * @hw: pointer to the hardware structure
109 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
112 u32 swfw_mask = hw->phy.phy_semaphore_mask;
125 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
127 ixgbe_i2c_start(hw);
129 if (ixgbe_out_i2c_byte_ack(hw, addr))
132 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
135 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
138 if (ixgbe_out_i2c_byte_ack(hw, csum))
141 ixgbe_i2c_start(hw);
143 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
146 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
149 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
152 ixgbe_clock_in_i2c_byte(hw, &csum_byte);
154 if (ixgbe_clock_out_i2c_bit(hw, false))
156 ixgbe_i2c_stop(hw);
158 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
163 ixgbe_i2c_bus_clear(hw);
165 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
178 * @hw: pointer to the hardware structure
186 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
189 u32 swfw_mask = hw->phy.phy_semaphore_mask;
201 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
203 ixgbe_i2c_start(hw);
205 if (ixgbe_out_i2c_byte_ack(hw, addr))
208 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
211 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
214 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
217 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
220 if (ixgbe_out_i2c_byte_ack(hw, csum))
222 ixgbe_i2c_stop(hw);
224 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
228 ixgbe_i2c_bus_clear(hw);
230 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
243 * @hw: pointer to the hardware structure
247 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
249 struct ixgbe_phy_info *phy = &hw->phy;
281 * @hw: pointer to hardware structure
286 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
290 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
296 if (ixgbe_get_phy_id(hw))
299 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
301 if (hw->phy.type == ixgbe_phy_unknown) {
302 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
307 hw->phy.type = ixgbe_phy_cu_unknown;
309 hw->phy.type = ixgbe_phy_generic;
317 * @hw: pointer to hardware structure
321 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
328 if (!hw->phy.phy_semaphore_mask) {
329 if (hw->bus.lan_id)
330 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
332 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
335 if (hw->phy.type != ixgbe_phy_unknown)
338 if (hw->phy.nw_mng_if_sel) {
339 phy_addr = (hw->phy.nw_mng_if_sel &
342 if (ixgbe_probe_phy(hw, phy_addr))
349 if (ixgbe_probe_phy(hw, phy_addr)) {
360 hw->phy.addr = 0;
367 * @hw: pointer to the hardware structure
374 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
381 if (hw->mac.type == ixgbe_mac_82598EB)
384 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
396 * @hw: pointer to hardware structure
400 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
407 hw->phy.addr = phy_addr;
408 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
421 * @hw: pointer to hardware structure
424 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
432 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
437 hw->phy.id = (u32)(phy_id_high << 16);
438 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
441 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
442 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
492 * @hw: pointer to hardware structure
494 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
502 if (hw->phy.type == ixgbe_phy_unknown)
503 status = ixgbe_identify_phy_generic(hw);
505 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
509 if (!hw->phy.reset_if_overtemp &&
510 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
514 if (ixgbe_check_reset_blocked(hw))
521 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
532 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
533 status = hw->phy.ops.read_reg(hw,
545 status = hw->phy.ops.read_reg(hw,
571 * @hw: pointer to hardware structure
573 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
578 if (ixgbe_check_reset_blocked(hw))
582 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
585 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
592 * @hw: pointer to hardware structure
597 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
605 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
608 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
618 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
636 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
639 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
649 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
664 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
674 * @hw: pointer to hardware structure
679 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
683 u32 gssr = hw->phy.phy_semaphore_mask;
687 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
690 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
692 hw->mac.ops.release_swfw_sync(hw, gssr);
700 * @hw: pointer to hardware structure
705 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
711 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
716 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
719 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
729 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
745 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
748 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
758 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
774 * @hw: pointer to hardware structure
779 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
783 u32 gssr = hw->phy.phy_semaphore_mask;
787 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
788 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
790 hw->mac.ops.release_swfw_sync(hw, gssr);
800 * @hw: pointer to hardware structure
804 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
813 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
816 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
825 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
829 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
833 if (hw->mac.type == ixgbe_mac_X550) {
836 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
842 if ((hw->phy.autoneg_advertised &
850 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
854 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
859 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
865 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
869 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
873 ixgbe_restart_auto_neg(hw);
879 * @hw: pointer to hardware structure
883 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
895 hw->phy.autoneg_advertised = 0;
898 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
901 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
904 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
907 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
910 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
913 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
916 ixgbe_setup_phy_link(hw);
923 * @hw: pointer to hardware structure
928 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
933 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
940 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
946 switch (hw->mac.type) {
948 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
949 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
953 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
964 * @hw: pointer to hardware structure
968 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
977 if (!hw->phy.speeds_supported)
978 status = ixgbe_get_copper_speeds_supported(hw);
980 *speed = hw->phy.speeds_supported;
986 * @hw: pointer to hardware structure
993 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1016 status = hw->phy.ops.read_reg(hw,
1037 * @hw: pointer to hardware structure
1041 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1050 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1054 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1059 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1062 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1069 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1074 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1077 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1084 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1089 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1092 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1097 ixgbe_restart_auto_neg(hw);
1103 * @hw: pointer to hardware structure
1106 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1113 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1122 * @hw: pointer to hardware structure
1125 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1132 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1141 * @hw: pointer to hardware structure
1143 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1155 if (ixgbe_check_reset_blocked(hw))
1158 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1162 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1167 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1186 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1192 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1207 ret_val = hw->eeprom.ops.read(hw, data_offset,
1213 ret_val = hw->eeprom.ops.read(hw, data_offset,
1217 hw->phy.ops.write_reg(hw, phy_offset,
1257 * @hw: pointer to hardware structure
1259 * Determines HW type and calls appropriate function.
1261 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1267 switch (hw->mac.ops.get_media_type(hw)) {
1269 status = ixgbe_identify_sfp_module_generic(hw);
1273 status = ixgbe_identify_qsfp_module_generic(hw);
1277 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1287 * @hw: pointer to hardware structure
1291 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1295 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1307 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1308 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1314 hw->mac.ops.set_lan_id(hw);
1316 status = hw->phy.ops.read_i2c_eeprom(hw,
1324 hw->phy.type = ixgbe_phy_sfp_unsupported;
1327 status = hw->phy.ops.read_i2c_eeprom(hw,
1334 status = hw->phy.ops.read_i2c_eeprom(hw,
1340 status = hw->phy.ops.read_i2c_eeprom(hw,
1363 if (hw->mac.type == ixgbe_mac_82598EB) {
1365 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1367 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1369 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1371 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1374 if (hw->bus.lan_id == 0)
1375 hw->phy.sfp_type =
1378 hw->phy.sfp_type =
1381 hw->phy.ops.read_i2c_eeprom(
1382 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1386 if (hw->bus.lan_id == 0)
1387 hw->phy.sfp_type =
1390 hw->phy.sfp_type =
1393 hw->phy.sfp_type =
1399 if (hw->bus.lan_id == 0)
1400 hw->phy.sfp_type =
1403 hw->phy.sfp_type =
1406 if (hw->bus.lan_id == 0)
1407 hw->phy.sfp_type =
1410 hw->phy.sfp_type =
1413 if (hw->bus.lan_id == 0)
1414 hw->phy.sfp_type =
1417 hw->phy.sfp_type =
1420 if (hw->bus.lan_id == 0)
1421 hw->phy.sfp_type =
1424 hw->phy.sfp_type =
1427 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1431 if (hw->phy.sfp_type != stored_sfp_type)
1432 hw->phy.sfp_setup_needed = true;
1435 hw->phy.multispeed_fiber = false;
1442 hw->phy.multispeed_fiber = true;
1445 if (hw->phy.type != ixgbe_phy_nl) {
1446 hw->phy.id = identifier;
1447 status = hw->phy.ops.read_i2c_eeprom(hw,
1454 status = hw->phy.ops.read_i2c_eeprom(hw,
1461 status = hw->phy.ops.read_i2c_eeprom(hw,
1476 hw->phy.type =
1481 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1483 hw->phy.type = ixgbe_phy_sfp_ftl;
1486 hw->phy.type = ixgbe_phy_sfp_avago;
1489 hw->phy.type = ixgbe_phy_sfp_intel;
1493 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1495 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1497 hw->phy.type = ixgbe_phy_sfp_unknown;
1511 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1513 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1515 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1516 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1517 hw->phy.type = ixgbe_phy_sfp_unsupported;
1523 if (hw->mac.type == ixgbe_mac_82598EB) {
1528 ixgbe_get_device_caps(hw, &enforce_sfp);
1530 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1534 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1535 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1537 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1540 if (hw->allow_unsupported_sfp == true) {
1542 EWARN(hw,
1551 hw->phy.type =
1565 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1566 if (hw->phy.type != ixgbe_phy_nl) {
1567 hw->phy.id = 0;
1568 hw->phy.type = ixgbe_phy_unknown;
1575 * @hw: pointer to hardware structure
1579 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1587 hw->phy.ops.identify_sfp(hw);
1588 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1591 switch (hw->phy.type) {
1606 hw->phy.ops.read_i2c_eeprom(hw,
1608 hw->phy.ops.read_i2c_eeprom(hw,
1621 hw->phy.ops.read_i2c_eeprom(hw,
1637 * @hw: pointer to hardware structure
1641 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1645 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1659 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1660 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1666 hw->mac.ops.set_lan_id(hw);
1668 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1675 hw->phy.type = ixgbe_phy_sfp_unsupported;
1680 hw->phy.id = identifier;
1682 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1688 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1695 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1696 if (hw->bus.lan_id == 0)
1697 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1699 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1702 if (hw->bus.lan_id == 0)
1703 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1705 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1713 hw->phy.ops.read_i2c_eeprom(hw,
1717 hw->phy.ops.read_i2c_eeprom(hw,
1721 hw->phy.ops.read_i2c_eeprom(hw,
1734 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1735 if (hw->bus.lan_id == 0)
1736 hw->phy.sfp_type =
1739 hw->phy.sfp_type =
1743 hw->phy.type = ixgbe_phy_sfp_unsupported;
1749 if (hw->phy.sfp_type != stored_sfp_type)
1750 hw->phy.sfp_setup_needed = true;
1753 hw->phy.multispeed_fiber = false;
1758 hw->phy.multispeed_fiber = true;
1763 status = hw->phy.ops.read_i2c_eeprom(hw,
1770 status = hw->phy.ops.read_i2c_eeprom(hw,
1777 status = hw->phy.ops.read_i2c_eeprom(hw,
1790 hw->phy.type = ixgbe_phy_qsfp_intel;
1792 hw->phy.type = ixgbe_phy_qsfp_unknown;
1794 ixgbe_get_device_caps(hw, &enforce_sfp);
1797 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1800 if (hw->allow_unsupported_sfp == true) {
1802 EWARN(hw,
1810 hw->phy.type =
1824 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1825 hw->phy.id = 0;
1826 hw->phy.type = ixgbe_phy_unknown;
1833 * @hw: pointer to hardware structure
1840 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1845 u16 sfp_type = hw->phy.sfp_type;
1849 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1852 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1855 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1856 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1875 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1892 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1898 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1908 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1928 * @hw: pointer to hardware structure
1934 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1939 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1946 * @hw: pointer to hardware structure
1952 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1955 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1962 * @hw: pointer to hardware structure
1968 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1973 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1980 * @hw: pointer to hardware structure
1984 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1988 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1995 * @hw: pointer to hardware structure
2004 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2010 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2016 if (hw->mac.type >= ixgbe_mac_X550)
2018 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2022 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2025 ixgbe_i2c_start(hw);
2028 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2032 status = ixgbe_get_i2c_ack(hw);
2036 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2040 status = ixgbe_get_i2c_ack(hw);
2044 ixgbe_i2c_start(hw);
2047 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2051 status = ixgbe_get_i2c_ack(hw);
2055 ixgbe_clock_in_i2c_byte(hw, data);
2057 status = ixgbe_clock_out_i2c_bit(hw, nack);
2061 ixgbe_i2c_stop(hw);
2063 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2067 ixgbe_i2c_bus_clear(hw);
2069 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2084 * @hw: pointer to hardware structure
2092 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2095 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2101 * @hw: pointer to hardware structure
2109 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2112 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2118 * @hw: pointer to hardware structure
2127 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2133 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2137 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2142 ixgbe_i2c_start(hw);
2144 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2148 status = ixgbe_get_i2c_ack(hw);
2152 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2156 status = ixgbe_get_i2c_ack(hw);
2160 status = ixgbe_clock_out_i2c_byte(hw, data);
2164 status = ixgbe_get_i2c_ack(hw);
2168 ixgbe_i2c_stop(hw);
2170 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2174 ixgbe_i2c_bus_clear(hw);
2183 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2190 * @hw: pointer to hardware structure
2198 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2201 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2207 * @hw: pointer to hardware structure
2215 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2218 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2224 * @hw: pointer to hardware structure
2229 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2231 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2235 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2238 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2239 ixgbe_raise_i2c_clk(hw, &i2cctl);
2244 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2249 ixgbe_lower_i2c_clk(hw, &i2cctl);
2258 * @hw: pointer to hardware structure
2264 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2266 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2267 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2268 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2269 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2274 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2275 ixgbe_raise_i2c_clk(hw, &i2cctl);
2280 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2288 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2289 IXGBE_WRITE_FLUSH(hw);
2295 * @hw: pointer to hardware structure
2300 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2309 ixgbe_clock_in_i2c_bit(hw, &bit);
2316 * @hw: pointer to hardware structure
2321 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2332 status = ixgbe_clock_out_i2c_bit(hw, bit);
2339 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2340 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2341 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2342 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2343 IXGBE_WRITE_FLUSH(hw);
2350 * @hw: pointer to hardware structure
2354 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2356 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2359 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2366 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2368 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2369 IXGBE_WRITE_FLUSH(hw);
2371 ixgbe_raise_i2c_clk(hw, &i2cctl);
2379 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2380 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2392 ixgbe_lower_i2c_clk(hw, &i2cctl);
2402 * @hw: pointer to hardware structure
2407 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2409 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2410 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2415 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2417 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2418 IXGBE_WRITE_FLUSH(hw);
2420 ixgbe_raise_i2c_clk(hw, &i2cctl);
2425 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2426 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2428 ixgbe_lower_i2c_clk(hw, &i2cctl);
2436 * @hw: pointer to hardware structure
2441 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2444 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2448 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2450 ixgbe_raise_i2c_clk(hw, &i2cctl);
2455 ixgbe_lower_i2c_clk(hw, &i2cctl);
2472 * @hw: pointer to hardware structure
2478 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2480 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2489 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2493 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2495 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2496 IXGBE_WRITE_FLUSH(hw);
2500 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2501 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2508 * @hw: pointer to hardware structure
2514 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2518 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2519 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2521 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2522 IXGBE_WRITE_FLUSH(hw);
2530 * @hw: pointer to hardware structure
2537 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2539 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2545 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2547 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2550 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2551 IXGBE_WRITE_FLUSH(hw);
2560 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2561 IXGBE_WRITE_FLUSH(hw);
2565 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2566 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2578 * @hw: pointer to hardware structure
2584 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2586 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2593 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2594 IXGBE_WRITE_FLUSH(hw);
2598 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2608 * @hw: pointer to hardware structure
2613 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2620 ixgbe_i2c_start(hw);
2621 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2623 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2626 ixgbe_raise_i2c_clk(hw, &i2cctl);
2631 ixgbe_lower_i2c_clk(hw, &i2cctl);
2637 ixgbe_i2c_start(hw);
2640 ixgbe_i2c_stop(hw);
2645 * @hw: pointer to hardware structure
2649 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2656 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2660 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2674 * @hw: pointer to hardware structure
2677 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2682 if (!on && ixgbe_mng_present(hw))
2685 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2694 if (ixgbe_check_reset_blocked(hw))
2699 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,