Lines Matching +full:mac +full:- +full:address
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
64 * ixgbe_init_ops_generic - Inits function ptrs
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
81 eeprom->ops.read = ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
88 eeprom->ops.write = ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
92 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 /* MAC */
96 mac->ops.init_hw = ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
109 mac->ops.prot_autoc_read = prot_autoc_read_generic;
110 mac->ops.prot_autoc_write = prot_autoc_write_generic;
113 mac->ops.led_on = ixgbe_led_on_generic;
114 mac->ops.led_off = ixgbe_led_off_generic;
115 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
116 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic;
120 mac->ops.set_rar = ixgbe_set_rar_generic;
121 mac->ops.clear_rar = ixgbe_clear_rar_generic;
122 mac->ops.insert_mac_addr = NULL;
123 mac->ops.set_vmdq = NULL;
124 mac->ops.clear_vmdq = NULL;
125 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
126 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
127 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
128 mac->ops.enable_mc = ixgbe_enable_mc_generic;
129 mac->ops.disable_mc = ixgbe_disable_mc_generic;
130 mac->ops.clear_vfta = NULL;
131 mac->ops.set_vfta = NULL;
132 mac->ops.set_vlvf = NULL;
133 mac->ops.init_uta_tables = NULL;
134 mac->ops.enable_rx = ixgbe_enable_rx_generic;
135 mac->ops.disable_rx = ixgbe_disable_rx_generic;
136 mac->ops.toggle_txdctl = ixgbe_toggle_txdctl_generic;
139 mac->ops.fc_enable = ixgbe_fc_enable_generic;
140 mac->ops.setup_fc = ixgbe_setup_fc_generic;
141 mac->ops.fc_autoneg = ixgbe_fc_autoneg;
144 mac->ops.get_link_capabilities = NULL;
145 mac->ops.setup_link = NULL;
146 mac->ops.check_link = NULL;
147 mac->ops.dmac_config = NULL;
148 mac->ops.dmac_update_tcs = NULL;
149 mac->ops.dmac_config_tcs = NULL;
155 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
171 switch (hw->phy.media_type) {
176 switch (hw->device_id) {
184 hw->mac.ops.check_link(hw, &speed, &link_up, false);
195 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
202 switch (hw->device_id) {
225 hw->device_id);
231 * ixgbe_setup_fc_generic - Set up flow control
246 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
257 if (hw->fc.requested_mode == ixgbe_fc_default)
258 hw->fc.requested_mode = ixgbe_fc_full;
265 switch (hw->phy.media_type) {
267 /* some MAC's need RMW protection on AUTOC */
268 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
281 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
298 switch (hw->fc.requested_mode) {
302 if (hw->phy.media_type == ixgbe_media_type_backplane)
305 else if (hw->phy.media_type == ixgbe_media_type_copper)
315 if (hw->phy.media_type == ixgbe_media_type_backplane) {
318 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
336 if (hw->phy.media_type == ixgbe_media_type_backplane)
339 else if (hw->phy.media_type == ixgbe_media_type_copper)
350 if (hw->mac.type < ixgbe_mac_X540) {
352 * Enable auto-negotiation between the MAC & PHY;
353 * the MAC will advertise clause 37 flow control.
359 if (hw->fc.strict_ieee)
371 if (hw->phy.media_type == ixgbe_media_type_backplane) {
373 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
376 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
378 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
388 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
392 * all on chip counters, initializes receive address registers, multicast
405 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
410 hw->mac.ops.clear_vfta(hw);
413 hw->mac.ops.clear_hw_cntrs(hw);
429 switch (hw->mac.type) {
433 hw->mac.ops.get_device_caps(hw, &device_caps);
435 hw->need_crosstalk_fix = false;
437 hw->need_crosstalk_fix = true;
440 hw->need_crosstalk_fix = false;
445 hw->adapter_stopped = false;
451 * ixgbe_start_hw_gen2 - Init sequence for common device family
466 for (i = 0; i < hw->mac.max_tx_queues; i++) {
473 for (i = 0; i < hw->mac.max_tx_queues; i++) {
479 for (i = 0; i < hw->mac.max_rx_queues; i++) {
488 * ixgbe_init_hw_generic - Generic hardware initialization
493 * address registers, multicast table, VLAN filter table, calls routine to set
504 status = hw->mac.ops.reset_hw(hw);
508 status = hw->mac.ops.start_hw(hw);
512 if (hw->mac.ops.init_led_link_act)
513 hw->mac.ops.init_led_link_act(hw);
522 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
546 if (hw->mac.type >= ixgbe_mac_82599EB) {
557 if (hw->mac.type >= ixgbe_mac_82599EB) {
565 if (hw->mac.type >= ixgbe_mac_82599EB)
582 if (hw->mac.type == ixgbe_mac_82598EB)
607 if (hw->mac.type >= ixgbe_mac_82599EB) {
619 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
620 if (hw->phy.id == 0)
622 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
624 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
626 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
628 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
636 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
659 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
665 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
692 pba_num[6] = '-';
700 /* switch all the data but the '-' to hex char */
705 pba_num[offset] += 'A' - 0xA;
711 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
717 if (length == 0xFFFF || length == 0 || length > hw->eeprom.word_size) {
723 if (pba_num_size < (((u32)length * 2) - 1)) {
730 length--;
733 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
747 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
760 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
770 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
803 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
804 &pba->word[0]);
809 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
810 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
816 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
817 if (pba->pba_block == NULL)
830 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
832 pba->pba_block);
836 if (eeprom_buf_size > (u32)(pba->word[1] +
838 memcpy(pba->pba_block,
839 &eeprom_buf[pba->word[1]],
870 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
871 &pba->word[0]);
876 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
877 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
883 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
884 if (pba->pba_block == NULL)
888 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
889 pba->pba_block[0],
890 pba->pba_block);
894 if (eeprom_buf_size > (u32)(pba->word[1] +
895 pba->pba_block[0])) {
896 memcpy(&eeprom_buf[pba->word[1]],
897 pba->pba_block,
898 pba->pba_block[0] * sizeof(u16));
930 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
945 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
970 * ixgbe_get_mac_addr_generic - Generic get MAC address
972 * @mac_addr: Adapter MAC address
974 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
976 * in order for the MAC address to have been loaded from the EEPROM into RAR0
999 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
1007 struct ixgbe_mac_info *mac = &hw->mac;
1009 if (hw->bus.type == ixgbe_bus_type_unknown)
1010 hw->bus.type = ixgbe_bus_type_pci_express;
1014 hw->bus.width = ixgbe_bus_width_pcie_x1;
1017 hw->bus.width = ixgbe_bus_width_pcie_x2;
1020 hw->bus.width = ixgbe_bus_width_pcie_x4;
1023 hw->bus.width = ixgbe_bus_width_pcie_x8;
1026 hw->bus.width = ixgbe_bus_width_unknown;
1032 hw->bus.speed = ixgbe_bus_speed_2500;
1035 hw->bus.speed = ixgbe_bus_speed_5000;
1038 hw->bus.speed = ixgbe_bus_speed_8000;
1041 hw->bus.speed = ixgbe_bus_speed_unknown;
1045 mac->ops.set_lan_id(hw);
1049 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1070 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1073 * Determines the LAN function id by reading memory-mapped registers and swaps
1074 * the port value if requested, and set MAC instance for devices that share
1079 struct ixgbe_bus_info *bus = &hw->bus;
1086 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1087 bus->lan_id = (u8)bus->func;
1092 bus->func ^= 0x1;
1094 /* Get MAC instance from EEPROM for configuring CS4227 */
1095 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1096 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1097 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
1103 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1122 hw->adapter_stopped = true;
1134 for (i = 0; i < hw->mac.max_tx_queues; i++)
1138 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1150 * Prevent the PCI-E bus from hanging by disabling PCI-E primary
1157 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1165 struct ixgbe_mac_info *mac = &hw->mac;
1177 mac->led_link_act = i;
1184 * known MAC defaults.
1186 switch (hw->mac.type) {
1189 mac->led_link_act = 1;
1192 mac->led_link_act = 2;
1198 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1221 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1244 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1252 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1258 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1259 eeprom->type = ixgbe_eeprom_none;
1262 eeprom->semaphore_delay = 10;
1264 eeprom->word_page_size = 0;
1272 eeprom->type = ixgbe_eeprom_spi;
1280 eeprom->word_size = 1 << (eeprom_size +
1285 eeprom->address_bits = 16;
1287 eeprom->address_bits = 8;
1288 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1289 "%d\n", eeprom->type, eeprom->word_size,
1290 eeprom->address_bits);
1297 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1303 * Reads 16 bit word(s) from EEPROM through bit-bang method
1313 hw->eeprom.ops.init_params(hw);
1320 if (offset + words > hw->eeprom.word_size) {
1329 if ((hw->eeprom.word_page_size == 0) &&
1339 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1340 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1353 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1395 * Some SPI eeproms use the 8th address bit embedded
1398 if ((hw->eeprom.address_bits == 8) &&
1402 /* Send the Write command (8-bit opcode + addr) */
1406 hw->eeprom.address_bits);
1408 page_size = hw->eeprom.word_page_size;
1420 if (((offset + i) & (page_size - 1)) ==
1421 (page_size - 1))
1428 /* Done with writing - release the EEPROM */
1436 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1450 hw->eeprom.ops.init_params(hw);
1452 if (offset >= hw->eeprom.word_size) {
1464 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1470 * Reads 16 bit word(s) from EEPROM through bit-bang method
1480 hw->eeprom.ops.init_params(hw);
1487 if (offset + words > hw->eeprom.word_size) {
1498 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1499 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1513 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1519 * Reads 16 bit word(s) from EEPROM through bit-bang method
1545 * Some SPI eeproms use the 8th address bit embedded
1548 if ((hw->eeprom.address_bits == 8) &&
1556 hw->eeprom.address_bits);
1571 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1576 * Reads 16 bit value from EEPROM through bit-bang method
1585 hw->eeprom.ops.init_params(hw);
1587 if (offset >= hw->eeprom.word_size) {
1599 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1616 hw->eeprom.ops.init_params(hw);
1624 if (offset >= hw->eeprom.word_size) {
1650 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1670 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1673 hw->eeprom.word_page_size = 0;
1683 * EEPROM address wraps around current page.
1685 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1688 hw->eeprom.word_page_size);
1694 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1707 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1724 hw->eeprom.ops.init_params(hw);
1732 if (offset >= hw->eeprom.word_size) {
1763 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1776 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1812 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1815 * Prepares EEPROM for access using bit-bang method. This function should
1826 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1850 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1867 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1870 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1897 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1958 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1978 * ixgbe_ready_eeprom - Polls for EEPROM ready
2007 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
2008 * devices (and only 0-5mSec on 5V devices)
2019 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
2042 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2062 mask = 0x01 << (count - 1);
2099 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2139 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2158 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2177 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2200 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2203 msec_delay(hw->eeprom.semaphore_delay);
2207 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2210 * Returns a negative error code on error, or the 16-bit checksum
2223 /* Include 0x0-0x3F in the checksum */
2225 if (hw->eeprom.ops.read(hw, i, &word)) {
2234 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2243 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2252 if (hw->eeprom.ops.read(hw, j, &word)) {
2260 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2266 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2286 status = hw->eeprom.ops.read(hw, 0, &checksum);
2292 status = hw->eeprom.ops.calc_checksum(hw);
2298 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2318 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2332 status = hw->eeprom.ops.read(hw, 0, &checksum);
2338 status = hw->eeprom.ops.calc_checksum(hw);
2344 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2350 * ixgbe_validate_mac_addr - Validate MAC address
2351 * @mac_addr: pointer to MAC address.
2353 * Tests a MAC address to ensure it is a valid Individual Address.
2361 /* Make sure it is not a multicast address */
2364 /* Not a broadcast address */
2367 /* Reject the zero address */
2376 * ixgbe_set_rar_generic - Set Rx address register
2378 * @index: Receive address register to write
2379 * @addr: Address to put into receive address register
2381 * @enable_addr: set flag that address is active
2383 * Puts an ethernet address into a receive address register.
2389 u32 rar_entries = hw->mac.num_rar_entries;
2401 hw->mac.ops.set_vmdq(hw, index, vmdq);
2414 * of the address and the address valid bit.
2430 * ixgbe_clear_rar_generic - Remove Rx address register
2432 * @index: Receive address register to write
2434 * Clears an ethernet address from a receive address register.
2439 u32 rar_entries = hw->mac.num_rar_entries;
2453 * of the address and the address valid bit.
2462 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2468 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2471 * Places the MAC address in receive address register 0 and clears the rest
2472 * of the receive address registers. Clears the multicast table. Assumes
2478 u32 rar_entries = hw->mac.num_rar_entries;
2483 * If the current mac address is valid, assume it is a software override
2484 * to the permanent address.
2485 * Otherwise, use the permanent address from the eeprom.
2487 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2489 /* Get the MAC address from the RAR0 for later reference */
2490 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2493 hw->mac.addr[0], hw->mac.addr[1],
2494 hw->mac.addr[2]);
2495 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2496 hw->mac.addr[4], hw->mac.addr[5]);
2498 /* Setup the receive address. */
2499 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2500 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2501 hw->mac.addr[0], hw->mac.addr[1],
2502 hw->mac.addr[2]);
2503 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2504 hw->mac.addr[4], hw->mac.addr[5]);
2506 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2510 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2512 hw->addr_ctrl.overflow_promisc = 0;
2514 hw->addr_ctrl.rar_used_count = 1;
2517 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2524 hw->addr_ctrl.mta_in_use = 0;
2525 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2528 for (i = 0; i < hw->mac.mcft_size; i++)
2537 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2539 * @addr: new address
2542 * Adds it to unused receive address register or goes into promiscuous mode.
2546 u32 rar_entries = hw->mac.num_rar_entries;
2555 * Place this address in the RAR if there is room,
2558 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2559 rar = hw->addr_ctrl.rar_used_count;
2560 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2561 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2562 hw->addr_ctrl.rar_used_count++;
2564 hw->addr_ctrl.overflow_promisc++;
2571 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2575 * @next: iterator function to walk the address list
2578 * receive address registers. Uses unused receive address registers for the
2589 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2597 * Clear accounting of old secondary address list,
2600 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2601 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2602 hw->addr_ctrl.overflow_promisc = 0;
2605 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2618 if (hw->addr_ctrl.overflow_promisc) {
2620 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2621 DEBUGOUT(" Entering address overflow promisc mode\n");
2628 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2629 DEBUGOUT(" Leaving address overflow promisc mode\n");
2641 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2643 * @mc_addr: the multicast address
2645 * Extracts the 12 bits, from a multicast address, to determine which
2646 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2647 * incoming rx multicast addresses, to determine the bit-vector to check in
2648 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2658 switch (hw->mac.mc_filter_type) {
2659 case 0: /* use bits [47:36] of the address */
2662 case 1: /* use bits [46:35] of the address */
2665 case 2: /* use bits [45:34] of the address */
2668 case 3: /* use bits [43:32] of the address */
2677 /* vector can only be 12-bits or boundary will be exceeded */
2683 * ixgbe_set_mta - Set bit-vector in multicast table
2685 * @mc_addr: Multicast address
2687 * Sets the bit-vector in the multicast table.
2697 hw->addr_ctrl.mta_in_use++;
2700 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2703 * The MTA is a register array of 128 32-bit registers. It is treated
2713 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2717 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2721 * @next: iterator function to walk the multicast address list
2740 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2741 hw->addr_ctrl.mta_in_use = 0;
2746 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2756 for (i = 0; i < hw->mac.mcft_size; i++)
2758 hw->mac.mta_shadow[i]);
2760 if (hw->addr_ctrl.mta_in_use > 0)
2762 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2769 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2772 * Enables multicast address in RAR and the use of the multicast hash table.
2776 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2780 if (a->mta_in_use > 0)
2782 hw->mac.mc_filter_type);
2788 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2791 * Disables multicast address in RAR and the use of the multicast hash table.
2795 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2799 if (a->mta_in_use > 0)
2800 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2806 * ixgbe_fc_enable_generic - Enable flow control
2822 if (!hw->fc.pause_time) {
2829 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2830 hw->fc.high_water[i]) {
2831 if (!hw->fc.low_water[i] ||
2832 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2841 hw->mac.ops.fc_autoneg(hw);
2860 switch (hw->fc.current_mode) {
2906 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2907 hw->fc.high_water[i]) {
2908 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2910 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2916 * to the Rx packet buffer size - 24KB. This allows
2920 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2927 reg = hw->fc.pause_time * 0x00010001;
2932 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2939 * ixgbe_negotiate_fc - Negotiate flow control
2970 if (hw->fc.requested_mode == ixgbe_fc_full) {
2971 hw->fc.current_mode = ixgbe_fc_full;
2974 hw->fc.current_mode = ixgbe_fc_rx_pause;
2979 hw->fc.current_mode = ixgbe_fc_tx_pause;
2983 hw->fc.current_mode = ixgbe_fc_rx_pause;
2986 hw->fc.current_mode = ixgbe_fc_none;
2993 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
3005 * - link is up but AN did not complete, or if
3006 * - link is up and AN completed but timed out
3012 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
3030 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
3042 * - backplane autoneg was not completed, or if
3043 * - we are 82599 and link partner is not AN enabled
3047 DEBUGOUT("Auto-Negotiation did not complete\n");
3051 if (hw->mac.type == ixgbe_mac_82599EB) {
3074 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3084 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3087 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3098 * ixgbe_fc_autoneg - Configure flow control
3115 * - FC autoneg is disabled, or if
3116 * - link is not up.
3118 if (hw->fc.disable_fc_autoneg) {
3125 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3131 switch (hw->phy.media_type) {
3157 hw->fc.fc_was_autonegged = true;
3159 hw->fc.fc_was_autonegged = false;
3160 hw->fc.current_mode = hw->fc.requested_mode;
3165 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3168 * System-wide timeout range is encoded in PCIe Device Control2 register.
3212 * ixgbe_disable_pcie_primary - Disable PCI-express primary access
3215 * Disables PCI-Express primary access and verifies there are no pending
3233 IXGBE_REMOVED(hw->hw_addr))
3251 DEBUGOUT("GIO Primary Disable bit didn't clear - requesting resets\n");
3252 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3254 if (hw->mac.type >= ixgbe_mac_X550)
3265 if (IXGBE_REMOVED(hw->hw_addr))
3280 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3327 * ixgbe_release_swfw_sync - Release SWFW semaphore
3351 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3375 /* Use interrupt-safe sleep just in case */
3388 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3403 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3420 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3440 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3459 * ixgbe_blink_led_start_generic - Blink LED based on index.
3478 * Link must be up to auto-blink the LEDs;
3481 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3484 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3491 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3509 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3525 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3532 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3547 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3549 * @san_mac_offset: SAN MAC address offset
3551 * This function will read the EEPROM location for the SAN MAC address
3563 * First read the EEPROM pointer to see if the MAC addresses are
3566 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3578 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3580 * @san_mac_addr: SAN MAC address
3582 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3583 * per-port, so set_lan_id() must be called before reading the addresses.
3585 * upon for non-SFP connections, so we must call it here.
3596 * First read the EEPROM pointer to see if the MAC addresses are
3604 hw->mac.ops.set_lan_id(hw);
3605 /* apply the port offset to the address offset */
3606 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3609 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3626 * error though, so just wipe the local address and return.
3634 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3636 * @san_mac_addr: SAN MAC address
3638 * Write a SAN MAC address to the EEPROM.
3648 /* Look for SAN mac address pointer. If not defined, return */
3654 hw->mac.ops.set_lan_id(hw);
3655 /* Apply the port offset to the address offset */
3656 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3662 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3670 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3673 * Read PCIe configuration space, and get the MSI-X vector count from
3682 switch (hw->mac.type) {
3701 if (IXGBE_REMOVED(hw->hw_addr))
3705 /* MSI-X count is zero-based in HW */
3715 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3717 * @addr: Address to put into receive address register
3720 * Puts an ethernet address into a receive address register, or
3745 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3758 if (rar < hw->mac.rar_highwater) {
3765 } else if (rar == hw->mac.rar_highwater) {
3768 hw->mac.rar_highwater++;
3769 } else if (rar >= hw->mac.num_rar_entries) {
3784 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3786 * @rar: receive address register index to disassociate
3792 u32 rar_entries = hw->mac.num_rar_entries;
3806 if (IXGBE_REMOVED(hw->hw_addr))
3825 mpsar_hi &= ~(1 << (vmdq - 32));
3831 rar != 0 && rar != hw->mac.san_mac_rar_index)
3832 hw->mac.ops.clear_rar(hw, rar);
3838 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3840 * @rar: receive address register index to associate with a VMDq index
3846 u32 rar_entries = hw->mac.num_rar_entries;
3863 mpsar |= 1 << (vmdq - 32);
3870 * ixgbe_set_vmdq_san_mac_generic - Associate default VMDq pool index with
3871 * a rx address
3878 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3882 u32 rar = hw->mac.san_mac_rar_index;
3891 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3898 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3915 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3946 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
3948 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3966 * ixgbe_set_vfta_generic - Set VLAN filter table
3987 * this is a 2 part operation - first the VFTA, then the
3993 * The VFTA is a bitstring made up of 128 32-bit registers
3995 * bits[11-5]: which register
3996 * bits[4-0]: which bit in the register
4030 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
4079 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4119 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4130 for (offset = 0; offset < hw->mac.vft_size; offset++)
4144 * ixgbe_toggle_txdctl_generic - Toggle VF's queues
4199 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4209 if (!hw->need_crosstalk_fix)
4213 switch (hw->mac.ops.get_media_type(hw)) {
4225 * ixgbe_check_mac_link_generic - Determine link and speed status
4247 switch (hw->mac.type) {
4258 /* sanity check - No SFP+ devices here */
4281 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4316 if (hw->mac.type >= ixgbe_mac_X550) {
4326 if (hw->mac.type == ixgbe_mac_X550) {
4333 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4334 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4345 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4351 * This function will read the EEPROM from the alternative SAN MAC address
4366 /* check if alternative SAN MAC is supported */
4368 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4375 /* check capability in alternative san mac address block */
4377 if (hw->eeprom.ops.read(hw, offset, &caps))
4384 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4390 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4403 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4421 status = hw->eeprom.ops.read(hw, offset, &caps);
4429 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4438 status = hw->eeprom.ops.read(hw, offset, &flags);
4452 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4454 * @enable: enable or disable switch for MAC anti-spoofing
4455 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4464 if (hw->mac.type == ixgbe_mac_82598EB)
4476 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4478 * @enable: enable or disable switch for VLAN anti-spoofing
4479 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4488 if (hw->mac.type == ixgbe_mac_82598EB)
4500 * ixgbe_get_device_caps_generic - Get additional device capabilities
4511 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4517 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4529 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4535 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4545 * ixgbe_calculate_checksum - Calculate checksum for buffer
4564 return (u8) (0 - sum);
4568 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4649 * ixgbe_host_interface_command - Issue command to manageability block
4684 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4709 if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD ||
4710 resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) {
4716 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3)
4717 & 0xF00) | resp->buf_len;
4720 buf_len = resp->buf_len;
4741 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4747 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4775 fw_cmd.port_num = (u8)hw->bus.func;
4807 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4816 u32 pbsize = hw->mac.rx_pb_size;
4821 pbsize -= headroom;
4835 pbsize -= rxpktsize * (num_pb / 2);
4839 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4844 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4854 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4869 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4885 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4908 if (IXGBE_REMOVED(hw->hw_addr))
4943 * ixgbe_get_thermal_sensor_data_generic - Gathers thermal sensor data
4958 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4963 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4969 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4978 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4993 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
5004 status = hw->phy.ops.read_i2c_byte(hw,
5007 &data->sensor[i].temp);
5017 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
5021 * and save off the threshold and location values into mac.thermal_sensor_data
5036 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
5043 if ((hw->mac.type != ixgbe_mac_82599EB) ||
5048 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
5054 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
5066 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
5078 hw->phy.ops.write_i2c_byte(hw,
5083 data->sensor[i].location = sensor_location;
5084 data->sensor[i].caution_thresh = therm_limit;
5085 data->sensor[i].max_op_thresh = therm_limit -
5098 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW
5104 * Bit-bangs the cmd to the by_pass FW status points to what is returned.
5118 /* SDP vary by MAC type */
5119 switch (hw->mac.type) {
5164 if ((cmd >> (31 - i)) & 0x01) {
5210 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang.
5211 * @in_reg: The register cmd for the bit-bang read.
5212 * @out_reg: The register returned from a bit-bang read.
5231 * - All the event actions
5232 * - The timeout value
5247 * - time valid bit
5248 * - time we last sent
5266 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter.
5312 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres.
5315 * @addr: The bypass eeprom address to read.
5316 * @value: The 8b of data at the address above.
5344 * ixgbe_get_orom_version - Return option ROM from EEPROM
5349 * if valid option ROM version, nvm_ver->or_valid set to true
5350 * else nvm_ver->or_valid is false.
5357 nvm_ver->or_valid = false;
5359 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5365 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5366 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5374 nvm_ver->or_valid = true;
5375 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT;
5376 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) |
5378 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK;
5382 * ixgbe_get_oem_prod_version - Return OEM Product version
5387 * if valid OEM product version, nvm_ver->oem_valid set to true
5388 * else nvm_ver->oem_valid is false.
5395 nvm_ver->oem_valid = false;
5396 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5403 hw->eeprom.ops.read(hw, offset, &mod_len);
5404 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5411 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
5412 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5419 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT;
5420 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK;
5421 nvm_ver->oem_release = rel_num;
5422 nvm_ver->oem_valid = true;
5426 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
5437 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5439 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5446 nvm_ver->etk_id = etk_id_h;
5447 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT);
5449 nvm_ver->etk_id = etk_id_l;
5450 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT);
5455 * ixgbe_get_nvm_version - Return version of NVM and its components
5471 /* eeprom version is mac-type specific */
5472 switch (hw->mac.type) {
5477 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK)
5479 nvm_ver->nvm_minor = ((word & NVM_EEP_MINOR_MASK)
5481 nvm_ver->nvm_id = (word & NVM_EEP_ID_MASK);
5487 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK)
5489 nvm_ver->nvm_minor = ((word & NVM_EEP_MINOR_MASK)
5491 nvm_ver->nvm_id = (word & NVM_EEP_ID_MASK);
5500 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK)
5502 nvm_ver->nvm_minor = (word & NVM_EEP_X550_MINOR_MASK);
5509 /* phy version is mac-type specific */
5510 switch (hw->mac.type) {
5518 nvm_ver->phy_fw_maj = ((word & NVM_PHY_MAJOR_MASK)
5520 nvm_ver->phy_fw_min = ((word & NVM_PHY_MINOR_MASK)
5522 nvm_ver->phy_fw_id = (word & NVM_PHY_ID_MASK);
5533 nvm_ver->devstart_major = ((word & NVM_DS_MAJOR_MASK) >> NVM_DS_SHIFT);
5534 nvm_ver->devstart_minor = (word & NVM_DS_MINOR_MASK);
5537 if (ixgbe_read_eeprom(hw, NVM_OEM_OFFSET, &nvm_ver->oem_specific))
5538 nvm_ver->oem_specific = NVM_VER_INVALID;
5543 nvm_ver->phy_vend_maj = ((phy_ver & NVM_PHYVEND_MAJOR_MASK)
5545 nvm_ver->phy_vend_min = (phy_ver & NVM_PHYVEND_MINOR_MASK);
5553 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5577 if (hw->mac.type != ixgbe_mac_82598EB) {
5582 hw->mac.set_lben = true;
5584 hw->mac.set_lben = false;
5600 if (hw->mac.type != ixgbe_mac_82598EB) {
5601 if (hw->mac.set_lben) {
5605 hw->mac.set_lben = false;
5611 * ixgbe_mng_present - returns true when management capability is present
5618 if (hw->mac.type < ixgbe_mac_82599EB)
5627 * ixgbe_mng_enabled - Is the manageability engine enabled?
5644 if (hw->mac.type <= ixgbe_mac_X540) {
5654 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5659 * Set the link speed in the MAC and/or PHY register and restarts link.
5674 /* Mask off requested but non-supported speeds */
5689 switch (hw->phy.media_type) {
5696 /* QSFP module automatically detects MAC link speed */
5703 /* Allow module to change analog characteristics (1G->10G) */
5740 switch (hw->phy.media_type) {
5754 /* Allow module to change analog characteristics (10G->1G) */
5789 hw->phy.autoneg_advertised = 0;
5792 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5795 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5801 * ixgbe_set_soft_rate_select_speed - Set module link speed
5827 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5837 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5846 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5856 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,