Lines Matching full:hw
41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
65 * @hw: pointer to the hardware structure
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
157 * @hw: pointer to hardware structure
163 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
171 switch (hw->phy.media_type) {
176 switch (hw->device_id) {
184 hw->mac.ops.check_link(hw, &speed, &link_up, false);
195 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI)
202 switch (hw->device_id) {
225 hw->device_id);
232 * @hw: pointer to hardware structure
236 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
246 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
257 if (hw->fc.requested_mode == ixgbe_fc_default)
258 hw->fc.requested_mode = ixgbe_fc_full;
262 * HW will be able to do fc autoneg once the cable is plugged in. If
265 switch (hw->phy.media_type) {
268 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
272 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
277 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
281 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
298 switch (hw->fc.requested_mode) {
302 if (hw->phy.media_type == ixgbe_media_type_backplane)
305 else if (hw->phy.media_type == ixgbe_media_type_copper)
315 if (hw->phy.media_type == ixgbe_media_type_backplane) {
318 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
336 if (hw->phy.media_type == ixgbe_media_type_backplane)
339 else if (hw->phy.media_type == ixgbe_media_type_copper)
350 if (hw->mac.type < ixgbe_mac_X540) {
355 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
356 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
359 if (hw->fc.strict_ieee)
362 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
371 if (hw->phy.media_type == ixgbe_media_type_backplane) {
373 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
376 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
377 (ixgbe_device_supports_autoneg_fc(hw))) {
378 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
389 * @hw: pointer to hardware structure
396 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
405 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
410 hw->mac.ops.clear_vfta(hw);
413 hw->mac.ops.clear_hw_cntrs(hw);
416 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
418 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
419 IXGBE_WRITE_FLUSH(hw);
422 ret_val = ixgbe_setup_fc(hw);
429 switch (hw->mac.type) {
433 hw->mac.ops.get_device_caps(hw, &device_caps);
435 hw->need_crosstalk_fix = false;
437 hw->need_crosstalk_fix = true;
440 hw->need_crosstalk_fix = false;
445 hw->adapter_stopped = false;
452 * @hw: pointer to hw structure
460 void ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
466 for (i = 0; i < hw->mac.max_tx_queues; i++) {
467 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
468 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
470 IXGBE_WRITE_FLUSH(hw);
473 for (i = 0; i < hw->mac.max_tx_queues; i++) {
474 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
476 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
479 for (i = 0; i < hw->mac.max_rx_queues; i++) {
480 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
483 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
489 * @hw: pointer to hardware structure
497 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
504 status = hw->mac.ops.reset_hw(hw);
507 /* Start the HW */
508 status = hw->mac.ops.start_hw(hw);
512 if (hw->mac.ops.init_led_link_act)
513 hw->mac.ops.init_led_link_act(hw);
516 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status);
523 * @hw: pointer to hardware structure
528 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
534 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
535 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
536 IXGBE_READ_REG(hw, IXGBE_ERRBC);
537 IXGBE_READ_REG(hw, IXGBE_MSPDC);
539 IXGBE_READ_REG(hw, IXGBE_MPC(i));
541 IXGBE_READ_REG(hw, IXGBE_MLFC);
542 IXGBE_READ_REG(hw, IXGBE_MRFC);
543 IXGBE_READ_REG(hw, IXGBE_RLEC);
544 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
545 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
546 if (hw->mac.type >= ixgbe_mac_82599EB) {
547 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
548 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
550 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
551 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
555 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
556 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
557 if (hw->mac.type >= ixgbe_mac_82599EB) {
558 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
559 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
561 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
562 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
565 if (hw->mac.type >= ixgbe_mac_82599EB)
567 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
568 IXGBE_READ_REG(hw, IXGBE_PRC64);
569 IXGBE_READ_REG(hw, IXGBE_PRC127);
570 IXGBE_READ_REG(hw, IXGBE_PRC255);
571 IXGBE_READ_REG(hw, IXGBE_PRC511);
572 IXGBE_READ_REG(hw, IXGBE_PRC1023);
573 IXGBE_READ_REG(hw, IXGBE_PRC1522);
574 IXGBE_READ_REG(hw, IXGBE_GPRC);
575 IXGBE_READ_REG(hw, IXGBE_BPRC);
576 IXGBE_READ_REG(hw, IXGBE_MPRC);
577 IXGBE_READ_REG(hw, IXGBE_GPTC);
578 IXGBE_READ_REG(hw, IXGBE_GORCL);
579 IXGBE_READ_REG(hw, IXGBE_GORCH);
580 IXGBE_READ_REG(hw, IXGBE_GOTCL);
581 IXGBE_READ_REG(hw, IXGBE_GOTCH);
582 if (hw->mac.type == ixgbe_mac_82598EB)
584 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
585 IXGBE_READ_REG(hw, IXGBE_RUC);
586 IXGBE_READ_REG(hw, IXGBE_RFC);
587 IXGBE_READ_REG(hw, IXGBE_ROC);
588 IXGBE_READ_REG(hw, IXGBE_RJC);
589 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
590 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
591 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
592 IXGBE_READ_REG(hw, IXGBE_TORL);
593 IXGBE_READ_REG(hw, IXGBE_TORH);
594 IXGBE_READ_REG(hw, IXGBE_TPR);
595 IXGBE_READ_REG(hw, IXGBE_TPT);
596 IXGBE_READ_REG(hw, IXGBE_PTC64);
597 IXGBE_READ_REG(hw, IXGBE_PTC127);
598 IXGBE_READ_REG(hw, IXGBE_PTC255);
599 IXGBE_READ_REG(hw, IXGBE_PTC511);
600 IXGBE_READ_REG(hw, IXGBE_PTC1023);
601 IXGBE_READ_REG(hw, IXGBE_PTC1522);
602 IXGBE_READ_REG(hw, IXGBE_MPTC);
603 IXGBE_READ_REG(hw, IXGBE_BPTC);
605 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
606 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
607 if (hw->mac.type >= ixgbe_mac_82599EB) {
608 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
609 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
610 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
611 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
612 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
614 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
615 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
619 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
620 if (hw->phy.id == 0)
621 ixgbe_identify_phy(hw);
622 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
624 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
626 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
628 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
637 * @hw: pointer to hardware structure
643 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
659 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
665 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
711 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
717 if (length == 0xFFFF || length == 0 || length > hw->eeprom.word_size) {
733 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
748 * @hw: pointer to hardware structure
753 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
760 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
770 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
782 * @hw: pointer to the HW structure
792 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
803 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
820 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
830 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
852 * @hw: pointer to the HW structure
861 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
870 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
888 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
910 * @hw: pointer to the HW structure
920 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
930 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
945 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
971 * @hw: pointer to hardware structure
978 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
986 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
987 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
1000 * @hw: pointer to hardware structure
1005 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
1007 struct ixgbe_mac_info *mac = &hw->mac;
1009 if (hw->bus.type == ixgbe_bus_type_unknown)
1010 hw->bus.type = ixgbe_bus_type_pci_express;
1014 hw->bus.width = ixgbe_bus_width_pcie_x1;
1017 hw->bus.width = ixgbe_bus_width_pcie_x2;
1020 hw->bus.width = ixgbe_bus_width_pcie_x4;
1023 hw->bus.width = ixgbe_bus_width_pcie_x8;
1026 hw->bus.width = ixgbe_bus_width_unknown;
1032 hw->bus.speed = ixgbe_bus_speed_2500;
1035 hw->bus.speed = ixgbe_bus_speed_5000;
1038 hw->bus.speed = ixgbe_bus_speed_8000;
1041 hw->bus.speed = ixgbe_bus_speed_unknown;
1045 mac->ops.set_lan_id(hw);
1050 * @hw: pointer to hardware structure
1055 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1062 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1064 ixgbe_set_pci_config_data_generic(hw, link_status);
1071 * @hw: pointer to the HW structure
1077 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1079 struct ixgbe_bus_info *bus = &hw->bus;
1085 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1090 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
1095 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
1096 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
1104 * @hw: pointer to hardware structure
1111 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1122 hw->adapter_stopped = true;
1125 ixgbe_disable_rx(hw);
1128 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1131 IXGBE_READ_REG(hw, IXGBE_EICR);
1134 for (i = 0; i < hw->mac.max_tx_queues; i++)
1135 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1138 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1139 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1146 IXGBE_WRITE_FLUSH(hw);
1153 return ixgbe_disable_pcie_primary(hw);
1158 * @hw: pointer to hardware structure
1163 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw)
1165 struct ixgbe_mac_info *mac = &hw->mac;
1169 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1186 switch (hw->mac.type) {
1199 * @hw: pointer to hardware structure
1202 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1204 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1214 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1215 IXGBE_WRITE_FLUSH(hw);
1222 * @hw: pointer to hardware structure
1225 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1227 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1237 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1238 IXGBE_WRITE_FLUSH(hw);
1245 * @hw: pointer to hardware structure
1250 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1252 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1270 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1298 * @hw: pointer to hardware structure
1305 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1313 hw->eeprom.ops.init_params(hw);
1320 if (offset + words > hw->eeprom.word_size) {
1329 if ((hw->eeprom.word_page_size == 0) &&
1331 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1341 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1354 * @hw: pointer to hardware structure
1362 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1374 status = ixgbe_acquire_eeprom(hw);
1377 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1378 ixgbe_release_eeprom(hw);
1385 ixgbe_standby_eeprom(hw);
1388 ixgbe_shift_out_eeprom_bits(hw,
1392 ixgbe_standby_eeprom(hw);
1398 if ((hw->eeprom.address_bits == 8) &&
1403 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1405 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1406 hw->eeprom.address_bits);
1408 page_size = hw->eeprom.word_page_size;
1414 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1425 ixgbe_standby_eeprom(hw);
1429 ixgbe_release_eeprom(hw);
1437 * @hw: pointer to hardware structure
1444 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1450 hw->eeprom.ops.init_params(hw);
1452 if (offset >= hw->eeprom.word_size) {
1457 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1465 * @hw: pointer to hardware structure
1472 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1480 hw->eeprom.ops.init_params(hw);
1487 if (offset + words > hw->eeprom.word_size) {
1501 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1514 * @hw: pointer to hardware structure
1521 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1532 status = ixgbe_acquire_eeprom(hw);
1535 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1536 ixgbe_release_eeprom(hw);
1543 ixgbe_standby_eeprom(hw);
1548 if ((hw->eeprom.address_bits == 8) &&
1553 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1555 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1556 hw->eeprom.address_bits);
1559 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1564 ixgbe_release_eeprom(hw);
1572 * @hw: pointer to hardware structure
1578 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1585 hw->eeprom.ops.init_params(hw);
1587 if (offset >= hw->eeprom.word_size) {
1592 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1600 * @hw: pointer to hardware structure
1607 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1616 hw->eeprom.ops.init_params(hw);
1624 if (offset >= hw->eeprom.word_size) {
1634 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1635 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1638 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1651 * @hw: pointer to hardware structure
1658 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1670 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1671 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1673 hw->eeprom.word_page_size = 0;
1677 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1685 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1688 hw->eeprom.word_page_size);
1695 * @hw: pointer to hardware structure
1701 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1703 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1708 * @hw: pointer to hardware structure
1715 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1724 hw->eeprom.ops.init_params(hw);
1732 if (offset >= hw->eeprom.word_size) {
1743 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1749 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1751 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1764 * @hw: pointer to hardware structure
1770 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1772 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1777 * @hw: pointer to hardware structure
1783 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1793 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1795 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1813 * @hw: pointer to hardware structure
1818 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1826 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1831 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1835 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1838 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
1847 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1850 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1858 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
1859 IXGBE_WRITE_FLUSH(hw);
1868 * @hw: pointer to hardware structure
1872 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1888 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1905 ixgbe_release_eeprom_semaphore(hw);
1913 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1921 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1925 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
1931 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
1945 ixgbe_release_eeprom_semaphore(hw);
1959 * @hw: pointer to hardware structure
1963 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1969 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1973 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1974 IXGBE_WRITE_FLUSH(hw);
1979 * @hw: pointer to hardware structure
1981 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1996 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1998 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
2003 ixgbe_standby_eeprom(hw);
2020 * @hw: pointer to hardware structure
2022 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
2028 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2032 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2033 IXGBE_WRITE_FLUSH(hw);
2036 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2037 IXGBE_WRITE_FLUSH(hw);
2043 * @hw: pointer to hardware structure
2047 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
2056 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2077 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2078 IXGBE_WRITE_FLUSH(hw);
2082 ixgbe_raise_eeprom_clk(hw, &eec);
2083 ixgbe_lower_eeprom_clk(hw, &eec);
2094 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2095 IXGBE_WRITE_FLUSH(hw);
2100 * @hw: pointer to hardware structure
2103 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2118 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2124 ixgbe_raise_eeprom_clk(hw, &eec);
2126 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2132 ixgbe_lower_eeprom_clk(hw, &eec);
2140 * @hw: pointer to hardware structure
2143 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2152 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2153 IXGBE_WRITE_FLUSH(hw);
2159 * @hw: pointer to hardware structure
2162 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2171 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
2172 IXGBE_WRITE_FLUSH(hw);
2178 * @hw: pointer to hardware structure
2180 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2186 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
2191 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2192 IXGBE_WRITE_FLUSH(hw);
2198 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
2200 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2203 msec_delay(hw->eeprom.semaphore_delay);
2208 * @hw: pointer to hardware structure
2212 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2225 if (hw->eeprom.ops.read(hw, i, &word)) {
2234 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2243 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2252 if (hw->eeprom.ops.read(hw, j, &word)) {
2267 * @hw: pointer to hardware structure
2273 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2286 status = hw->eeprom.ops.read(hw, 0, &checksum);
2292 status = hw->eeprom.ops.calc_checksum(hw);
2298 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2319 * @hw: pointer to hardware structure
2321 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2332 status = hw->eeprom.ops.read(hw, 0, &checksum);
2338 status = hw->eeprom.ops.calc_checksum(hw);
2344 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2377 * @hw: pointer to hardware structure
2385 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2389 u32 rar_entries = hw->mac.num_rar_entries;
2401 hw->mac.ops.set_vmdq(hw, index, vmdq);
2404 * HW expects these in little endian so we reverse the byte
2416 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2423 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2424 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2431 * @hw: pointer to hardware structure
2436 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2439 u32 rar_entries = hw->mac.num_rar_entries;
2455 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2458 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2459 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2462 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2469 * @hw: pointer to hardware structure
2475 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2478 u32 rar_entries = hw->mac.num_rar_entries;
2487 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2490 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2493 hw->mac.addr[0], hw->mac.addr[1],
2494 hw->mac.addr[2]);
2495 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2496 hw->mac.addr[4], hw->mac.addr[5]);
2501 hw->mac.addr[0], hw->mac.addr[1],
2502 hw->mac.addr[2]);
2503 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2504 hw->mac.addr[4], hw->mac.addr[5]);
2506 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2510 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2512 hw->addr_ctrl.overflow_promisc = 0;
2514 hw->addr_ctrl.rar_used_count = 1;
2519 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2520 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2524 hw->addr_ctrl.mta_in_use = 0;
2525 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2528 for (i = 0; i < hw->mac.mcft_size; i++)
2529 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2531 ixgbe_init_uta_tables(hw);
2538 * @hw: pointer to hardware structure
2544 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2546 u32 rar_entries = hw->mac.num_rar_entries;
2558 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2559 rar = hw->addr_ctrl.rar_used_count;
2560 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2562 hw->addr_ctrl.rar_used_count++;
2564 hw->addr_ctrl.overflow_promisc++;
2572 * @hw: pointer to hardware structure
2584 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2589 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2600 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2601 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2602 hw->addr_ctrl.overflow_promisc = 0;
2607 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2608 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2614 addr = next(hw, &addr_list, &vmdq);
2615 ixgbe_add_uc_addr(hw, addr, vmdq);
2618 if (hw->addr_ctrl.overflow_promisc) {
2620 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2622 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2624 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2628 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2630 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2632 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2642 * @hw: pointer to hardware structure
2652 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2658 switch (hw->mac.mc_filter_type) {
2684 * @hw: pointer to hardware structure
2689 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2697 hw->addr_ctrl.mta_in_use++;
2699 vector = ixgbe_mta_vector(hw, mc_addr);
2713 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2718 * @hw: pointer to hardware structure
2727 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2740 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2741 hw->addr_ctrl.mta_in_use = 0;
2746 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2752 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2756 for (i = 0; i < hw->mac.mcft_size; i++)
2757 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2758 hw->mac.mta_shadow[i]);
2760 if (hw->addr_ctrl.mta_in_use > 0)
2761 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2762 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2770 * @hw: pointer to hardware structure
2774 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2776 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2781 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2782 hw->mac.mc_filter_type);
2789 * @hw: pointer to hardware structure
2793 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2795 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2800 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2807 * @hw: pointer to hardware structure
2811 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2822 if (!hw->fc.pause_time) {
2829 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2830 hw->fc.high_water[i]) {
2831 if (!hw->fc.low_water[i] ||
2832 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2841 hw->mac.ops.fc_autoneg(hw);
2844 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2847 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2860 switch (hw->fc.current_mode) {
2864 * The code below will actually disable it in the HW.
2900 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2901 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2906 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2907 hw->fc.high_water[i]) {
2908 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2909 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2910 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2912 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2920 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2923 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2927 reg = hw->fc.pause_time * 0x00010001;
2929 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2932 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2940 * @hw: pointer to hardware structure
2951 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2970 if (hw->fc.requested_mode == ixgbe_fc_full) {
2971 hw->fc.current_mode = ixgbe_fc_full;
2974 hw->fc.current_mode = ixgbe_fc_rx_pause;
2979 hw->fc.current_mode = ixgbe_fc_tx_pause;
2983 hw->fc.current_mode = ixgbe_fc_rx_pause;
2986 hw->fc.current_mode = ixgbe_fc_none;
2994 * @hw: pointer to hardware structure
2998 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
3009 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
3016 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
3017 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
3019 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
3031 * @hw: pointer to hardware structure
3035 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
3045 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
3051 if (hw->mac.type == ixgbe_mac_82599EB) {
3052 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
3062 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3063 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
3065 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
3075 * @hw: pointer to hardware structure
3079 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
3084 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
3087 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
3091 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
3099 * @hw: pointer to hardware structure
3104 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3118 if (hw->fc.disable_fc_autoneg) {
3125 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3131 switch (hw->phy.media_type) {
3137 ret_val = ixgbe_fc_autoneg_fiber(hw);
3142 ret_val = ixgbe_fc_autoneg_backplane(hw);
3147 if (ixgbe_device_supports_autoneg_fc(hw))
3148 ret_val = ixgbe_fc_autoneg_copper(hw);
3157 hw->fc.fc_was_autonegged = true;
3159 hw->fc.fc_was_autonegged = false;
3160 hw->fc.current_mode = hw->fc.requested_mode;
3166 * @hw: pointer to hardware structure
3174 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3179 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3213 * @hw: pointer to hardware structure
3220 s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw)
3229 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3232 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3233 IXGBE_REMOVED(hw->hw_addr))
3239 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3252 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3254 if (hw->mac.type >= ixgbe_mac_X550)
3261 poll = ixgbe_pcie_timeout_poll(hw);
3264 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3265 if (IXGBE_REMOVED(hw->hw_addr))
3281 * @hw: pointer to hardware structure
3287 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3302 if (ixgbe_get_eeprom_semaphore(hw))
3305 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3308 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3309 ixgbe_release_eeprom_semaphore(hw);
3313 ixgbe_release_eeprom_semaphore(hw);
3320 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3328 * @hw: pointer to hardware structure
3334 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3341 ixgbe_get_eeprom_semaphore(hw);
3343 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3345 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3347 ixgbe_release_eeprom_semaphore(hw);
3352 * @hw: pointer to hardware structure
3354 * Stops the receive data path and waits for the HW to internally empty
3357 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3367 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3369 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3371 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3389 * @hw: pointer to hardware structure
3395 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3398 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3404 * @hw: pointer to hardware structure
3411 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3415 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3421 * @hw: pointer to hardware structure
3425 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3431 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3433 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3434 IXGBE_WRITE_FLUSH(hw);
3441 * @hw: pointer to hardware structure
3446 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3451 ixgbe_enable_rx(hw);
3453 ixgbe_disable_rx(hw);
3460 * @hw: pointer to hardware structure
3463 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3468 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3481 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3484 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3491 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3495 IXGBE_WRITE_FLUSH(hw);
3501 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3502 IXGBE_WRITE_FLUSH(hw);
3510 * @hw: pointer to hardware structure
3513 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3516 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3525 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3532 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3539 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3540 IXGBE_WRITE_FLUSH(hw);
3548 * @hw: pointer to hardware structure
3555 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3566 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3579 * @hw: pointer to hardware structure
3587 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3599 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3604 hw->mac.ops.set_lan_id(hw);
3606 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3609 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3635 * @hw: pointer to hardware structure
3640 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3649 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3654 hw->mac.ops.set_lan_id(hw);
3656 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3662 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3671 * @hw: pointer to hardware structure
3676 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3682 switch (hw->mac.type) {
3700 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3701 if (IXGBE_REMOVED(hw->hw_addr))
3705 /* MSI-X count is zero-based in HW */
3716 * @hw: pointer to hardware structure
3723 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3733 /* swap bytes for HW little endian */
3745 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3746 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3752 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3758 if (rar < hw->mac.rar_highwater) {
3760 ixgbe_set_vmdq(hw, rar, vmdq);
3764 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3765 } else if (rar == hw->mac.rar_highwater) {
3767 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3768 hw->mac.rar_highwater++;
3769 } else if (rar >= hw->mac.num_rar_entries) {
3778 ixgbe_clear_vmdq(hw, rar, 0);
3785 * @hw: pointer to hardware struct
3789 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3792 u32 rar_entries = hw->mac.num_rar_entries;
3803 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3804 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3806 if (IXGBE_REMOVED(hw->hw_addr))
3814 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3815 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3818 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3819 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3823 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3826 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3831 rar != 0 && rar != hw->mac.san_mac_rar_index)
3832 hw->mac.ops.clear_rar(hw, rar);
3839 * @hw: pointer to hardware struct
3843 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3846 u32 rar_entries = hw->mac.num_rar_entries;
3858 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3860 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3862 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3864 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3872 * @hw: pointer to hardware struct
3878 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3880 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3882 u32 rar = hw->mac.san_mac_rar_index;
3887 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3888 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3890 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3891 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3899 * @hw: pointer to hardware structure
3901 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3909 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3916 * @hw: pointer to hardware structure
3925 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3949 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3967 * @hw: pointer to hardware structure
3975 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4000 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
4013 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta,
4024 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
4031 * @hw: pointer to hardware structure
4042 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
4061 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
4064 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
4068 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
4079 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
4085 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta);
4088 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4089 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
4112 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
4113 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
4120 * @hw: pointer to hardware structure
4124 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4130 for (offset = 0; offset < hw->mac.vft_size; offset++)
4131 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4134 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4135 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4136 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
4145 * @hw: pointer to hardware structure
4150 s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number)
4162 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4183 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
4185 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
4186 IXGBE_WRITE_FLUSH(hw);
4189 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset));
4191 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg);
4192 IXGBE_WRITE_FLUSH(hw);
4200 * @hw: pointer to hardware structure
4205 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
4209 if (!hw->need_crosstalk_fix)
4213 switch (hw->mac.ops.get_media_type(hw)) {
4226 * @hw: pointer to hardware structure
4233 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4244 if (ixgbe_need_crosstalk_fix(hw)) {
4247 switch (hw->mac.type) {
4249 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4254 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
4271 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4273 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4281 for (i = 0; i < hw->mac.max_link_up_time; i++) {
4289 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4293 if (ixgbe_need_crosstalk_fix(hw)) {
4299 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4316 if (hw->mac.type >= ixgbe_mac_X550) {
4326 if (hw->mac.type == ixgbe_mac_X550) {
4333 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4334 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4347 * @hw: pointer to hardware structure
4354 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4368 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4377 if (hw->eeprom.ops.read(hw, offset, &caps))
4384 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4390 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4404 * @hw: pointer to hardware structure
4409 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4421 status = hw->eeprom.ops.read(hw, offset, &caps);
4429 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4438 status = hw->eeprom.ops.read(hw, offset, &flags);
4453 * @hw: pointer to hardware structure
4458 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4464 if (hw->mac.type == ixgbe_mac_82598EB)
4467 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4472 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4477 * @hw: pointer to hardware structure
4482 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4488 if (hw->mac.type == ixgbe_mac_82598EB)
4491 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4496 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4501 * @hw: pointer to hardware structure
4507 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4511 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4518 * @hw: pointer to hardware structure
4521 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4529 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4530 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4532 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4535 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4536 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4539 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4569 * @hw: pointer to the HW structure
4581 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length,
4595 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4596 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4599 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4617 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4621 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4624 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4639 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4650 * @hw: pointer to the HW structure
4666 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4684 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4688 status = ixgbe_hic_unlocked(hw, buffer, length, timeout);
4700 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4712 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4736 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4741 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4748 * @hw: pointer to the HW structure
4761 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4775 fw_cmd.port_num = (u8)hw->bus.func;
4787 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4808 * @hw: pointer to hardware structure
4813 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4816 u32 pbsize = hw->mac.rx_pb_size;
4838 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4841 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4846 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4856 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4857 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4862 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4863 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4864 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4870 * @hw: pointer to the hardware structure
4876 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4885 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4893 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4894 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4897 IXGBE_WRITE_FLUSH(hw);
4904 poll = ixgbe_pcie_timeout_poll(hw);
4907 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4908 if (IXGBE_REMOVED(hw->hw_addr))
4916 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4917 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4921 IXGBE_WRITE_FLUSH(hw);
4925 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4926 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4944 * @hw: pointer to hardware structure
4948 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4958 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4963 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4964 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4969 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4978 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4993 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
5004 status = hw->phy.ops.read_i2c_byte(hw,
5018 * @hw: pointer to hardware structure
5023 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
5036 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
5043 if ((hw->mac.type != ixgbe_mac_82599EB) ||
5044 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
5048 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
5054 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
5066 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
5078 hw->phy.ops.write_i2c_byte(hw,
5100 * @hw: pointer to hardware structure
5107 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)
5119 switch (hw->mac.type) {
5141 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5147 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5148 IXGBE_WRITE_FLUSH(hw);
5153 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5154 IXGBE_WRITE_FLUSH(hw);
5158 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5159 IXGBE_WRITE_FLUSH(hw);
5166 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5169 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5171 IXGBE_WRITE_FLUSH(hw);
5175 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5176 IXGBE_WRITE_FLUSH(hw);
5180 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5181 IXGBE_WRITE_FLUSH(hw);
5184 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5195 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5196 IXGBE_WRITE_FLUSH(hw);
5200 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
5201 IXGBE_WRITE_FLUSH(hw);
5268 * @hw: pointer to hardware structure
5276 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,
5285 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5290 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))
5300 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl))
5314 * @hw: pointer to hardware structure
5318 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)
5327 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5335 if (ixgbe_bypass_rw_generic(hw, cmd, &status))
5346 * @hw: pointer to hardware structure
5352 void ixgbe_get_orom_version(struct ixgbe_hw *hw,
5359 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset);
5365 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh);
5366 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl);
5384 * @hw: pointer to hardware structure
5390 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
5396 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset);
5403 hw->eeprom.ops.read(hw, offset, &mod_len);
5404 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap);
5411 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver);
5412 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num);
5428 * @hw: pointer to hardware structure
5433 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver)
5437 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l))
5439 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h))
5457 * @hw: pointer to hardware structure
5462 void ixgbe_get_nvm_version(struct ixgbe_hw *hw,
5472 switch (hw->mac.type) {
5475 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_82598, &word))
5485 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word))
5498 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word))
5510 switch (hw->mac.type) {
5516 if (ixgbe_read_eeprom(hw, NVM_EEP_PHY_OFF_X540, &word))
5528 ixgbe_get_etk_id(hw, nvm_ver);
5531 if (ixgbe_read_eeprom(hw, NVM_DS_OFFSET, &word))
5537 if (ixgbe_read_eeprom(hw, NVM_OEM_OFFSET, &nvm_ver->oem_specific))
5541 if (ixgbe_get_phy_firmware_version(hw, &phy_ver))
5548 ixgbe_get_orom_version(hw, nvm_ver);
5554 * @hw: pointer to hardware structure
5557 * Read the rtrup2tc HW register and resolve its content into map
5559 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
5563 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
5570 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
5575 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5577 if (hw->mac.type != ixgbe_mac_82598EB) {
5578 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5581 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5582 hw->mac.set_lben = true;
5584 hw->mac.set_lben = false;
5588 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
5592 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
5597 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5598 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
5600 if (hw->mac.type != ixgbe_mac_82598EB) {
5601 if (hw->mac.set_lben) {
5602 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5604 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
5605 hw->mac.set_lben = false;
5612 * @hw: pointer to hardware structure
5614 bool ixgbe_mng_present(struct ixgbe_hw *hw)
5618 if (hw->mac.type < ixgbe_mac_82599EB)
5621 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5628 * @hw: pointer to hardware structure
5632 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
5636 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
5640 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
5644 if (hw->mac.type <= ixgbe_mac_X540) {
5645 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
5655 * @hw: pointer to hardware structure
5661 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
5675 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
5689 switch (hw->phy.media_type) {
5692 ixgbe_set_rate_select_speed(hw,
5706 status = ixgbe_setup_mac_link(hw,
5713 ixgbe_flap_tx_laser(hw);
5724 status = ixgbe_check_link(hw, &link_speed,
5740 switch (hw->phy.media_type) {
5743 ixgbe_set_rate_select_speed(hw,
5757 status = ixgbe_setup_mac_link(hw,
5764 ixgbe_flap_tx_laser(hw);
5770 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
5783 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
5789 hw->phy.autoneg_advertised = 0;
5792 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
5795 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
5802 * @hw: pointer to hardware structure
5807 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
5827 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5837 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
5846 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
5856 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,